ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>

include/configs/rpi.h

@@ -7,6 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE		32
+
 #include "rpi-common.h"
 
 #endif

include/configs/rpi_2.h

@@ -9,6 +9,7 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BCM2836
+#define CONFIG_SYS_CACHELINE_SIZE		64
 
 #include "rpi-common.h"