提交 553e9c18 编写于 作者: A Andy Shevchenko 提交者: Darren Hart

platform/x86: intel_mid_powerbtn: Acknowledge interrupts

Some platforms require interrupt to be acknowledged by clearing
MSIC_PWRBTNM bit in interrupt level 1 mask register.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
上级 4b819c6d
...@@ -94,6 +94,7 @@ static irqreturn_t mid_pb_isr(int irq, void *dev_id) ...@@ -94,6 +94,7 @@ static irqreturn_t mid_pb_isr(int irq, void *dev_id)
input_sync(input); input_sync(input);
} }
ddata->ack(ddata);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册