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由 Andy Shevchenko 提交于
Some platforms require interrupt to be acknowledged by clearing MSIC_PWRBTNM bit in interrupt level 1 mask register. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>553e9c18
Some platforms require interrupt to be acknowledged by clearing
MSIC_PWRBTNM bit in interrupt level 1 mask register.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>