rt61pci.c 94.2 KB
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/*
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	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
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	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt61pci
	Abstract: rt61pci device specific routines.
	Supported chipsets: RT2561, RT2561s, RT2661.
 */

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#include <linux/crc-itu-t.h>
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#include <linux/delay.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
#include <linux/eeprom_93cx6.h>

#include "rt2x00.h"
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#include "rt2x00mmio.h"
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#include "rt2x00pci.h"
#include "rt61pci.h"

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/*
 * Allow hardware encryption to be disabled.
 */
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static bool modparam_nohwcrypt = false;
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module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");

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/*
 * Register access.
 * BBP and RF register require indirect register access,
 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
 * These indirect registers work with busy bits,
 * and we will try maximal REGISTER_BUSY_COUNT times to access
 * the register while taking a REGISTER_BUSY_DELAY us delay
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 * between each attempt. When the busy bit is still set at that time,
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 * the access attempt is considered to have failed,
 * and we will print an error.
 */
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#define WAIT_FOR_BBP(__dev, __reg) \
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	rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
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#define WAIT_FOR_RF(__dev, __reg) \
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	rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
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#define WAIT_FOR_MCU(__dev, __reg) \
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	rt2x00mmio_regbusy_read((__dev), H2M_MAILBOX_CSR, \
				H2M_MAILBOX_CSR_OWNER, (__reg))
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static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
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			      const unsigned int word, const u8 value)
{
	u32 reg;

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	mutex_lock(&rt2x00dev->csr_mutex);

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	/*
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	 * Wait until the BBP becomes available, afterwards we
	 * can safely write the new data into the register.
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	 */
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	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
		rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
		rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
		rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);

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		rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
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	}
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	mutex_unlock(&rt2x00dev->csr_mutex);
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}

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static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
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			     const unsigned int word, u8 *value)
{
	u32 reg;

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	mutex_lock(&rt2x00dev->csr_mutex);

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	/*
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	 * Wait until the BBP becomes available, afterwards we
	 * can safely write the read request into the register.
	 * After the data has been written, we wait until hardware
	 * returns the correct value, if at any time the register
	 * doesn't become available in time, reg will be 0xffffffff
	 * which means we return 0xff to the caller.
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	 */
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	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
		rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
		rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
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		rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
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		WAIT_FOR_BBP(rt2x00dev, &reg);
	}
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	*value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
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	mutex_unlock(&rt2x00dev->csr_mutex);
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}

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static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
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			     const unsigned int word, const u32 value)
{
	u32 reg;

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	mutex_lock(&rt2x00dev->csr_mutex);

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	/*
	 * Wait until the RF becomes available, afterwards we
	 * can safely write the new data into the register.
	 */
	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
		rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
		rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
		rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);

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		rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg);
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		rt2x00_rf_write(rt2x00dev, word, value);
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	}

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	mutex_unlock(&rt2x00dev->csr_mutex);
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}

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static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
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				const u8 command, const u8 token,
				const u8 arg0, const u8 arg1)
{
	u32 reg;

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	mutex_lock(&rt2x00dev->csr_mutex);

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	/*
	 * Wait until the MCU becomes available, afterwards we
	 * can safely write the new data into the register.
	 */
	if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
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		rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
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		rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
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		rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
		rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
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		rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg);
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	}
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	mutex_unlock(&rt2x00dev->csr_mutex);

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}

static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
{
	struct rt2x00_dev *rt2x00dev = eeprom->data;
	u32 reg;

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	rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
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	eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
	eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
	eeprom->reg_data_clock =
	    !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
	eeprom->reg_chip_select =
	    !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
}

static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
{
	struct rt2x00_dev *rt2x00dev = eeprom->data;
	u32 reg = 0;

	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
	rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
			   !!eeprom->reg_data_clock);
	rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
			   !!eeprom->reg_chip_select);

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	rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
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}

#ifdef CONFIG_RT2X00_LIB_DEBUGFS
static const struct rt2x00debug rt61pci_rt2x00debug = {
	.owner	= THIS_MODULE,
	.csr	= {
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		.read		= rt2x00mmio_register_read,
		.write		= rt2x00mmio_register_write,
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		.flags		= RT2X00DEBUGFS_OFFSET,
		.word_base	= CSR_REG_BASE,
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		.word_size	= sizeof(u32),
		.word_count	= CSR_REG_SIZE / sizeof(u32),
	},
	.eeprom	= {
		.read		= rt2x00_eeprom_read,
		.write		= rt2x00_eeprom_write,
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		.word_base	= EEPROM_BASE,
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		.word_size	= sizeof(u16),
		.word_count	= EEPROM_SIZE / sizeof(u16),
	},
	.bbp	= {
		.read		= rt61pci_bbp_read,
		.write		= rt61pci_bbp_write,
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		.word_base	= BBP_BASE,
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		.word_size	= sizeof(u8),
		.word_count	= BBP_SIZE / sizeof(u8),
	},
	.rf	= {
		.read		= rt2x00_rf_read,
		.write		= rt61pci_rf_write,
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		.word_base	= RF_BASE,
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		.word_size	= sizeof(u32),
		.word_count	= RF_SIZE / sizeof(u32),
	},
};
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */

static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;

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	rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
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	return rt2x00_get_field32(reg, MAC_CSR13_VAL5);
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}

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#ifdef CONFIG_RT2X00_LIB_LEDS
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static void rt61pci_brightness_set(struct led_classdev *led_cdev,
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				   enum led_brightness brightness)
{
	struct rt2x00_led *led =
	    container_of(led_cdev, struct rt2x00_led, led_dev);
	unsigned int enabled = brightness != LED_OFF;
	unsigned int a_mode =
	    (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
	unsigned int bg_mode =
	    (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);

	if (led->type == LED_TYPE_RADIO) {
		rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
				   MCU_LEDCS_RADIO_STATUS, enabled);

		rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
				    (led->rt2x00dev->led_mcu_reg & 0xff),
				    ((led->rt2x00dev->led_mcu_reg >> 8)));
	} else if (led->type == LED_TYPE_ASSOC) {
		rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
				   MCU_LEDCS_LINK_BG_STATUS, bg_mode);
		rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
				   MCU_LEDCS_LINK_A_STATUS, a_mode);

		rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
				    (led->rt2x00dev->led_mcu_reg & 0xff),
				    ((led->rt2x00dev->led_mcu_reg >> 8)));
	} else if (led->type == LED_TYPE_QUALITY) {
		/*
		 * The brightness is divided into 6 levels (0 - 5),
		 * this means we need to convert the brightness
		 * argument into the matching level within that range.
		 */
		rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
				    brightness / (LED_FULL / 6), 0);
	}
}
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static int rt61pci_blink_set(struct led_classdev *led_cdev,
			     unsigned long *delay_on,
			     unsigned long *delay_off)
{
	struct rt2x00_led *led =
	    container_of(led_cdev, struct rt2x00_led, led_dev);
	u32 reg;

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	rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, &reg);
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	rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
	rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
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	rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg);
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	return 0;
}
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static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
			     struct rt2x00_led *led,
			     enum led_type type)
{
	led->rt2x00dev = rt2x00dev;
	led->type = type;
	led->led_dev.brightness_set = rt61pci_brightness_set;
	led->led_dev.blink_set = rt61pci_blink_set;
	led->flags = LED_INITIALIZED;
}
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#endif /* CONFIG_RT2X00_LIB_LEDS */
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/*
 * Configuration handlers.
 */
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static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
				     struct rt2x00lib_crypto *crypto,
				     struct ieee80211_key_conf *key)
{
	struct hw_key_entry key_entry;
	struct rt2x00_field32 field;
	u32 mask;
	u32 reg;

	if (crypto->cmd == SET_KEY) {
		/*
		 * rt2x00lib can't determine the correct free
		 * key_idx for shared keys. We have 1 register
		 * with key valid bits. The goal is simple, read
		 * the register, if that is full we have no slots
		 * left.
		 * Note that each BSS is allowed to have up to 4
		 * shared keys, so put a mask over the allowed
		 * entries.
		 */
		mask = (0xf << crypto->bssidx);

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		rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
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		reg &= mask;

		if (reg && reg == mask)
			return -ENOSPC;

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		key->hw_key_idx += reg ? ffz(reg) : 0;
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		/*
		 * Upload key to hardware
		 */
		memcpy(key_entry.key, crypto->key,
		       sizeof(key_entry.key));
		memcpy(key_entry.tx_mic, crypto->tx_mic,
		       sizeof(key_entry.tx_mic));
		memcpy(key_entry.rx_mic, crypto->rx_mic,
		       sizeof(key_entry.rx_mic));

		reg = SHARED_KEY_ENTRY(key->hw_key_idx);
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		rt2x00mmio_register_multiwrite(rt2x00dev, reg,
					       &key_entry, sizeof(key_entry));
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		/*
		 * The cipher types are stored over 2 registers.
		 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
		 * bssidx 1 and 2 keys are stored in SEC_CSR5.
		 * Using the correct defines correctly will cause overhead,
		 * so just calculate the correct offset.
		 */
		if (key->hw_key_idx < 8) {
			field.bit_offset = (3 * key->hw_key_idx);
			field.bit_mask = 0x7 << field.bit_offset;

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			rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, &reg);
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			rt2x00_set_field32(&reg, field, crypto->cipher);
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			rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg);
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		} else {
			field.bit_offset = (3 * (key->hw_key_idx - 8));
			field.bit_mask = 0x7 << field.bit_offset;

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			rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, &reg);
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			rt2x00_set_field32(&reg, field, crypto->cipher);
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			rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg);
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		}

		/*
		 * The driver does not support the IV/EIV generation
		 * in hardware. However it doesn't support the IV/EIV
		 * inside the ieee80211 frame either, but requires it
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		 * to be provided separately for the descriptor.
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		 * rt2x00lib will cut the IV/EIV data out of all frames
		 * given to us by mac80211, but we must tell mac80211
		 * to generate the IV/EIV data.
		 */
		key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
	}

	/*
	 * SEC_CSR0 contains only single-bit fields to indicate
	 * a particular key is valid. Because using the FIELD32()
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	 * defines directly will cause a lot of overhead, we use
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	 * a calculation to determine the correct bit directly.
	 */
	mask = 1 << key->hw_key_idx;

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	rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
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	if (crypto->cmd == SET_KEY)
		reg |= mask;
	else if (crypto->cmd == DISABLE_KEY)
		reg &= ~mask;
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	rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg);
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	return 0;
}

static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
				       struct rt2x00lib_crypto *crypto,
				       struct ieee80211_key_conf *key)
{
	struct hw_pairwise_ta_entry addr_entry;
	struct hw_key_entry key_entry;
	u32 mask;
	u32 reg;

	if (crypto->cmd == SET_KEY) {
		/*
		 * rt2x00lib can't determine the correct free
		 * key_idx for pairwise keys. We have 2 registers
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		 * with key valid bits. The goal is simple: read
		 * the first register. If that is full, move to
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		 * the next register.
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		 * When both registers are full, we drop the key.
		 * Otherwise, we use the first invalid entry.
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		 */
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		rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
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		if (reg && reg == ~0) {
			key->hw_key_idx = 32;
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			rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
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			if (reg && reg == ~0)
				return -ENOSPC;
		}

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		key->hw_key_idx += reg ? ffz(reg) : 0;
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		/*
		 * Upload key to hardware
		 */
		memcpy(key_entry.key, crypto->key,
		       sizeof(key_entry.key));
		memcpy(key_entry.tx_mic, crypto->tx_mic,
		       sizeof(key_entry.tx_mic));
		memcpy(key_entry.rx_mic, crypto->rx_mic,
		       sizeof(key_entry.rx_mic));

		memset(&addr_entry, 0, sizeof(addr_entry));
		memcpy(&addr_entry, crypto->address, ETH_ALEN);
		addr_entry.cipher = crypto->cipher;

		reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
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		rt2x00mmio_register_multiwrite(rt2x00dev, reg,
					       &key_entry, sizeof(key_entry));
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		reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
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		rt2x00mmio_register_multiwrite(rt2x00dev, reg,
					       &addr_entry, sizeof(addr_entry));
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		/*
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		 * Enable pairwise lookup table for given BSS idx.
		 * Without this, received frames will not be decrypted
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		 * by the hardware.
		 */
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		rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, &reg);
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		reg |= (1 << crypto->bssidx);
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		rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg);
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		/*
		 * The driver does not support the IV/EIV generation
		 * in hardware. However it doesn't support the IV/EIV
		 * inside the ieee80211 frame either, but requires it
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		 * to be provided separately for the descriptor.
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		 * rt2x00lib will cut the IV/EIV data out of all frames
		 * given to us by mac80211, but we must tell mac80211
		 * to generate the IV/EIV data.
		 */
		key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
	}

	/*
	 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
	 * a particular key is valid. Because using the FIELD32()
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	 * defines directly will cause a lot of overhead, we use
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	 * a calculation to determine the correct bit directly.
	 */
	if (key->hw_key_idx < 32) {
		mask = 1 << key->hw_key_idx;

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		rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
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		if (crypto->cmd == SET_KEY)
			reg |= mask;
		else if (crypto->cmd == DISABLE_KEY)
			reg &= ~mask;
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		rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg);
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	} else {
		mask = 1 << (key->hw_key_idx - 32);

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		rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
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		if (crypto->cmd == SET_KEY)
			reg |= mask;
		else if (crypto->cmd == DISABLE_KEY)
			reg &= ~mask;
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		rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg);
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	}

	return 0;
}

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static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
				  const unsigned int filter_flags)
{
	u32 reg;

	/*
	 * Start configuration steps.
	 * Note that the version error will always be dropped
	 * and broadcast frames will always be accepted since
	 * there is no filter for it at this time.
	 */
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	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
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	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
			   !(filter_flags & FIF_FCSFAIL));
	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
			   !(filter_flags & FIF_PLCPFAIL));
	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
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			   !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
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	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
			   !(filter_flags & FIF_PROMISC_IN_BSS));
	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
539 540
			   !(filter_flags & FIF_PROMISC_IN_BSS) &&
			   !rt2x00dev->intf_ap_count);
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	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
			   !(filter_flags & FIF_ALLMULTI));
	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
	rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
			   !(filter_flags & FIF_CONTROL));
547
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
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}

550 551 552 553
static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
				struct rt2x00_intf *intf,
				struct rt2x00intf_conf *conf,
				const unsigned int flags)
554
{
555
	u32 reg;
556

557 558 559 560
	if (flags & CONFIG_UPDATE_TYPE) {
		/*
		 * Enable synchronisation.
		 */
561
		rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
562
		rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
563
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
564
	}
565

566 567 568 569
	if (flags & CONFIG_UPDATE_MAC) {
		reg = le32_to_cpu(conf->mac[1]);
		rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
		conf->mac[1] = cpu_to_le32(reg);
570

571 572
		rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2,
					       conf->mac, sizeof(conf->mac));
573
	}
574

575 576 577 578
	if (flags & CONFIG_UPDATE_BSSID) {
		reg = le32_to_cpu(conf->bssid[1]);
		rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
		conf->bssid[1] = cpu_to_le32(reg);
579

580 581 582
		rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4,
					       conf->bssid,
					       sizeof(conf->bssid));
583
	}
584 585
}

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586
static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
587 588
			       struct rt2x00lib_erp *erp,
			       u32 changed)
589 590 591
{
	u32 reg;

592
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
593
	rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
594
	rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
595
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
596

597
	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
598
		rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
599 600 601
		rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
		rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
				   !!erp->short_preamble);
602
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
603
	}
604

605
	if (changed & BSS_CHANGED_BASIC_RATES)
606 607
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5,
					  erp->basic_rates);
608

609
	if (changed & BSS_CHANGED_BEACON_INT) {
610
		rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
611 612
		rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
				   erp->beacon_int * 16);
613
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
614
	}
615

616
	if (changed & BSS_CHANGED_ERP_SLOT) {
617
		rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
618
		rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
619
		rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
620

621
		rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, &reg);
622 623 624
		rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
		rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
		rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
625
		rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg);
626
	}
627 628 629
}

static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
630
				      struct antenna_setup *ant)
631 632 633 634 635 636 637 638 639
{
	u8 r3;
	u8 r4;
	u8 r77;

	rt61pci_bbp_read(rt2x00dev, 3, &r3);
	rt61pci_bbp_read(rt2x00dev, 4, &r4);
	rt61pci_bbp_read(rt2x00dev, 77, &r77);

640
	rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
641 642 643 644

	/*
	 * Configure the RX antenna.
	 */
645
	switch (ant->rx) {
646
	case ANTENNA_HW_DIVERSITY:
647
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
648
		rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
649
				  (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
650 651
		break;
	case ANTENNA_A:
652
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
653
		rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
654
		if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
655 656 657
			rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
		else
			rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
658 659
		break;
	case ANTENNA_B:
660
	default:
661
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
662
		rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
663
		if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
664 665 666
			rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
		else
			rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
667 668 669 670 671 672 673 674 675
		break;
	}

	rt61pci_bbp_write(rt2x00dev, 77, r77);
	rt61pci_bbp_write(rt2x00dev, 3, r3);
	rt61pci_bbp_write(rt2x00dev, 4, r4);
}

static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
676
				      struct antenna_setup *ant)
677 678 679 680 681 682 683 684 685
{
	u8 r3;
	u8 r4;
	u8 r77;

	rt61pci_bbp_read(rt2x00dev, 3, &r3);
	rt61pci_bbp_read(rt2x00dev, 4, &r4);
	rt61pci_bbp_read(rt2x00dev, 77, &r77);

686
	rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
687
	rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
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688
			  !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags));
689

690 691 692
	/*
	 * Configure the RX antenna.
	 */
693
	switch (ant->rx) {
694
	case ANTENNA_HW_DIVERSITY:
695
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
696 697
		break;
	case ANTENNA_A:
698 699
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
		rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
700 701
		break;
	case ANTENNA_B:
702
	default:
703 704
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
		rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
705 706 707 708 709 710 711 712 713 714 715 716 717
		break;
	}

	rt61pci_bbp_write(rt2x00dev, 77, r77);
	rt61pci_bbp_write(rt2x00dev, 3, r3);
	rt61pci_bbp_write(rt2x00dev, 4, r4);
}

static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
					   const int p1, const int p2)
{
	u32 reg;

718
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
719

720 721
	rt2x00_set_field32(&reg, MAC_CSR13_DIR4, 0);
	rt2x00_set_field32(&reg, MAC_CSR13_VAL4, p1);
722

723 724
	rt2x00_set_field32(&reg, MAC_CSR13_DIR3, 0);
	rt2x00_set_field32(&reg, MAC_CSR13_VAL3, !p2);
725

726
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
727 728 729
}

static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
730
					struct antenna_setup *ant)
731 732 733 734 735 736 737 738
{
	u8 r3;
	u8 r4;
	u8 r77;

	rt61pci_bbp_read(rt2x00dev, 3, &r3);
	rt61pci_bbp_read(rt2x00dev, 4, &r4);
	rt61pci_bbp_read(rt2x00dev, 77, &r77);
739 740 741 742 743 744

	/*
	 * Configure the RX antenna.
	 */
	switch (ant->rx) {
	case ANTENNA_A:
745 746 747
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
		rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
		rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
748 749 750
		break;
	case ANTENNA_HW_DIVERSITY:
		/*
751 752 753
		 * FIXME: Antenna selection for the rf 2529 is very confusing
		 * in the legacy driver. Just default to antenna B until the
		 * legacy code can be properly translated into rt2x00 code.
754 755
		 */
	case ANTENNA_B:
756
	default:
757 758 759
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
		rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
		rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
760 761 762 763
		break;
	}

	rt61pci_bbp_write(rt2x00dev, 77, r77);
764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798
	rt61pci_bbp_write(rt2x00dev, 3, r3);
	rt61pci_bbp_write(rt2x00dev, 4, r4);
}

struct antenna_sel {
	u8 word;
	/*
	 * value[0] -> non-LNA
	 * value[1] -> LNA
	 */
	u8 value[2];
};

static const struct antenna_sel antenna_sel_a[] = {
	{ 96,  { 0x58, 0x78 } },
	{ 104, { 0x38, 0x48 } },
	{ 75,  { 0xfe, 0x80 } },
	{ 86,  { 0xfe, 0x80 } },
	{ 88,  { 0xfe, 0x80 } },
	{ 35,  { 0x60, 0x60 } },
	{ 97,  { 0x58, 0x58 } },
	{ 98,  { 0x58, 0x58 } },
};

static const struct antenna_sel antenna_sel_bg[] = {
	{ 96,  { 0x48, 0x68 } },
	{ 104, { 0x2c, 0x3c } },
	{ 75,  { 0xfe, 0x80 } },
	{ 86,  { 0xfe, 0x80 } },
	{ 88,  { 0xfe, 0x80 } },
	{ 35,  { 0x50, 0x50 } },
	{ 97,  { 0x48, 0x48 } },
	{ 98,  { 0x48, 0x48 } },
};

799 800
static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
			       struct antenna_setup *ant)
801 802 803 804 805 806
{
	const struct antenna_sel *sel;
	unsigned int lna;
	unsigned int i;
	u32 reg;

807 808 809 810 811 812 813
	/*
	 * We should never come here because rt2x00lib is supposed
	 * to catch this and send us the correct antenna explicitely.
	 */
	BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
	       ant->tx == ANTENNA_SW_DIVERSITY);

814
	if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
815
		sel = antenna_sel_a;
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816
		lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
817 818
	} else {
		sel = antenna_sel_bg;
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819
		lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
820 821
	}

822 823 824
	for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
		rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);

825
	rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, &reg);
826

827
	rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
828
			   rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
829
	rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
830
			   rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
831

832
	rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg);
833

834
	if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
835
		rt61pci_config_antenna_5x(rt2x00dev, ant);
836
	else if (rt2x00_rf(rt2x00dev, RF2527))
837
		rt61pci_config_antenna_2x(rt2x00dev, ant);
838
	else if (rt2x00_rf(rt2x00dev, RF2529)) {
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839
		if (test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags))
840
			rt61pci_config_antenna_2x(rt2x00dev, ant);
841
		else
842
			rt61pci_config_antenna_2529(rt2x00dev, ant);
843 844 845
	}
}

846 847 848 849 850 851
static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
				    struct rt2x00lib_conf *libconf)
{
	u16 eeprom;
	short lna_gain = 0;

852
	if (libconf->conf->chandef.chan->band == IEEE80211_BAND_2GHZ) {
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853
		if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
854 855 856 857 858
			lna_gain += 14;

		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
		lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
	} else {
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859
		if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878
			lna_gain += 14;

		rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
		lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
	}

	rt2x00dev->lna_gain = lna_gain;
}

static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
				   struct rf_channel *rf, const int txpower)
{
	u8 r3;
	u8 r94;
	u8 smart;

	rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);

879
	smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927

	rt61pci_bbp_read(rt2x00dev, 3, &r3);
	rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
	rt61pci_bbp_write(rt2x00dev, 3, r3);

	r94 = 6;
	if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
		r94 += txpower - MAX_TXPOWER;
	else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
		r94 += txpower;
	rt61pci_bbp_write(rt2x00dev, 94, r94);

	rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
	rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
	rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
	rt61pci_rf_write(rt2x00dev, 4, rf->rf4);

	udelay(200);

	rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
	rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
	rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
	rt61pci_rf_write(rt2x00dev, 4, rf->rf4);

	udelay(200);

	rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
	rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
	rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
	rt61pci_rf_write(rt2x00dev, 4, rf->rf4);

	msleep(1);
}

static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
				   const int txpower)
{
	struct rf_channel rf;

	rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
	rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
	rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
	rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);

	rt61pci_config_channel(rt2x00dev, &rf, txpower);
}

static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
928
				    struct rt2x00lib_conf *libconf)
929 930 931
{
	u32 reg;

932
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
933 934 935
	rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
	rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
	rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
936 937 938 939
	rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
			   libconf->conf->long_frame_max_tx_count);
	rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
			   libconf->conf->short_frame_max_tx_count);
940
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
941
}
942

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Ivo van Doorn 已提交
943 944 945 946 947 948 949 950 951
static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
				struct rt2x00lib_conf *libconf)
{
	enum dev_state state =
	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
		STATE_SLEEP : STATE_AWAKE;
	u32 reg;

	if (state == STATE_SLEEP) {
952
		rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
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953
		rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
954
				   rt2x00dev->beacon_int - 10);
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955 956 957 958 959 960
		rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
				   libconf->conf->listen_interval - 1);
		rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);

		/* We must first disable autowake before it can be enabled */
		rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
961
		rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
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962 963

		rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
964
		rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
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965

966 967 968 969
		rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
					  0x00000005);
		rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
		rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
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970 971 972

		rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
	} else {
973
		rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
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974 975 976 977
		rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
		rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
		rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
		rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
978
		rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
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979

980 981 982 983
		rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
					  0x00000007);
		rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
		rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
I
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984 985 986 987 988

		rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
	}
}

989
static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
990 991
			   struct rt2x00lib_conf *libconf,
			   const unsigned int flags)
992
{
993 994 995
	/* Always recalculate LNA gain before changing configuration */
	rt61pci_config_lna_gain(rt2x00dev, libconf);

996
	if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
997 998
		rt61pci_config_channel(rt2x00dev, &libconf->rf,
				       libconf->conf->power_level);
999 1000
	if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
	    !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1001
		rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1002 1003
	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
		rt61pci_config_retry_limit(rt2x00dev, libconf);
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1004 1005
	if (flags & IEEE80211_CONF_CHANGE_PS)
		rt61pci_config_ps(rt2x00dev, libconf);
1006 1007 1008 1009 1010
}

/*
 * Link tuning
 */
1011 1012
static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
			       struct link_qual *qual)
1013 1014 1015 1016 1017 1018
{
	u32 reg;

	/*
	 * Update FCS error count from register.
	 */
1019
	rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
1020
	qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1021 1022 1023 1024

	/*
	 * Update False CCA count from register.
	 */
1025
	rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
1026
	qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1027 1028
}

1029 1030
static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
				   struct link_qual *qual, u8 vgc_level)
1031
{
1032
	if (qual->vgc_level != vgc_level) {
1033
		rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1034 1035
		qual->vgc_level = vgc_level;
		qual->vgc_level_reg = vgc_level;
1036 1037 1038
	}
}

1039 1040
static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
				struct link_qual *qual)
1041
{
1042
	rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1043 1044
}

1045 1046
static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
			       struct link_qual *qual, const u32 count)
1047 1048 1049 1050 1051 1052 1053
{
	u8 up_bound;
	u8 low_bound;

	/*
	 * Determine r17 bounds.
	 */
1054
	if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1055 1056
		low_bound = 0x28;
		up_bound = 0x48;
I
Ivo van Doorn 已提交
1057
		if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
1058 1059 1060 1061 1062 1063
			low_bound += 0x10;
			up_bound += 0x10;
		}
	} else {
		low_bound = 0x20;
		up_bound = 0x40;
I
Ivo van Doorn 已提交
1064
		if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) {
1065 1066 1067 1068 1069
			low_bound += 0x10;
			up_bound += 0x10;
		}
	}

1070 1071 1072 1073 1074 1075 1076
	/*
	 * If we are not associated, we should go straight to the
	 * dynamic CCA tuning.
	 */
	if (!rt2x00dev->intf_associated)
		goto dynamic_cca_tune;

1077 1078 1079
	/*
	 * Special big-R17 for very short distance
	 */
1080 1081
	if (qual->rssi >= -35) {
		rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1082 1083 1084 1085 1086 1087
		return;
	}

	/*
	 * Special big-R17 for short distance
	 */
1088 1089
	if (qual->rssi >= -58) {
		rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1090 1091 1092 1093 1094 1095
		return;
	}

	/*
	 * Special big-R17 for middle-short distance
	 */
1096 1097
	if (qual->rssi >= -66) {
		rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1098 1099 1100 1101 1102 1103
		return;
	}

	/*
	 * Special mid-R17 for middle distance
	 */
1104 1105
	if (qual->rssi >= -74) {
		rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1106 1107 1108 1109 1110 1111 1112
		return;
	}

	/*
	 * Special case: Change up_bound based on the rssi.
	 * Lower up_bound when rssi is weaker then -74 dBm.
	 */
1113
	up_bound -= 2 * (-74 - qual->rssi);
1114 1115 1116
	if (low_bound > up_bound)
		up_bound = low_bound;

1117 1118
	if (qual->vgc_level > up_bound) {
		rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1119 1120 1121
		return;
	}

1122 1123
dynamic_cca_tune:

1124 1125 1126 1127
	/*
	 * r17 does not yet exceed upper limit, continue and base
	 * the r17 tuning on the false CCA count.
	 */
1128 1129 1130 1131
	if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
		rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
	else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
		rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1132 1133
}

1134 1135 1136 1137 1138 1139 1140 1141 1142 1143
/*
 * Queue handlers.
 */
static void rt61pci_start_queue(struct data_queue *queue)
{
	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
	u32 reg;

	switch (queue->qid) {
	case QID_RX:
1144
		rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1145
		rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1146
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1147 1148
		break;
	case QID_BEACON:
1149
		rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1150 1151 1152
		rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
		rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
		rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1153
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165
		break;
	default:
		break;
	}
}

static void rt61pci_kick_queue(struct data_queue *queue)
{
	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
	u32 reg;

	switch (queue->qid) {
I
Ivo van Doorn 已提交
1166
	case QID_AC_VO:
1167
		rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1168
		rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1169
		rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1170
		break;
I
Ivo van Doorn 已提交
1171
	case QID_AC_VI:
1172
		rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1173
		rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1174
		rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1175
		break;
I
Ivo van Doorn 已提交
1176
	case QID_AC_BE:
1177
		rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1178
		rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1179
		rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1180
		break;
I
Ivo van Doorn 已提交
1181
	case QID_AC_BK:
1182
		rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1183
		rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1184
		rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
		break;
	default:
		break;
	}
}

static void rt61pci_stop_queue(struct data_queue *queue)
{
	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
	u32 reg;

	switch (queue->qid) {
I
Ivo van Doorn 已提交
1197
	case QID_AC_VO:
1198
		rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1199
		rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1200
		rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1201
		break;
I
Ivo van Doorn 已提交
1202
	case QID_AC_VI:
1203
		rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1204
		rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1205
		rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1206
		break;
I
Ivo van Doorn 已提交
1207
	case QID_AC_BE:
1208
		rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1209
		rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1210
		rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1211
		break;
I
Ivo van Doorn 已提交
1212
	case QID_AC_BK:
1213
		rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1214
		rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1215
		rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1216 1217
		break;
	case QID_RX:
1218
		rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1219
		rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1220
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1221 1222
		break;
	case QID_BEACON:
1223
		rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1224 1225 1226
		rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
		rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
		rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1227
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1228 1229 1230 1231

		/*
		 * Wait for possibly running tbtt tasklets.
		 */
1232
		tasklet_kill(&rt2x00dev->tbtt_tasklet);
1233 1234 1235 1236 1237 1238
		break;
	default:
		break;
	}
}

1239
/*
1240
 * Firmware functions
1241 1242 1243
 */
static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
{
1244
	u16 chip;
1245 1246
	char *fw_name;

1247 1248 1249
	pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
	switch (chip) {
	case RT2561_PCI_ID:
1250 1251
		fw_name = FIRMWARE_RT2561;
		break;
1252
	case RT2561s_PCI_ID:
1253 1254
		fw_name = FIRMWARE_RT2561s;
		break;
1255
	case RT2661_PCI_ID:
1256 1257 1258 1259 1260 1261 1262 1263 1264 1265
		fw_name = FIRMWARE_RT2661;
		break;
	default:
		fw_name = NULL;
		break;
	}

	return fw_name;
}

1266 1267
static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
				  const u8 *data, const size_t len)
1268
{
1269
	u16 fw_crc;
1270 1271 1272
	u16 crc;

	/*
1273 1274 1275 1276 1277 1278
	 * Only support 8kb firmware files.
	 */
	if (len != 8192)
		return FW_BAD_LENGTH;

	/*
1279 1280
	 * The last 2 bytes in the firmware array are the crc checksum itself.
	 * This means that we should never pass those 2 bytes to the crc
1281 1282
	 * algorithm.
	 */
1283 1284 1285 1286 1287
	fw_crc = (data[len - 2] << 8 | data[len - 1]);

	/*
	 * Use the crc itu-t algorithm.
	 */
1288 1289 1290 1291
	crc = crc_itu_t(0, data, len - 2);
	crc = crc_itu_t_byte(crc, 0);
	crc = crc_itu_t_byte(crc, 0);

1292
	return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1293 1294
}

1295 1296
static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
				 const u8 *data, const size_t len)
1297 1298 1299 1300 1301 1302 1303 1304
{
	int i;
	u32 reg;

	/*
	 * Wait for stable hardware.
	 */
	for (i = 0; i < 100; i++) {
1305
		rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
1306 1307 1308 1309 1310 1311
		if (reg)
			break;
		msleep(1);
	}

	if (!reg) {
1312
		rt2x00_err(rt2x00dev, "Unstable hardware\n");
1313 1314 1315 1316 1317 1318 1319 1320
		return -EBUSY;
	}

	/*
	 * Prepare MCU and mailbox for firmware loading.
	 */
	reg = 0;
	rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1321 1322 1323 1324
	rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
	rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
	rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
	rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1325 1326 1327 1328 1329 1330 1331

	/*
	 * Write firmware to device.
	 */
	reg = 0;
	rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
	rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1332
	rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1333

1334 1335
	rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
				       data, len);
1336 1337

	rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1338
	rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1339 1340

	rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1341
	rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1342 1343

	for (i = 0; i < 100; i++) {
1344
		rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1345 1346 1347 1348 1349 1350
		if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
			break;
		msleep(1);
	}

	if (i == 100) {
1351
		rt2x00_err(rt2x00dev, "MCU Control register not ready\n");
1352 1353 1354
		return -EBUSY;
	}

1355 1356 1357 1358 1359
	/*
	 * Hardware needs another millisecond before it is ready.
	 */
	msleep(1);

1360 1361 1362 1363 1364 1365
	/*
	 * Reset MAC and BBP registers.
	 */
	reg = 0;
	rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
	rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1366
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1367

1368
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1369 1370
	rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
	rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1371
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1372

1373
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1374
	rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1375
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1376 1377 1378 1379

	return 0;
}

1380 1381 1382
/*
 * Initialization functions.
 */
1383
static bool rt61pci_get_entry_state(struct queue_entry *entry)
1384
{
1385
	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1386 1387
	u32 word;

1388 1389
	if (entry->queue->qid == QID_RX) {
		rt2x00_desc_read(entry_priv->desc, 0, &word);
1390

1391 1392 1393 1394 1395 1396 1397
		return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
	} else {
		rt2x00_desc_read(entry_priv->desc, 0, &word);

		return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
		        rt2x00_get_field32(word, TXD_W0_VALID));
	}
1398 1399
}

1400
static void rt61pci_clear_entry(struct queue_entry *entry)
1401
{
1402
	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1403
	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1404 1405
	u32 word;

1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420
	if (entry->queue->qid == QID_RX) {
		rt2x00_desc_read(entry_priv->desc, 5, &word);
		rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
				   skbdesc->skb_dma);
		rt2x00_desc_write(entry_priv->desc, 5, word);

		rt2x00_desc_read(entry_priv->desc, 0, &word);
		rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
		rt2x00_desc_write(entry_priv->desc, 0, word);
	} else {
		rt2x00_desc_read(entry_priv->desc, 0, &word);
		rt2x00_set_field32(&word, TXD_W0_VALID, 0);
		rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
		rt2x00_desc_write(entry_priv->desc, 0, word);
	}
1421 1422
}

I
Ivo van Doorn 已提交
1423
static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1424
{
1425
	struct queue_entry_priv_mmio *entry_priv;
1426 1427 1428 1429 1430
	u32 reg;

	/*
	 * Initialize registers.
	 */
1431
	rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1432
	rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
I
Ivo van Doorn 已提交
1433
			   rt2x00dev->tx[0].limit);
1434
	rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
I
Ivo van Doorn 已提交
1435
			   rt2x00dev->tx[1].limit);
1436
	rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
I
Ivo van Doorn 已提交
1437
			   rt2x00dev->tx[2].limit);
1438
	rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
I
Ivo van Doorn 已提交
1439
			   rt2x00dev->tx[3].limit);
1440
	rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg);
1441

1442
	rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1443
	rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
I
Ivo van Doorn 已提交
1444
			   rt2x00dev->tx[0].desc_size / 4);
1445
	rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg);
1446

1447
	entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1448
	rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1449
	rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1450
			   entry_priv->desc_dma);
1451
	rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1452

1453
	entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1454
	rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1455
	rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1456
			   entry_priv->desc_dma);
1457
	rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1458

1459
	entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1460
	rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1461
	rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1462
			   entry_priv->desc_dma);
1463
	rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1464

1465
	entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1466
	rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1467
	rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1468
			   entry_priv->desc_dma);
1469
	rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1470

1471
	rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, &reg);
I
Ivo van Doorn 已提交
1472
	rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1473 1474 1475
	rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
			   rt2x00dev->rx->desc_size / 4);
	rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1476
	rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg);
1477

1478
	entry_priv = rt2x00dev->rx->entries[0].priv_data;
1479
	rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1480
	rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1481
			   entry_priv->desc_dma);
1482
	rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg);
1483

1484
	rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1485 1486 1487 1488
	rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
	rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
	rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
	rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1489
	rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1490

1491
	rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1492 1493 1494 1495
	rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
	rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
	rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
	rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1496
	rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1497

1498
	rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1499
	rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1500
	rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1501 1502 1503 1504 1505 1506 1507 1508

	return 0;
}

static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;

1509
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
1510 1511 1512
	rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
	rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
	rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1513
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
1514

1515
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, &reg);
1516 1517 1518 1519 1520 1521 1522 1523
	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
	rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1524
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg);
1525 1526 1527 1528

	/*
	 * CCK TXD BBP registers
	 */
1529
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, &reg);
1530 1531 1532 1533 1534 1535 1536 1537
	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
	rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1538
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg);
1539 1540 1541 1542

	/*
	 * OFDM TXD BBP registers
	 */
1543
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, &reg);
1544 1545 1546 1547 1548 1549
	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
	rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1550
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg);
1551

1552
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, &reg);
1553 1554 1555 1556
	rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
	rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
	rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
	rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1557
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg);
1558

1559
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, &reg);
1560 1561 1562 1563
	rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
	rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
	rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
	rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1564
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg);
1565

1566
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1567 1568 1569 1570 1571 1572
	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
	rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
	rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
	rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
	rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1573
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1574

1575
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1576

1577
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1578

1579
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
1580
	rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1581
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
1582

1583
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1584 1585 1586 1587

	if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
		return -EBUSY;

1588
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1589 1590 1591 1592 1593

	/*
	 * Invalidate all Shared Keys (SEC_CSR0),
	 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
	 */
1594 1595 1596
	rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
	rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
	rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1597

1598 1599 1600 1601
	rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
	rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
	rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
	rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1602

1603
	rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1604

1605
	rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1606

1607
	rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1608

1609 1610 1611 1612 1613 1614
	/*
	 * Clear all beacons
	 * For the Beacon base registers we only need to clear
	 * the first byte since that byte contains the VALID and OWNER
	 * bits which (when set to 0) will invalidate the entire beacon.
	 */
1615 1616 1617 1618
	rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
	rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
	rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
	rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1619

1620 1621 1622 1623 1624
	/*
	 * We must clear the error counters.
	 * These registers are cleared on read,
	 * so we may pass a useless variable to store the value.
	 */
1625 1626 1627
	rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
	rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
	rt2x00mmio_register_read(rt2x00dev, STA_CSR2, &reg);
1628 1629 1630 1631

	/*
	 * Reset MAC and BBP registers.
	 */
1632
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1633 1634
	rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
	rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1635
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1636

1637
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1638 1639
	rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
	rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1640
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1641

1642
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
1643
	rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1644
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
1645 1646 1647 1648

	return 0;
}

1649
static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1650 1651 1652 1653 1654 1655 1656
{
	unsigned int i;
	u8 value;

	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt61pci_bbp_read(rt2x00dev, 0, &value);
		if ((value != 0xff) && (value != 0x00))
1657
			return 0;
1658 1659 1660
		udelay(REGISTER_BUSY_DELAY);
	}

1661
	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
1662
	return -EACCES;
1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673
}

static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
{
	unsigned int i;
	u16 eeprom;
	u8 reg_id;
	u8 value;

	if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
		return -EACCES;
1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718

	rt61pci_bbp_write(rt2x00dev, 3, 0x00);
	rt61pci_bbp_write(rt2x00dev, 15, 0x30);
	rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
	rt61pci_bbp_write(rt2x00dev, 22, 0x38);
	rt61pci_bbp_write(rt2x00dev, 23, 0x06);
	rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
	rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
	rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
	rt61pci_bbp_write(rt2x00dev, 34, 0x12);
	rt61pci_bbp_write(rt2x00dev, 37, 0x07);
	rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
	rt61pci_bbp_write(rt2x00dev, 41, 0x60);
	rt61pci_bbp_write(rt2x00dev, 53, 0x10);
	rt61pci_bbp_write(rt2x00dev, 54, 0x18);
	rt61pci_bbp_write(rt2x00dev, 60, 0x10);
	rt61pci_bbp_write(rt2x00dev, 61, 0x04);
	rt61pci_bbp_write(rt2x00dev, 62, 0x04);
	rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
	rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
	rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
	rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
	rt61pci_bbp_write(rt2x00dev, 99, 0x00);
	rt61pci_bbp_write(rt2x00dev, 102, 0x16);
	rt61pci_bbp_write(rt2x00dev, 107, 0x04);

	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);

		if (eeprom != 0xffff && eeprom != 0x0000) {
			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
			rt61pci_bbp_write(rt2x00dev, reg_id, value);
		}
	}

	return 0;
}

/*
 * Device state switch handlers.
 */
static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
			       enum dev_state state)
{
1719
	int mask = (state == STATE_RADIO_IRQ_OFF);
1720
	u32 reg;
1721
	unsigned long flags;
1722 1723 1724 1725 1726 1727

	/*
	 * When interrupts are being enabled, the interrupt registers
	 * should clear the register to assure a clean state.
	 */
	if (state == STATE_RADIO_IRQ_ON) {
1728 1729
		rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
		rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1730

1731 1732
		rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
		rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1733 1734 1735 1736 1737 1738
	}

	/*
	 * Only toggle the interrupts bits we are going to use.
	 * Non-checked interrupt bits are disabled by default.
	 */
1739 1740
	spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);

1741
	rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1742 1743
	rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
	rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1744
	rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1745 1746
	rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
	rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1747
	rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
1748

1749
	rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1750 1751 1752 1753 1754 1755 1756 1757
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1758
	rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1759
	rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1760 1761 1762 1763 1764 1765 1766

	spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);

	if (state == STATE_RADIO_IRQ_OFF) {
		/*
		 * Ensure that all tasklets are finished.
		 */
1767 1768 1769 1770
		tasklet_kill(&rt2x00dev->txstatus_tasklet);
		tasklet_kill(&rt2x00dev->rxdone_tasklet);
		tasklet_kill(&rt2x00dev->autowake_tasklet);
		tasklet_kill(&rt2x00dev->tbtt_tasklet);
1771
	}
1772 1773 1774 1775 1776 1777 1778 1779 1780
}

static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;

	/*
	 * Initialize all registers.
	 */
1781 1782 1783
	if (unlikely(rt61pci_init_queues(rt2x00dev) ||
		     rt61pci_init_registers(rt2x00dev) ||
		     rt61pci_init_bbp(rt2x00dev)))
1784 1785 1786 1787 1788
		return -EIO;

	/*
	 * Enable RX.
	 */
1789
	rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1790
	rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1791
	rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1792 1793 1794 1795 1796 1797 1798

	return 0;
}

static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
{
	/*
1799
	 * Disable power
1800
	 */
1801
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1802 1803 1804 1805
}

static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
{
1806
	u32 reg, reg2;
1807 1808 1809 1810 1811
	unsigned int i;
	char put_to_sleep;

	put_to_sleep = (state != STATE_AWAKE);

1812
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg);
1813 1814
	rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
	rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1815
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1816 1817 1818 1819 1820 1821 1822

	/*
	 * Device is not guaranteed to be in the requested state yet.
	 * We must wait until the register indicates that the
	 * device has entered the correct state.
	 */
	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1823
		rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg2);
1824
		state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1825
		if (state == !put_to_sleep)
1826
			return 0;
1827
		rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845
		msleep(10);
	}

	return -EBUSY;
}

static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
				    enum dev_state state)
{
	int retval = 0;

	switch (state) {
	case STATE_RADIO_ON:
		retval = rt61pci_enable_radio(rt2x00dev);
		break;
	case STATE_RADIO_OFF:
		rt61pci_disable_radio(rt2x00dev);
		break;
1846 1847 1848
	case STATE_RADIO_IRQ_ON:
	case STATE_RADIO_IRQ_OFF:
		rt61pci_toggle_irq(rt2x00dev, state);
1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860
		break;
	case STATE_DEEP_SLEEP:
	case STATE_SLEEP:
	case STATE_STANDBY:
	case STATE_AWAKE:
		retval = rt61pci_set_state(rt2x00dev, state);
		break;
	default:
		retval = -ENOTSUPP;
		break;
	}

1861
	if (unlikely(retval))
1862 1863
		rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
			   state, retval);
1864

1865 1866 1867 1868 1869 1870
	return retval;
}

/*
 * TX descriptor initialization
 */
1871
static void rt61pci_write_tx_desc(struct queue_entry *entry,
1872
				  struct txentry_desc *txdesc)
1873
{
1874
	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1875
	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1876
	__le32 *txd = entry_priv->desc;
1877 1878 1879 1880 1881 1882
	u32 word;

	/*
	 * Start writing the descriptor words.
	 */
	rt2x00_desc_read(txd, 1, &word);
H
Helmut Schaa 已提交
1883 1884 1885 1886
	rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
	rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
	rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
	rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1887
	rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1888 1889
	rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1890
	rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1891 1892 1893
	rt2x00_desc_write(txd, 1, word);

	rt2x00_desc_read(txd, 2, &word);
1894 1895 1896 1897 1898 1899
	rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
	rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
	rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
			   txdesc->u.plcp.length_low);
	rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
			   txdesc->u.plcp.length_high);
1900 1901
	rt2x00_desc_write(txd, 2, word);

1902
	if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
I
Ivo van Doorn 已提交
1903 1904
		_rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
		_rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1905 1906
	}

1907
	rt2x00_desc_read(txd, 5, &word);
1908
	rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1909 1910
	rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
			   skbdesc->entry->entry_idx);
1911
	rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1912
			   TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1913 1914 1915
	rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
	rt2x00_desc_write(txd, 5, word);

H
Helmut Schaa 已提交
1916
	if (entry->queue->qid != QID_BEACON) {
1917 1918 1919 1920
		rt2x00_desc_read(txd, 6, &word);
		rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
				   skbdesc->skb_dma);
		rt2x00_desc_write(txd, 6, word);
1921

1922
		rt2x00_desc_read(txd, 11, &word);
1923 1924
		rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
				   txdesc->length);
1925 1926
		rt2x00_desc_write(txd, 11, word);
	}
1927

1928 1929 1930 1931 1932
	/*
	 * Writing TXD word 0 must the last to prevent a race condition with
	 * the device, whereby the device may take hold of the TXD before we
	 * finished updating it.
	 */
1933 1934 1935 1936
	rt2x00_desc_read(txd, 0, &word);
	rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
	rt2x00_set_field32(&word, TXD_W0_VALID, 1);
	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
I
Ivo van Doorn 已提交
1937
			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1938
	rt2x00_set_field32(&word, TXD_W0_ACK,
I
Ivo van Doorn 已提交
1939
			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1940
	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
I
Ivo van Doorn 已提交
1941
			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1942
	rt2x00_set_field32(&word, TXD_W0_OFDM,
1943
			   (txdesc->rate_mode == RATE_MODE_OFDM));
1944
	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1945
	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1946
			   test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1947 1948 1949 1950 1951
	rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
			   test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
	rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
			   test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
	rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1952
	rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1953
	rt2x00_set_field32(&word, TXD_W0_BURST,
I
Ivo van Doorn 已提交
1954
			   test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1955
	rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1956
	rt2x00_desc_write(txd, 0, word);
1957 1958 1959 1960 1961

	/*
	 * Register descriptor details in skb frame descriptor.
	 */
	skbdesc->desc = txd;
H
Helmut Schaa 已提交
1962 1963
	skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
			    TXD_DESC_SIZE;
1964 1965 1966 1967 1968
}

/*
 * TX data initialization
 */
1969 1970
static void rt61pci_write_beacon(struct queue_entry *entry,
				 struct txentry_desc *txdesc)
1971 1972
{
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1973
	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
1974
	unsigned int beacon_base;
1975
	unsigned int padding_len;
1976
	u32 orig_reg, reg;
1977 1978 1979 1980 1981

	/*
	 * Disable beaconing while we are reloading the beacon data,
	 * otherwise we might be sending out invalid data.
	 */
1982
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1983
	orig_reg = reg;
1984
	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1985
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1986

1987 1988 1989
	/*
	 * Write the TX descriptor for the beacon.
	 */
1990
	rt61pci_write_tx_desc(entry, txdesc);
1991 1992 1993 1994 1995 1996

	/*
	 * Dump beacon to userspace through debugfs.
	 */
	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);

1997
	/*
1998
	 * Write entire beacon with descriptor and padding to register.
1999
	 */
2000
	padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
2001
	if (padding_len && skb_pad(entry->skb, padding_len)) {
2002
		rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
2003 2004
		/* skb freed by skb_pad() on failure */
		entry->skb = NULL;
2005
		rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2006 2007 2008
		return;
	}

2009
	beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2010 2011 2012 2013 2014
	rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base,
				       entry_priv->desc, TXINFO_SIZE);
	rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
				       entry->skb->data,
				       entry->skb->len + padding_len);
2015

2016 2017 2018 2019 2020 2021
	/*
	 * Enable beaconing again.
	 *
	 * For Wi-Fi faily generated beacons between participating
	 * stations. Set TBTT phase adaptive adjustment step to 8us.
	 */
2022
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2023 2024

	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2025
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2026

2027 2028 2029 2030 2031 2032 2033
	/*
	 * Clean up beacon skb.
	 */
	dev_kfree_skb_any(entry->skb);
	entry->skb = NULL;
}

2034 2035 2036 2037 2038 2039 2040 2041 2042
static void rt61pci_clear_beacon(struct queue_entry *entry)
{
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
	u32 reg;

	/*
	 * Disable beaconing while we are reloading the beacon data,
	 * otherwise we might be sending out invalid data.
	 */
2043
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
2044
	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2045
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2046 2047 2048 2049

	/*
	 * Clear beacon.
	 */
2050 2051
	rt2x00mmio_register_write(rt2x00dev,
				  HW_BEACON_OFFSET(entry->entry_idx), 0);
2052 2053 2054 2055 2056

	/*
	 * Enable beaconing again.
	 */
	rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2057
	rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
2058 2059
}

2060 2061 2062 2063 2064
/*
 * RX control handlers
 */
static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
{
2065
	u8 offset = rt2x00dev->lna_gain;
2066 2067 2068 2069 2070
	u8 lna;

	lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
	switch (lna) {
	case 3:
2071
		offset += 90;
2072 2073
		break;
	case 2:
2074
		offset += 74;
2075 2076
		break;
	case 1:
2077
		offset += 64;
2078 2079 2080 2081 2082
		break;
	default:
		return 0;
	}

2083
	if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
2084 2085 2086 2087 2088 2089 2090
		if (lna == 3 || lna == 2)
			offset += 10;
	}

	return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
}

I
Ivo van Doorn 已提交
2091
static void rt61pci_fill_rxdone(struct queue_entry *entry,
J
John Daiker 已提交
2092
				struct rxdone_entry_desc *rxdesc)
2093
{
2094
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2095
	struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
2096 2097 2098
	u32 word0;
	u32 word1;

2099 2100
	rt2x00_desc_read(entry_priv->desc, 0, &word0);
	rt2x00_desc_read(entry_priv->desc, 1, &word1);
2101

2102
	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
I
Ivo van Doorn 已提交
2103
		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2104

2105 2106
	rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
	rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
2107 2108

	if (rxdesc->cipher != CIPHER_NONE) {
I
Ivo van Doorn 已提交
2109 2110
		_rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
		_rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
2111 2112
		rxdesc->dev_flags |= RXDONE_CRYPTO_IV;

2113
		_rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2114
		rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2115 2116 2117

		/*
		 * Hardware has stripped IV/EIV data from 802.11 frame during
2118
		 * decryption. It has provided the data separately but rt2x00lib
2119 2120 2121 2122 2123
		 * should decide if it should be reinserted.
		 */
		rxdesc->flags |= RX_FLAG_IV_STRIPPED;

		/*
2124 2125
		 * The hardware has already checked the Michael Mic and has
		 * stripped it from the frame. Signal this to mac80211.
2126 2127 2128 2129 2130 2131 2132 2133 2134
		 */
		rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;

		if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
			rxdesc->flags |= RX_FLAG_DECRYPTED;
		else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
			rxdesc->flags |= RX_FLAG_MMIC_ERROR;
	}

2135 2136
	/*
	 * Obtain the status about this packet.
I
Ivo van Doorn 已提交
2137 2138 2139
	 * When frame was received with an OFDM bitrate,
	 * the signal is the PLCP value. If it was received with
	 * a CCK bitrate the signal is the rate in 100kbit/s.
2140
	 */
I
Ivo van Doorn 已提交
2141
	rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2142
	rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
I
Ivo van Doorn 已提交
2143
	rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2144 2145 2146

	if (rt2x00_get_field32(word0, RXD_W0_OFDM))
		rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
I
Ivo van Doorn 已提交
2147 2148
	else
		rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2149 2150
	if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
		rxdesc->dev_flags |= RXDONE_MY_BSS;
2151 2152 2153 2154 2155 2156 2157
}

/*
 * Interrupt functions.
 */
static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
{
I
Ivo van Doorn 已提交
2158 2159 2160
	struct data_queue *queue;
	struct queue_entry *entry;
	struct queue_entry *entry_done;
2161
	struct queue_entry_priv_mmio *entry_priv;
I
Ivo van Doorn 已提交
2162
	struct txdone_entry_desc txdesc;
2163 2164 2165 2166
	u32 word;
	u32 reg;
	int type;
	int index;
2167
	int i;
2168 2169

	/*
2170 2171 2172 2173 2174 2175 2176
	 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
	 * at most X times and also stop processing once the TX_STA_FIFO_VALID
	 * flag is not set anymore.
	 *
	 * The legacy drivers use X=TX_RING_SIZE but state in a comment
	 * that the TX_STA_FIFO stack has a size of 16. We stick to our
	 * tx ring size for now.
2177
	 */
2178
	for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
2179
		rt2x00mmio_register_read(rt2x00dev, STA_CSR4, &reg);
2180 2181 2182 2183 2184
		if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
			break;

		/*
		 * Skip this entry when it contains an invalid
I
Ivo van Doorn 已提交
2185
		 * queue identication number.
2186 2187
		 */
		type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2188
		queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
I
Ivo van Doorn 已提交
2189
		if (unlikely(!queue))
2190 2191 2192 2193 2194 2195 2196
			continue;

		/*
		 * Skip this entry when it contains an invalid
		 * index number.
		 */
		index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
I
Ivo van Doorn 已提交
2197
		if (unlikely(index >= queue->limit))
2198 2199
			continue;

I
Ivo van Doorn 已提交
2200
		entry = &queue->entries[index];
2201 2202
		entry_priv = entry->priv_data;
		rt2x00_desc_read(entry_priv->desc, 0, &word);
2203 2204 2205 2206 2207

		if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
		    !rt2x00_get_field32(word, TXD_W0_VALID))
			return;

I
Ivo van Doorn 已提交
2208
		entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2209
		while (entry != entry_done) {
I
Ivo van Doorn 已提交
2210 2211 2212
			/* Catch up.
			 * Just report any entries we missed as failed.
			 */
2213 2214
			rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n",
				    entry_done->entry_idx);
I
Ivo van Doorn 已提交
2215

2216
			rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
I
Ivo van Doorn 已提交
2217
			entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2218 2219
		}

2220 2221 2222
		/*
		 * Obtain the status about this packet.
		 */
I
Ivo van Doorn 已提交
2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233
		txdesc.flags = 0;
		switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
		case 0: /* Success, maybe with retry */
			__set_bit(TXDONE_SUCCESS, &txdesc.flags);
			break;
		case 6: /* Failure, excessive retries */
			__set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
			/* Don't break, this is a failed frame! */
		default: /* Failure */
			__set_bit(TXDONE_FAILURE, &txdesc.flags);
		}
I
Ivo van Doorn 已提交
2234
		txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2235

2236 2237 2238 2239 2240 2241 2242
		/*
		 * the frame was retried at least once
		 * -> hw used fallback rates
		 */
		if (txdesc.retry)
			__set_bit(TXDONE_FALLBACK, &txdesc.flags);

2243
		rt2x00lib_txdone(entry, &txdesc);
2244 2245 2246
	}
}

2247 2248
static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
{
2249
	struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf };
2250 2251 2252 2253

	rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
}

2254 2255
static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
					    struct rt2x00_field32 irq_field)
2256
{
2257
	u32 reg;
2258 2259

	/*
2260 2261
	 * Enable a single interrupt. The interrupt mask register
	 * access needs locking.
2262
	 */
2263
	spin_lock_irq(&rt2x00dev->irqmask_lock);
2264

2265
	rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2266
	rt2x00_set_field32(&reg, irq_field, 0);
2267
	rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2268

2269
	spin_unlock_irq(&rt2x00dev->irqmask_lock);
2270
}
2271

2272 2273 2274 2275
static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
					 struct rt2x00_field32 irq_field)
{
	u32 reg;
2276

2277
	/*
2278 2279
	 * Enable a single MCU interrupt. The interrupt mask register
	 * access needs locking.
2280
	 */
2281
	spin_lock_irq(&rt2x00dev->irqmask_lock);
2282

2283
	rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2284
	rt2x00_set_field32(&reg, irq_field, 0);
2285
	rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2286

2287
	spin_unlock_irq(&rt2x00dev->irqmask_lock);
2288 2289
}

2290 2291 2292 2293
static void rt61pci_txstatus_tasklet(unsigned long data)
{
	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
	rt61pci_txdone(rt2x00dev);
2294 2295
	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
		rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2296 2297 2298 2299 2300 2301
}

static void rt61pci_tbtt_tasklet(unsigned long data)
{
	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
	rt2x00lib_beacondone(rt2x00dev);
2302 2303
	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
		rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2304 2305 2306 2307 2308
}

static void rt61pci_rxdone_tasklet(unsigned long data)
{
	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2309
	if (rt2x00mmio_rxdone(rt2x00dev))
2310 2311
		tasklet_schedule(&rt2x00dev->rxdone_tasklet);
	else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2312
		rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2313 2314 2315 2316 2317 2318
}

static void rt61pci_autowake_tasklet(unsigned long data)
{
	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
	rt61pci_wakeup(rt2x00dev);
2319 2320
	rt2x00mmio_register_write(rt2x00dev,
				  M2H_CMD_DONE_CSR, 0xffffffff);
2321 2322
	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
		rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2323
}
2324 2325 2326 2327

static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
{
	struct rt2x00_dev *rt2x00dev = dev_instance;
2328 2329
	u32 reg_mcu, mask_mcu;
	u32 reg, mask;
2330 2331 2332 2333 2334

	/*
	 * Get the interrupt sources & saved to local variable.
	 * Write register value back to clear pending interrupts.
	 */
2335 2336
	rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
	rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2337

2338 2339
	rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
	rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2340 2341 2342 2343 2344 2345 2346

	if (!reg && !reg_mcu)
		return IRQ_NONE;

	if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
		return IRQ_HANDLED;

2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373
	/*
	 * Schedule tasklets for interrupt handling.
	 */
	if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
		tasklet_schedule(&rt2x00dev->rxdone_tasklet);

	if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
		tasklet_schedule(&rt2x00dev->txstatus_tasklet);

	if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
		tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);

	if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
		tasklet_schedule(&rt2x00dev->autowake_tasklet);

	/*
	 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
	 * for interrupts and interrupt masks we can just use the value of
	 * INT_SOURCE_CSR to create the interrupt mask.
	 */
	mask = reg;
	mask_mcu = reg_mcu;

	/*
	 * Disable all interrupts for which a tasklet was scheduled right now,
	 * the tasklet will reenable the appropriate interrupts.
	 */
2374
	spin_lock(&rt2x00dev->irqmask_lock);
2375

2376
	rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2377
	reg |= mask;
2378
	rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
2379

2380
	rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2381
	reg |= mask_mcu;
2382
	rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2383

2384
	spin_unlock(&rt2x00dev->irqmask_lock);
2385 2386

	return IRQ_HANDLED;
2387 2388
}

2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399
/*
 * Device probe functions.
 */
static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
{
	struct eeprom_93cx6 eeprom;
	u32 reg;
	u16 word;
	u8 *mac;
	s8 value;

2400
	rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419

	eeprom.data = rt2x00dev;
	eeprom.register_read = rt61pci_eepromregister_read;
	eeprom.register_write = rt61pci_eepromregister_write;
	eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
	    PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
	eeprom.reg_data_in = 0;
	eeprom.reg_data_out = 0;
	eeprom.reg_data_clock = 0;
	eeprom.reg_chip_select = 0;

	eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
			       EEPROM_SIZE / sizeof(u16));

	/*
	 * Start validation of the data that has been read.
	 */
	mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
	if (!is_valid_ether_addr(mac)) {
J
Joe Perches 已提交
2420
		eth_random_addr(mac);
2421
		rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
2422 2423 2424 2425 2426
	}

	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
	if (word == 0xffff) {
		rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
I
Ivo van Doorn 已提交
2427 2428 2429 2430
		rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
				   ANTENNA_B);
		rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
				   ANTENNA_B);
2431 2432 2433 2434 2435
		rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
		rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
		rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
		rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2436
		rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
2437 2438 2439 2440 2441 2442
	}

	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
	if (word == 0xffff) {
		rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2443 2444
		rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2445 2446 2447 2448
		rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
		rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2449
		rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
2450 2451 2452 2453 2454 2455 2456
	}

	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
	if (word == 0xffff) {
		rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
				   LED_MODE_DEFAULT);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2457
		rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
2458 2459 2460 2461 2462 2463 2464
	}

	rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
	if (word == 0xffff) {
		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
		rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2465
		rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
2466 2467 2468 2469 2470 2471 2472
	}

	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
	if (word == 0xffff) {
		rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
		rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2473
		rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488
	} else {
		value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
		if (value < -10 || value > 10)
			rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
		value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
		if (value < -10 || value > 10)
			rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
	}

	rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
	if (word == 0xffff) {
		rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
		rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2489
		rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517
	} else {
		value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
		if (value < -10 || value > 10)
			rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
		value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
		if (value < -10 || value > 10)
			rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
		rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
	}

	return 0;
}

static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;
	u16 value;
	u16 eeprom;

	/*
	 * Read EEPROM word for configuration.
	 */
	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);

	/*
	 * Identify RF chipset.
	 */
	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2518
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
2519 2520
	rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
			value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2521

2522 2523 2524 2525
	if (!rt2x00_rf(rt2x00dev, RF5225) &&
	    !rt2x00_rf(rt2x00dev, RF5325) &&
	    !rt2x00_rf(rt2x00dev, RF2527) &&
	    !rt2x00_rf(rt2x00dev, RF2529)) {
2526
		rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
2527 2528 2529
		return -ENODEV;
	}

2530
	/*
L
Luis Correia 已提交
2531
	 * Determine number of antennas.
2532 2533
	 */
	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
I
Ivo van Doorn 已提交
2534
		__set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
2535

2536 2537 2538
	/*
	 * Identify default antenna configuration.
	 */
2539
	rt2x00dev->default_ant.tx =
2540
	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2541
	rt2x00dev->default_ant.rx =
2542 2543 2544 2545 2546 2547
	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);

	/*
	 * Read the Frame type.
	 */
	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
I
Ivo van Doorn 已提交
2548
		__set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
2549 2550

	/*
2551
	 * Detect if this device has a hardware controlled radio.
2552 2553
	 */
	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
I
Ivo van Doorn 已提交
2554
		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
2555 2556 2557 2558 2559 2560

	/*
	 * Read frequency offset and RF programming sequence.
	 */
	rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
	if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
I
Ivo van Doorn 已提交
2561
		__set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
2562 2563 2564 2565 2566 2567 2568 2569 2570

	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);

	/*
	 * Read external LNA informations.
	 */
	rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);

	if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
I
Ivo van Doorn 已提交
2571
		__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
2572
	if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
I
Ivo van Doorn 已提交
2573
		__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
2574

2575
	/*
2576
	 * When working with a RF2529 chip without double antenna,
2577 2578 2579
	 * the antenna settings should be gathered from the NIC
	 * eeprom word.
	 */
2580
	if (rt2x00_rf(rt2x00dev, RF2529) &&
I
Ivo van Doorn 已提交
2581
	    !test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags)) {
2582 2583 2584 2585
		rt2x00dev->default_ant.rx =
		    ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
		rt2x00dev->default_ant.tx =
		    ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2586 2587 2588 2589 2590 2591 2592

		if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
			rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
		if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
			rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
	}

2593 2594 2595 2596 2597
	/*
	 * Store led settings, for correct led behaviour.
	 * If the eeprom value is invalid,
	 * switch to default led mode.
	 */
2598
#ifdef CONFIG_RT2X00_LIB_LEDS
2599
	rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2600 2601
	value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);

2602 2603 2604 2605 2606
	rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
	rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
	if (value == LED_MODE_SIGNAL_STRENGTH)
		rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
				 LED_TYPE_QUALITY);
2607

2608 2609
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2610 2611
			   rt2x00_get_field16(eeprom,
					      EEPROM_LED_POLARITY_GPIO_0));
2612
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2613 2614
			   rt2x00_get_field16(eeprom,
					      EEPROM_LED_POLARITY_GPIO_1));
2615
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2616 2617
			   rt2x00_get_field16(eeprom,
					      EEPROM_LED_POLARITY_GPIO_2));
2618
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2619 2620
			   rt2x00_get_field16(eeprom,
					      EEPROM_LED_POLARITY_GPIO_3));
2621
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2622 2623
			   rt2x00_get_field16(eeprom,
					      EEPROM_LED_POLARITY_GPIO_4));
2624
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2625
			   rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2626
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2627 2628
			   rt2x00_get_field16(eeprom,
					      EEPROM_LED_POLARITY_RDY_G));
2629
	rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2630 2631
			   rt2x00_get_field16(eeprom,
					      EEPROM_LED_POLARITY_RDY_A));
2632
#endif /* CONFIG_RT2X00_LIB_LEDS */
2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750

	return 0;
}

/*
 * RF value list for RF5225 & RF5325
 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
 */
static const struct rf_channel rf_vals_noseq[] = {
	{ 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
	{ 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
	{ 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
	{ 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
	{ 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
	{ 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
	{ 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
	{ 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
	{ 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
	{ 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
	{ 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
	{ 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
	{ 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
	{ 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },

	/* 802.11 UNI / HyperLan 2 */
	{ 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
	{ 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
	{ 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
	{ 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
	{ 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
	{ 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
	{ 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
	{ 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },

	/* 802.11 HyperLan 2 */
	{ 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
	{ 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
	{ 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
	{ 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
	{ 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
	{ 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
	{ 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
	{ 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
	{ 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
	{ 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },

	/* 802.11 UNII */
	{ 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
	{ 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
	{ 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
	{ 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
	{ 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
	{ 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },

	/* MMAC(Japan)J52 ch 34,38,42,46 */
	{ 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
	{ 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
	{ 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
	{ 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
};

/*
 * RF value list for RF5225 & RF5325
 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
 */
static const struct rf_channel rf_vals_seq[] = {
	{ 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
	{ 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
	{ 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
	{ 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
	{ 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
	{ 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
	{ 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
	{ 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
	{ 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
	{ 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
	{ 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
	{ 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
	{ 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
	{ 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },

	/* 802.11 UNI / HyperLan 2 */
	{ 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
	{ 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
	{ 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
	{ 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
	{ 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
	{ 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
	{ 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
	{ 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },

	/* 802.11 HyperLan 2 */
	{ 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
	{ 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
	{ 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
	{ 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
	{ 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
	{ 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
	{ 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
	{ 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
	{ 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
	{ 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },

	/* 802.11 UNII */
	{ 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
	{ 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
	{ 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
	{ 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
	{ 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
	{ 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },

	/* MMAC(Japan)J52 ch 34,38,42,46 */
	{ 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
	{ 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
	{ 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
	{ 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
};

2751
static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2752 2753
{
	struct hw_mode_spec *spec = &rt2x00dev->spec;
2754 2755
	struct channel_info *info;
	char *tx_power;
2756 2757
	unsigned int i;

2758 2759 2760 2761 2762
	/*
	 * Disable powersaving as default.
	 */
	rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;

2763 2764 2765 2766
	/*
	 * Initialize all hw fields.
	 */
	rt2x00dev->hw->flags =
2767
	    IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2768 2769 2770
	    IEEE80211_HW_SIGNAL_DBM |
	    IEEE80211_HW_SUPPORTS_PS |
	    IEEE80211_HW_PS_NULLFUNC_STACK;
2771

2772
	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2773 2774 2775 2776 2777
	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
				rt2x00_eeprom_addr(rt2x00dev,
						   EEPROM_MAC_ADDR_0));

	/*
2778 2779 2780
	 * As rt61 has a global fallback table we cannot specify
	 * more then one tx rate per frame but since the hw will
	 * try several rates (based on the fallback table) we should
2781
	 * initialize max_report_rates to the maximum number of rates
2782 2783 2784 2785
	 * we are going to try. Otherwise mac80211 will truncate our
	 * reported tx rates and the rc algortihm will end up with
	 * incorrect data.
	 */
2786 2787
	rt2x00dev->hw->max_rates = 1;
	rt2x00dev->hw->max_report_rates = 7;
2788 2789 2790
	rt2x00dev->hw->max_rate_tries = 1;

	/*
2791 2792
	 * Initialize hw_mode information.
	 */
2793 2794
	spec->supported_bands = SUPPORT_BAND_2GHZ;
	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2795

I
Ivo van Doorn 已提交
2796
	if (!test_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags)) {
2797 2798 2799 2800 2801 2802 2803
		spec->num_channels = 14;
		spec->channels = rf_vals_noseq;
	} else {
		spec->num_channels = 14;
		spec->channels = rf_vals_seq;
	}

2804
	if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2805
		spec->supported_bands |= SUPPORT_BAND_5GHZ;
2806
		spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2807 2808 2809 2810 2811
	}

	/*
	 * Create channel information array
	 */
2812
	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2813 2814 2815 2816
	if (!info)
		return -ENOMEM;

	spec->channels_info = info;
2817

2818
	tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2819 2820 2821 2822
	for (i = 0; i < 14; i++) {
		info[i].max_power = MAX_TXPOWER;
		info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
	}
2823

2824 2825
	if (spec->num_channels > 14) {
		tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2826 2827 2828 2829
		for (i = 14; i < spec->num_channels; i++) {
			info[i].max_power = MAX_TXPOWER;
			info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
		}
2830
	}
2831 2832

	return 0;
2833 2834 2835 2836 2837
}

static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
{
	int retval;
2838
	u32 reg;
2839

P
Pavel Roskin 已提交
2840 2841 2842
	/*
	 * Disable power saving.
	 */
2843
	rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
P
Pavel Roskin 已提交
2844

2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855
	/*
	 * Allocate eeprom data.
	 */
	retval = rt61pci_validate_eeprom(rt2x00dev);
	if (retval)
		return retval;

	retval = rt61pci_init_eeprom(rt2x00dev);
	if (retval)
		return retval;

2856 2857 2858 2859
	/*
	 * Enable rfkill polling by setting GPIO direction of the
	 * rfkill switch GPIO pin correctly.
	 */
2860
	rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
2861
	rt2x00_set_field32(&reg, MAC_CSR13_DIR5, 1);
2862
	rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
2863

2864 2865 2866
	/*
	 * Initialize hw specifications.
	 */
2867 2868 2869
	retval = rt61pci_probe_hw_mode(rt2x00dev);
	if (retval)
		return retval;
2870

2871 2872 2873 2874
	/*
	 * This device has multiple filters for control frames,
	 * but has no a separate filter for PS Poll frames.
	 */
I
Ivo van Doorn 已提交
2875
	__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2876

2877
	/*
2878
	 * This device requires firmware and DMA mapped skbs.
2879
	 */
I
Ivo van Doorn 已提交
2880 2881
	__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
	__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
2882
	if (!modparam_nohwcrypt)
I
Ivo van Doorn 已提交
2883 2884
		__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
	__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896

	/*
	 * Set the rssi offset.
	 */
	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;

	return 0;
}

/*
 * IEEE80211 stack callback functions.
 */
2897 2898
static int rt61pci_conf_tx(struct ieee80211_hw *hw,
			   struct ieee80211_vif *vif, u16 queue_idx,
2899 2900 2901 2902 2903 2904 2905
			   const struct ieee80211_tx_queue_params *params)
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	struct data_queue *queue;
	struct rt2x00_field32 field;
	int retval;
	u32 reg;
2906
	u32 offset;
2907 2908 2909 2910 2911 2912 2913

	/*
	 * First pass the configuration through rt2x00lib, that will
	 * update the queue settings and validate the input. After that
	 * we are free to update the registers based on the value
	 * in the queue parameter.
	 */
2914
	retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2915 2916 2917
	if (retval)
		return retval;

2918 2919
	/*
	 * We only need to perform additional register initialization
2920
	 * for WMM queues.
2921 2922 2923 2924
	 */
	if (queue_idx >= 4)
		return 0;

2925
	queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2926 2927

	/* Update WMM TXOP register */
2928 2929 2930 2931
	offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
	field.bit_offset = (queue_idx & 1) * 16;
	field.bit_mask = 0xffff << field.bit_offset;

2932
	rt2x00mmio_register_read(rt2x00dev, offset, &reg);
2933
	rt2x00_set_field32(&reg, field, queue->txop);
2934
	rt2x00mmio_register_write(rt2x00dev, offset, reg);
2935 2936 2937 2938 2939

	/* Update WMM registers */
	field.bit_offset = queue_idx * 4;
	field.bit_mask = 0xf << field.bit_offset;

2940
	rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, &reg);
2941
	rt2x00_set_field32(&reg, field, queue->aifs);
2942
	rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg);
2943

2944
	rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, &reg);
2945
	rt2x00_set_field32(&reg, field, queue->cw_min);
2946
	rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg);
2947

2948
	rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, &reg);
2949
	rt2x00_set_field32(&reg, field, queue->cw_max);
2950
	rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg);
2951 2952 2953 2954

	return 0;
}

2955
static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2956 2957 2958 2959 2960
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	u64 tsf;
	u32 reg;

2961
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, &reg);
2962
	tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2963
	rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, &reg);
2964 2965 2966 2967 2968 2969 2970
	tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);

	return tsf;
}

static const struct ieee80211_ops rt61pci_mac80211_ops = {
	.tx			= rt2x00mac_tx,
2971 2972
	.start			= rt2x00mac_start,
	.stop			= rt2x00mac_stop,
2973 2974 2975
	.add_interface		= rt2x00mac_add_interface,
	.remove_interface	= rt2x00mac_remove_interface,
	.config			= rt2x00mac_config,
I
Ivo van Doorn 已提交
2976
	.configure_filter	= rt2x00mac_configure_filter,
2977
	.set_key		= rt2x00mac_set_key,
2978 2979
	.sw_scan_start		= rt2x00mac_sw_scan_start,
	.sw_scan_complete	= rt2x00mac_sw_scan_complete,
2980
	.get_stats		= rt2x00mac_get_stats,
2981
	.bss_info_changed	= rt2x00mac_bss_info_changed,
2982
	.conf_tx		= rt61pci_conf_tx,
2983
	.get_tsf		= rt61pci_get_tsf,
2984
	.rfkill_poll		= rt2x00mac_rfkill_poll,
I
Ivo van Doorn 已提交
2985
	.flush			= rt2x00mac_flush,
2986 2987
	.set_antenna		= rt2x00mac_set_antenna,
	.get_antenna		= rt2x00mac_get_antenna,
2988
	.get_ringparam		= rt2x00mac_get_ringparam,
2989
	.tx_frames_pending	= rt2x00mac_tx_frames_pending,
2990 2991 2992 2993
};

static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
	.irq_handler		= rt61pci_interrupt,
2994 2995 2996 2997
	.txstatus_tasklet	= rt61pci_txstatus_tasklet,
	.tbtt_tasklet		= rt61pci_tbtt_tasklet,
	.rxdone_tasklet		= rt61pci_rxdone_tasklet,
	.autowake_tasklet	= rt61pci_autowake_tasklet,
2998 2999
	.probe_hw		= rt61pci_probe_hw,
	.get_firmware_name	= rt61pci_get_firmware_name,
3000
	.check_firmware		= rt61pci_check_firmware,
3001
	.load_firmware		= rt61pci_load_firmware,
3002 3003
	.initialize		= rt2x00mmio_initialize,
	.uninitialize		= rt2x00mmio_uninitialize,
3004 3005
	.get_entry_state	= rt61pci_get_entry_state,
	.clear_entry		= rt61pci_clear_entry,
3006 3007 3008 3009 3010
	.set_device_state	= rt61pci_set_device_state,
	.rfkill_poll		= rt61pci_rfkill_poll,
	.link_stats		= rt61pci_link_stats,
	.reset_tuner		= rt61pci_reset_tuner,
	.link_tuner		= rt61pci_link_tuner,
3011 3012 3013
	.start_queue		= rt61pci_start_queue,
	.kick_queue		= rt61pci_kick_queue,
	.stop_queue		= rt61pci_stop_queue,
3014
	.flush_queue		= rt2x00mmio_flush_queue,
3015
	.write_tx_desc		= rt61pci_write_tx_desc,
3016
	.write_beacon		= rt61pci_write_beacon,
3017
	.clear_beacon		= rt61pci_clear_beacon,
3018
	.fill_rxdone		= rt61pci_fill_rxdone,
3019 3020
	.config_shared_key	= rt61pci_config_shared_key,
	.config_pairwise_key	= rt61pci_config_pairwise_key,
I
Ivo van Doorn 已提交
3021
	.config_filter		= rt61pci_config_filter,
3022
	.config_intf		= rt61pci_config_intf,
3023
	.config_erp		= rt61pci_config_erp,
3024
	.config_ant		= rt61pci_config_ant,
3025 3026 3027
	.config			= rt61pci_config,
};

I
Ivo van Doorn 已提交
3028
static const struct data_queue_desc rt61pci_queue_rx = {
3029
	.entry_num		= 32,
I
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3030 3031
	.data_size		= DATA_FRAME_SIZE,
	.desc_size		= RXD_DESC_SIZE,
3032
	.priv_size		= sizeof(struct queue_entry_priv_mmio),
I
Ivo van Doorn 已提交
3033 3034 3035
};

static const struct data_queue_desc rt61pci_queue_tx = {
3036
	.entry_num		= 32,
I
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3037 3038
	.data_size		= DATA_FRAME_SIZE,
	.desc_size		= TXD_DESC_SIZE,
3039
	.priv_size		= sizeof(struct queue_entry_priv_mmio),
I
Ivo van Doorn 已提交
3040 3041 3042
};

static const struct data_queue_desc rt61pci_queue_bcn = {
3043
	.entry_num		= 4,
3044
	.data_size		= 0, /* No DMA required for beacons */
I
Ivo van Doorn 已提交
3045
	.desc_size		= TXINFO_SIZE,
3046
	.priv_size		= sizeof(struct queue_entry_priv_mmio),
I
Ivo van Doorn 已提交
3047 3048
};

3049
static const struct rt2x00_ops rt61pci_ops = {
G
Gertjan van Wingerde 已提交
3050 3051 3052 3053 3054
	.name			= KBUILD_MODNAME,
	.max_ap_intf		= 4,
	.eeprom_size		= EEPROM_SIZE,
	.rf_size		= RF_SIZE,
	.tx_queues		= NUM_TX_QUEUES,
3055
	.extra_tx_headroom	= 0,
G
Gertjan van Wingerde 已提交
3056 3057 3058 3059 3060
	.rx			= &rt61pci_queue_rx,
	.tx			= &rt61pci_queue_tx,
	.bcn			= &rt61pci_queue_bcn,
	.lib			= &rt61pci_rt2x00_ops,
	.hw			= &rt61pci_mac80211_ops,
3061
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
G
Gertjan van Wingerde 已提交
3062
	.debugfs		= &rt61pci_rt2x00debug,
3063 3064 3065 3066 3067 3068
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
};

/*
 * RT61pci module information.
 */
3069
static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
3070
	/* RT2561s */
3071
	{ PCI_DEVICE(0x1814, 0x0301) },
3072
	/* RT2561 v2 */
3073
	{ PCI_DEVICE(0x1814, 0x0302) },
3074
	/* RT2661 */
3075
	{ PCI_DEVICE(0x1814, 0x0401) },
3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089
	{ 0, }
};

MODULE_AUTHOR(DRV_PROJECT);
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
			"PCI & PCMCIA chipset based cards");
MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
MODULE_FIRMWARE(FIRMWARE_RT2561);
MODULE_FIRMWARE(FIRMWARE_RT2561s);
MODULE_FIRMWARE(FIRMWARE_RT2661);
MODULE_LICENSE("GPL");

3090 3091 3092 3093 3094 3095
static int rt61pci_probe(struct pci_dev *pci_dev,
			 const struct pci_device_id *id)
{
	return rt2x00pci_probe(pci_dev, &rt61pci_ops);
}

3096
static struct pci_driver rt61pci_driver = {
3097
	.name		= KBUILD_MODNAME,
3098
	.id_table	= rt61pci_device_table,
3099
	.probe		= rt61pci_probe,
B
Bill Pemberton 已提交
3100
	.remove		= rt2x00pci_remove,
3101 3102 3103 3104
	.suspend	= rt2x00pci_suspend,
	.resume		= rt2x00pci_resume,
};

A
Axel Lin 已提交
3105
module_pci_driver(rt61pci_driver);