This patch adds audio controller, codec and simple card node of
UniPhier AIO sound system for LD11/20 SoCs.
Signed-off-by: NKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

When a full/low speed device is connected to USB 2.0 port on UniPhier SoC
that has ehci controller, the kernel shows the following messages.

| usb usb1-port1: Cannot enable. Maybe the USB cable is bad?
| usb usb1-port1: Cannot enable. Maybe the USB cable is bad?
| usb usb1-port1: Cannot enable. Maybe the USB cable is bad?
| usb usb1-port1: unable to enumerate USB device

To fix the issue, the driver needs to enable Transaction Translator on ehci
root hub. This adds 'has-transaction-translator' property to each node.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The dt-bindings header was applied to the driver subsystem.  I had to
wait for a merge window to use it from DT.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add resets properties to all nodes that have reset lines.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add mmc-pwrseq-emmc node to perform standard eMMC hardware reset
procedure.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The GPIO controller also acts as an interrupt controller and the
interrupt lines are connected to the AIDET block.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Fix warnings like follows:

Warning (node_name_chars_strict): Character '_' not recommended in ...

Commit 8654cb8d ("dtc: update warning settings for new bus and
node/property name checks") says these checks are a bit subjective,
but Rob also says to not add new W=2 warnings.

The exising warnings should be fixed in order to catch new ones
easily.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add efuse node for UniPhier LD11, LD20, and PXs3.
This efuse node is included in soc-glue.
Signed-off-by: NKeiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Without the STDMAC clock enabled, the USB 2.0 hosts do not work.
This clock must be explicitly listed in the "clocks" property because
it is independent of the other clocks.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add UniPhier AIDET (ARM Interrupt Detector) nodes to support
active low interrupts.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This patch adds reset controller node of analog signal amplifier
core (ADAMV) for UniPhier LD11/LD20 SoCs.
Signed-off-by: NKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add NAND controller node to LD11 and LD20.  Neither of them supports
the CS1 line, so pinctrl is set up for a single CS line.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

To include dt-bindings headers.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add nodes of watchdog timer for UniPhier LD11 and LD20 SoC.
The watchdog timer is included in sysctrl.
Signed-off-by: NKeiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Follow the recent trend for the license description, and fix the wrongly
stated X11 to MIT.

The X11 license text [1] is explicitly for the X Consortium and has a
couple of extra clauses.  The MIT license text [2] is actually what the
current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.htmlSigned-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Reserve enough space below the kernel base.
The assumed address map is:
  80000000 - 80ffffff : for IPP
  81000000 - 81ffffff : for ARM secure
  82000000 -          : for Linux
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Compiling the UniPhier DT files with W=1, DTC warns like follows:

Warning (simple_bus_reg): Node /soc/smpctrl@59800000 simple-bus unit address format error, expected "59801000"
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property

Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reported-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Adjust the PHY parameters for more stable access to the eMMC device.
Set the SDCLK output delay value to 21 (including HS200/400 modes).
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Since commit a89c472d ("mmc: sdhci-cadence: Update PHY delay
configuration"), PHY parameters must be specified by DT.

The hard-coded settings have been converted as follows:
- SDHCI_CDNS_PHY_DLY_SD_DEFAULT -> cdns,phy-input-delay-legacy
- SDHCI_CDNS_PHY_DLY_EMMC_SDR   -> cdns,phy-input-delay-mmc-highspeed
- SDHCI_CDNS_PHY_DLY_EMMC_DDR   -> cdns,phy-input-delay-mmc-ddr

The following have not been moved:
- SDHCI_CDNS_PHY_DLY_SD_HS
   this is unneeded in the eMMC configuration
- SDHCI_CDNS_PHY_DLY_EMMC_LEGACY
   this is never enabled by the driver as it is covered by
   SDHCI_CDNS_PHY_DLY_SD_DEFAULT
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Deassert the bit in the System Control block before the MIO block.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now everything is ready to enable this pinctrl.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Fix warnings reported when built with W=1:
  Node /memory has a reg or ranges property, but no unit name
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add Cadence's eMMC controller node for LD11/LD20.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The LD11 SoC is equipped with SD-ctrl (0x59810000) as well as
MIO-ctrl (0x5b3e0000).  The SD-ctrl block on this SoC has just
one register for controlling RST_n pin of the eMMC device.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These hardware blocks are SoC-specific, so their compatible strings
should be SoC-specific as well.  This change has no impact on the
actual behavior since it is controlled by the generic "simple-mfd",
"syscon" compatible strings.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.

Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>

The System Control node has 0x10000 byte of registers.  The current
reg size must be expanded to use the cpufreq driver because the
registers controlling CPU frequency are located at offset 0x8000.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI.
Now I finished porting the ATF BL31 for the UniPhier platform, so it
is ready to migrate to PSCI enable method.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This is a low-cost 64bit SoC from Socionext.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This is a simple MFD, but add a specific compatible just in case.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The UniPhier reset controller driver has been merged.  Enable it.
Also, replace the fixed-rate clocks with the dedicated clock
drivers.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This pinctrl is needed to get access to the UniPhier System Bus.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

All UniPhier device trees have the common prefix "uniphier-", so
"ph1-" is just making names longer.  Recent documents and other
projects are not using PH1- prefixes any more.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

At first, 256 byte of the head of DRAM space was reserved for some
reasons.  However, as the progress of development, it turned out
unnecessary, and it was never used in the end.  Move the CPU release
address to leave no space.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This node consists of various system-level configuration registers.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add a master clock node generated by a 25MHz crystal oscillator.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The I2C hardware blocks on this SoC are connected as follows:

  I2C0: external connection
  I2C1: external connection
  I2C2: internal connection
  I2C3: external connection
  I2C4: external connection
  I2C5: internal connection
  I2C6: no connection (not accessible)

Delete pinctrl from Ch2, add pinctrl to Ch4, and remove the Ch6 node.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

During the review process of the UniPhier System Bus driver
(drivers/bus/uniphier.c), the current binding of the System Bus
Controller turned out to be no good.  In order to make the driver
really usable, we have to switch over to the new binding defined by
Documentation/devicetree/bindings/bus/uniphier-system-bus.txt.
The old binding will be still supported for a while to keep the
backward compatibility.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>