1. 14 2月, 2013 1 次提交
    • G
      pps: Move timestamp read into PPS code proper · 593fb1ae
      George Spelvin 提交于
      The PPS (Pulse-Per-Second) line discipline has developed a number of
      unhealthy attachments to core tty data and functions, ultimately leading
      to its breakage.
      
      The previous patches fixed the crashing.  This one reduces coupling further
      by eliminating the timestamp parameter from the dcd_change ldisc method.
      This reduces header file linkage and makes the extension more generic,
      and the timestamp read is delayed only slightly, from just before the
      ldisc->ops->dcd_change method call to just after.
      
      Fix attendant build breakage in
          drivers/tty/n_tty.c
          drivers/tty/tty_buffer.c
          drivers/staging/speakup/selection.c
          drivers/staging/dgrp/dgrp_*.c
      
      Cc: William Hubbs <w.d.hubbs@gmail.com>
      Cc: Chris Brannon <chris@the-brannons.com>
      Cc: Kirk Reiser <kirk@braille.uwo.ca>
      Cc: Samuel Thibault <samuel.thibault@ens-lyon.org>
      Signed-off-by: NPeter Hurley <peter@hurleysoftware.com>
      Signed-off-by: NGeorge Spelvin <linux@horizon.com>
      Acked-by: NRodolfo Giometti <giometti@enneenne.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      593fb1ae
  2. 30 1月, 2013 1 次提交
  3. 16 1月, 2013 3 次提交
  4. 04 11月, 2012 3 次提交
  5. 13 10月, 2012 1 次提交
  6. 27 9月, 2012 2 次提交
  7. 17 8月, 2012 1 次提交
    • A
      serial: New serial driver MAX310X · f6544418
      Alexander Shiyan 提交于
      This driver is a replacement for a MAX3107 driver with a lot of
      improvements and new features.
      The main differences from the old version:
      - Using the regmap.
      - Using devm_XXX-related functions.
      - The use of threaded IRQ with IRQF_ONESHOT flag allows the driver to
        the hardware that supports only level IRQ.
      - Improved error handling of serial port, improved FIFO handling,
        improved hardware & software flow control.
      - Advanced flags allows turn on RS-485 mode (Auto direction control).
      - Ability to load multiple instances of drivers.
      - Added support for MAX3108.
      - GPIO support.
      - Driver is quite ready for adding I2C support and support other ICs
        with compatible registers set (MAX3109, MAX14830).
      Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      f6544418
  8. 27 7月, 2012 1 次提交
  9. 13 6月, 2012 1 次提交
  10. 19 4月, 2012 1 次提交
  11. 10 4月, 2012 2 次提交
  12. 10 3月, 2012 1 次提交
    • P
      serial: introduce generic port in/out helpers · 927353a7
      Paul Gortmaker 提交于
      Looking at the existing serial drivers (esp. the 8250 derived
      variants) we see a common trend.  They create a hardware specific
      port struct, which in turn contains a generic serial_port struct.
      
      The other trend, is that they all create some sort of shortcut
      to go through the hardware specific struct, to the serial_port
      struct, which has the basic in/out operations within.  Looking
      for the serial_in and serial_out in several drivers shows this.
      
      Rather than let this continue, lets create a generic set of
      similar helper wrappers that can be used on a struct port, so
      we can eliminate bouncing out through hardware specific struct
      pointers just to come back into struct port where possible.
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      Acked-by: NAlan Cox <alan@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      927353a7
  13. 27 1月, 2012 1 次提交
  14. 08 12月, 2011 1 次提交
  15. 27 11月, 2011 1 次提交
  16. 16 11月, 2011 1 次提交
    • J
      TTY: serial, cleanup include file · 027d7dac
      Jiri Slaby 提交于
      There are some functions (uart_handle_dcd_change, _handle_cts_change,
      _insert_char) which are big enough to not be inlined. So move them
      from .h to .c. We need to export them so that modules can actually use
      them.
      
      They will be even bigger when we introduce tty refcounting to them.
      
      While at it, cleanup the "Proud member of Uglyhacks'R'US". It means,
      define uart_handle_sysrq_char only when SUPPORT_SYSRQ is set.
      Otherwise define it as a macro. This is needed for some arm driver
      where the second parameter is undefined if expanded.
      Signed-off-by: NJiri Slaby <jslaby@suse.cz>
      Cc: Alan Cox <alan@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      027d7dac
  17. 23 9月, 2011 1 次提交
  18. 24 8月, 2011 3 次提交
  19. 20 5月, 2011 1 次提交
    • S
      tty/serial: Add explicit PORT_TEGRA type · 4539c24f
      Stephen Warren 提交于
      Tegra's UART is currently auto-detected as PORT_XSCALE due to register
      bit UART_IER.UUE being writable. However, the Tegra documentation states
      that this register bit is reserved. Hence, we should not program it.
      
      Instead, the documentation specifies that the UART is 16550 compatible.
      However, Tegra does need register bit UART_IER.RTOIE set, which is not
      enabled by any 16550 port type. This was not noticed before, since
      PORT_XSCALE enables CAP_UUE, which conflates both UUE and RTOIE bit
      programming.
      
      This change defines PORT_TEGRA that doesn't set UART_CAP_UUE, but does
      set UART_CAP_RTOIE, which is a new capability indicating that the RTOIE
      bit needs to be enabled.
      Based-on-code-by: NLaxman Dewangan <ldewangan@nvidia.com>
      Cc: Laxman Dewangan <ldewangan@nvidia.com>
      Signed-off-by: NStephen Warren <swarren@nvidia.com>
      Acked-by: NAlan Cox <alan@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      4539c24f
  20. 04 5月, 2011 1 次提交
  21. 14 1月, 2011 1 次提交
  22. 17 12月, 2010 1 次提交
  23. 11 12月, 2010 1 次提交
    • J
      8250: add a UPIO_DWAPB32 for 32 bit accesses · a3ae0fc3
      Jamie Iles 提交于
      Some platforms contain a Synopsys DesignWare APB UART that is attached
      to a 32-bit APB bus where sub-word accesses are not allowed. Add a new
      IO type (UPIO_DWAPB32) that performs 32 bit acccesses to the UART.
      
      v2:
      	- don't test for 32 bit in the output fast path, provide a
      	  separate dwabp32_serial_out() function. Refactor
      	  dwabp_serial_out() so that we can reuse the LCR saving
      	  code.
      v3:
      	- rebased on top of "8250: use container_of() instead of
      	  casting"
      Signed-off-by: NJamie Iles <jamie@jamieiles.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      a3ae0fc3
  24. 17 11月, 2010 1 次提交
  25. 12 11月, 2010 1 次提交
  26. 23 10月, 2010 2 次提交
  27. 30 9月, 2010 1 次提交
  28. 04 9月, 2010 1 次提交
  29. 21 8月, 2010 1 次提交
  30. 11 8月, 2010 2 次提交
    • P
      U6715 16550A serial driver support · 235dae5d
      Philippe Langlais 提交于
      UART Features extract from STEricsson U6715 data-sheet (arm926 SoC for mobile phone):
      * Fully compatible with industry standard 16C550 and 16C450 from various
      manufacturers
      * RX and TX 64 byte FIFO reduces CPU interrupts
      * Full double buffering
      * Modem control signals include CTS, RTS, (and DSR, DTR on UART1 only)
      * Automatic baud rate selection
      * Manual or automatic RTS/CTS smart hardware flow control
      * Programmable serial characteristics:
      – Baud rate generation (50 to 3.25M baud)
      – 5, 6, 7 or 8-bit characters
      – Even, odd or no-parity bit generation and detection
      – 1, 1.5 or 2 stop bit generation
      * Independent control of transmit, receive, line status, data set interrupts and FIFOs
      * Full status-reporting capabilities
      * Separate DMA signaling for RX and TX
      * Timed interrupt to spread receive interrupt on known duration
      * DMA time-out interrupt to allow detection of end of reception
      * Carkit pulse coding and decoding compliant with USB carkit control interface [40]
      
      In 16550A auto-configuration, if the fifo size is 64 then it's an U6 16550A port
      Add set_termios hook & export serial8250_do_set_termios to change uart
      clock following baudrate
      Signed-off-by: NPhilippe Langlais <philippe.langlais@stericsson.com>
      Acked-by: NAlan Cox <alan@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      235dae5d
    • F
      hsu: driver for Medfield High Speed UART device · d843fc6e
      Feng Tang 提交于
      This is a PCI & UART driver, which suppors both PIO and DMA mode
      UART operation. It has 3 identical UART ports and one internal
      DMA controller.
      
      Current FW will export 4 pci devices for hsu: 3 uart ports and 1
      dma controller, each has one IRQ line. And we need to discuss the
      device model, one PCI device covering whole HSU should be a better
      model, but there is a problem of how to export the 4 IRQs info
      
      Current driver set the highest baud rate to 2746800bps, which is
      easy to scale down to 115200/230400.... To suport higher baud rate,
      we need add special process, change DLAB/DLH/PS/DIV/MUL registers
      all together.
      
      921600 is the highest baud rate that has been tested with Bluetooth
      modem connected to HSU port 0. Will test more when there is right
      BT firmware.
      
      Current version contains several work around for A0's Silicon bugs
      Signed-off-by: NFeng Tang <feng.tang@intel.com>
      Signed-off-by: NAlan Cox <alan@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      d843fc6e