Add the host1x node along with its children to the Tegra20 DTSI. Board-
specific DTS files are expected to enable the available outputs and
complement the device tree with data specific to the hardware.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

TrimSlice contains a 1MiB SPI flash. Represent this in the device tree.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Nvidia's Tegra20 have the SPI (SFLASH) controller to
interface with spi flash device which is used for system
boot. Add DT entry for this controller.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: move sflash node to keep file sorted]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Harmony board has an ON Semiconductors NCT1008 temperature sensor
connected to the DVC bus. It can be used to monitor the ambient (local)
and on-die (remote) temperatures.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tamonten SOM has an ON Semiconductor NCT1008 connected to the DVC
bus which is used to measure the ambient (local) temperature as well as
the on-die (remote) temperature.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Harmony board has an Analog Devices ADT7461 temperature sensor
connected to the DVC bus. It can be used to monitor the ambient (local)
and on-die (remote) temperatures.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

These properties are already set by the tegra20-tamonten.dtsi, so they
don't need to be repeated.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This commit allows the I2C2 controller on Tegra20 to be routed either to
the DDC or the PTA pin group at runtime. On Tamonten this allows the I2C
bus to be used for the DDC of the HDMI connector or to access I2C chips
on the carrier board.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Enable SLINK4 and connected device in Tegra30 based
platform Cardhu.
Setting maximum spi frequency to 25MHz.

SPI serial flash is connected on CS1 of SLINK4 on
cardhu platform.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: swapped reg/compatible order to be consistent]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add slink controller details in the dts file of
Tegra20 and Tegra30.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Tegra 2's I2C2 controller can be routed to either the PTA
or DDC pin group on Ventana. So:
- Remove the HDMI function definition of pta pingroup
- Define child i2c adapters(ddc & pta) for I2C2 controller
Signed-off-by: NMark Zhang <markz@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Configure pinmux as required for WiFi.
Enable the SDHCI1 controller for a02 and a04 board, which is connected to the
WiFi module.
For now, always enable the regulator that provides power to the Wifi module.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Configure pinmux as required for WiFi.
Enable the SDHCI1 controller, which is connectted to the WiFi module.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Enable the SDHCI1 controller. This is connected to the WiFi module.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Setup the clock parents for the two display controllers and HDMI.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the OF_DEV_AUXDATA table entries required to associate the proper
names with host1x and its children. In turn, this allows the devices to
find the required clocks.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Extend the pll_d frequency table with a few entries to support common
HDMI and LVDS display modes and setup the clock parents for the two
display controllers and HDMI.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add the OF_DEV_AUXDATA table entries required to associate the proper
names with host1x and its children. In turn, this allows the devices to
find the required clocks.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch adds speedo-based process identification support for Tegra30.
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
[swarren s/Tegra3/Tegra30/ in log print,
s/T30/Tegra30/ in commit description]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Detect CPU and core process ID by checking speedo corner tables.
This can provide a more accurate process ID.
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
[swarren s/Tegra2/Tegra20/ in log print]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Change the spare fuse base from a definition to a variable.
It provides flexibilty to read spare fuse on different chip.
Signed-off-by: NDanny Huang <dahuang@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This patch implements ARM linux patch 6395/1 for Tegra. See commit
1a8e41cd "ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache
controller) AuxCtlr register" for details.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
[swarren: added commit subject for referenced patch]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add OF_DEV_AUXDATA for sflash controller driver for Tegra20
board dt files.
Set the parent clock of sflash controller to PLLP and configure
clock to 20MHz.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Enable the data prefetch on L2. The bit28 in aux ctrl register.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30
board dt files.
Set the parent clock of slink controller to PLLP and configure
clock to 100MHz.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Moving L2 cache init to DT support.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add L2 cache controller binding into DT for Tegra.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Adding the AHB and APB bus clock for Tegra30.
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Set up the wlan clock tree for Tegra20 and Tegra30.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Nothing outside mach-tegra uses this file, so there's no need for it to
be in <mach/>.

Since uncompress.h and debug-macro.S remain in include/mach, they need
to include "../../irammap.h" becaue of this change. Both these usages
will be removed shortly, when Tegra's DEBUG_LL implementation is updated
not to pass information through IRAM.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Nothing outside mach-tegra uses this file, so there's no need for it to
be in <mach/>.

Since uncompress.h and debug-macro.S remain in include/mach, they need
to include "../../iomap.h" becaue of this change. uncompress.h will soon
be deleted in later multi-platform/single-zImage patches. debug-macro.S
will need to continue to include this header using an explicit relative
path, to avoid duplicating the physical->virtual address mapping that
iomap.h dictates.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Remove includes of <mach/dma.h> from sound/soc; nothing from it is used.

Remove include of <mach/dma.h> from mach-tegra/apbio.c; since the DMA
transfers made by this file don't need flow-control with any peripheral,
there's no need to set any slave ID.

Once those changes are made, there are no remaining users of <mach/dma.h>
so remove it. Drivers should get this information from device tree. This
removal is necessary for single zImage.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

We wish to empty arch/arm/mach-tegra/include/mach/ as much as possible
to enable single zImage. Move tegra-ahb.h to a more central location
(suggested by Arnd, OK'd by Greg KH), and actually make tegra-ahb.c
include the header to ensure client and provider agree on the prototype.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This should make it easier to delete or move <mach/*.h>; something that
is useful for single-zImage.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Commit 13511def "regulator: deprecate regulator-compatible DT property"
now allows for simpler content within the regulators node within a PMIC.
Modify all the Tegra device tree files to take advantage of this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NThierry Reding <thierry.reding@avionic-design.de>

Just get %icc2 into the state we would have after local_irq_disable()
and physical IRQ having happened since then.  Then we can simply
use preempt_schedule_irq() and be done with the whole mess.
Acked-by: NDavid Howells <dhowells@redhat.com>
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>

Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>

The kernel_thread() changes for FRV don't work, and FRV fails to boot,
starting with:

	commit 02ce496f
	Author: Al Viro <viro@zeniv.linux.org.uk>
	Date:   Tue Sep 18 22:18:51 2012 -0400
	Subject: frv: split ret_from_fork, simplify kernel_thread() a lot

The problem is that the userspace registers are completely cleared when a
kernel thread is created and all subsequent user threads are then copied from
that.  Unfortunately, however, the TBR and PSR registers are restored from the
pt_regs and the values they should be set to are clobbered by the memset.

Instead, copy across the old user registers as normal, and then merely alter
GR8 and GR9 in it if we're going to execute a kernel thread.
Signed-off-by: NDavid Howells <dhowells@redhat.com>

Fix the preemption handling in FRV code where the PREEMPT_ACTIVE value is
incorrectly loaded into the threadinfo flags rather than the threadinfo
preemption count.

Unfortunately, the code cannot be simply converted to use
preempt_schedule_irq() as is because FRV uses virtual interrupt disablement to
cut down on the cost of actually disabling interrupts and thus
local_irq_enable() doesn't actually enable interrupts.
Reported-by: NAl Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: NDavid Howells <dhowells@redhat.com>
cc: Al Viro <viro@ZenIV.linux.org.uk>

Don't let objcopy transfer the GNU build_id note into the loadable image as it
is located at address 0 and the image ends up >3G in size.
Signed-off-by: NDavid Howells <dhowells@redhat.com>