1. 03 6月, 2015 4 次提交
    • S
      powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC · ec66a97d
      Shengzhou Liu 提交于
      The T1024 SoC includes the following function and features:
      - Two 64-bit Power architecture e5500 cores, up to 1.4GHz
      - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
      - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
      - Data Path Acceleration Architecture (DPAA) incorporating acceleration
      - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
      - High-speed peripheral interfaces
        - Three PCI Express 2.0 controllers
      - Additional peripheral interfaces
        - One SATA 2.0 controller
        - Two USB 2.0 controllers with integrated PHY
        - Enhanced secure digital host controller (SD/eSDHC/eMMC)
        - Enhanced serial peripheral interface (eSPI)
        - Four I2C controllers
        - Four 2-pin UARTs or two 4-pin UARTs
        - Integrated Flash Controller supporting NAND and NOR flash
      - Two 8-channel DMA engines
      - Multicore programmable interrupt controller (PIC)
      - LCD interface (DIU) with 12 bit dual data rate
      - QUICC Engine block supporting TDM, HDLC, and UART
      - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
      - Support for hardware virtualization and partitioning enforcement
      - QorIQ Platform's Trust Architecture 2.0
      Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
      [scottwood@freescale.com: whitespace fixes]
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      ec66a97d
    • S
      powerpc/e500mc: Remove dead L2 flushing code in idle_e500.S · 86d63363
      Scott Wood 提交于
      This code can never be executed as it is only built when
      CONFIG_PPC_E500MC is unset, but the only CPUs that have CPU_FTR_L2CSR
      require CONFIG_PPC_E500MC and do not have the MSR/HID0-based nap
      mechanism that this file uses.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      86d63363
    • S
      powerpc/e6500: Optimize hugepage TLB misses · c89ca8ab
      Scott Wood 提交于
      Some workloads take a lot of TLB misses despite using traditional
      hugepages.  Handle these TLB misses in the asm fastpath rather than
      going through a bunch of C code.  With this patch I measured around a
      5x speedup in handling hugepage TLB misses.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      c89ca8ab
    • I
      powerpc/dts: Unify B4 mux nodes · fb326e98
      Igal Liberman 提交于
      Signed-off-by: NIgal Liberman <Igal.Liberman@freescale.com>
      Change-Id: Ic5f28f7b492b708f00a5ff74dda723ce5e1da0ba
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      fb326e98
  2. 02 6月, 2015 10 次提交
  3. 22 5月, 2015 15 次提交
  4. 20 5月, 2015 1 次提交
    • L
      powerpc: Enable sys_kcmp() for CRIU · 7978f76c
      Laurent Dufour 提交于
      The commit 8170a83f ("powerpc: Wireup the kcmp syscall to sys_ni") has
      disabled the kcmp syscall for powerpc.  This has been done due to the use
      of unsigned long parameters which may require a dedicated wrapper to handle
      32bit process on top of 64bit kernel.  However in the kcmp() case, the 2
      unsigned long parameters are currently only used to carry file descriptors
      from user space to the kernel.  Since such a parameter is passed through
      register, and file descriptor doesn't need to get extended, there is,
      today, no need for a wrapper.
      
      In the case there will be a need to pass address in or out of this system
      call, then a wrapper could be required, it will then be to care of it.
      
      As today this is not the case, it is safe to enable kcmp() on powerpc.
      
      Tested (by Laurent) on 64-bit, 32-bit, and 32-bit userspace on 64-bit
      kernel using tools/testing/selftests/kcmp [mpe].
      Signed-off-by: NLaurent Dufour <ldufour@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      7978f76c
  5. 18 5月, 2015 1 次提交
  6. 13 5月, 2015 4 次提交
  7. 12 5月, 2015 3 次提交
  8. 11 5月, 2015 2 次提交