1. 16 9月, 2011 1 次提交
  2. 11 8月, 2011 1 次提交
  3. 21 6月, 2011 2 次提交
  4. 05 5月, 2011 1 次提交
  5. 14 4月, 2011 4 次提交
  6. 12 3月, 2011 1 次提交
  7. 08 3月, 2011 2 次提交
  8. 03 3月, 2011 7 次提交
  9. 17 11月, 2010 2 次提交
    • D
      ixgbe: make silicon specific functions generic · a391f1d5
      Don Skidmore 提交于
      The new MAC type X540 shares much of the same functionality of
      some silicon specific functions.  To reduce duplicate code,
      made these functions generic.
      Signed-off-by: NDon Skidmore <donald.c.skidmore@intel.com>
      Tested-by: NStephen Ko <stephen.s.ko@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      a391f1d5
    • J
      ixgbe: DCB set PFC high and low water marks per data sheet specs · 16b61beb
      John Fastabend 提交于
      Currently the high and low water marks for PFC are being set
      conservatively for jumbo frames. This means the RX buffers
      are being underutilized in the default 1500 MTU. This patch
      fixes this so that the water marks are set as described in
      the data sheet considering the MTU size.
      
      The equation used is,
      
      RTT * 1.44 + MTU * 1.44 + MTU
      
      Where RTT is the round trip time and MTU is the max frame size
      in KB. To avoid floating point arithmetic FC_HIGH_WATER is
      defined
      
      ((((RTT + MTU) * 144) + 99) / 100) + MTU
      
      This changes how the hardware field fc.low_water and
      fc.high_water are used. With this change they are no longer
      storing the actual low water and high water markers but are
      storing the required head room in the buffer. This simplifies
      the logic and we do not need to account for the size of the
      buffer when setting the thresholds.
      
      Testing with iperf and 16 threads showed a slight uptick in
      throughput over a single traffic class .1-.2Gbps and a reduction
      in pause frames. Without the patch a 30 second run would show
      ~10-15 pause frames being transmitted with the patch ~2-5 are
      seen. Test were run back to back with 82599.
      
      Note RXPBSIZE is in KB and low and high water marks fields are
      also in KB. However the FCRT* registers are 32B granularity and
      right shifted 5 into the register,
      
      (((rx_pbsize - water_mark) * 1024) / 32) << 5
      
      is the most explicit conversion here we simplify
      
      (rx_pbsize - water_mark) * 32 << 5 = (rx_pbsize - water_mark) << 10
      
      This patch updates the PFC thresholds and legacy FC thresholds.
      Signed-off-by: NJohn Fastabend <john.r.fastabend@intel.com>
      Tested-by: NRoss Brattain <ross.b.brattain@intel.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      16b61beb
  10. 21 5月, 2010 1 次提交
  11. 14 5月, 2010 1 次提交
  12. 16 2月, 2010 1 次提交
  13. 14 1月, 2010 1 次提交
  14. 16 12月, 2009 1 次提交
  15. 01 10月, 2009 1 次提交
  16. 15 9月, 2009 1 次提交
  17. 02 9月, 2009 1 次提交
  18. 27 8月, 2009 1 次提交
  19. 04 8月, 2009 1 次提交
  20. 18 7月, 2009 1 次提交
  21. 07 6月, 2009 1 次提交
  22. 27 5月, 2009 1 次提交
  23. 18 5月, 2009 2 次提交
  24. 30 4月, 2009 1 次提交
  25. 11 4月, 2009 3 次提交