1. 21 9月, 2007 6 次提交
    • P
      sh: Support explicit L1 cache disabling. · e7bd34a1
      Paul Mundt 提交于
      This reworks the cache mode configuration in Kconfig, and allows for
      explicit selection of write-back/write-through/off configurations.
      All of the cache flushing routines are optimized away for the off
      case.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      e7bd34a1
    • M
      sh: intc - avoid SH7710 specific vector on SH7712 · ac919986
      Magnus Damm 提交于
      This patch makes sure that the sh7710 specific ipsec vector is missing
      if building for a sh7712. All according to the datasheet.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      ac919986
    • M
      sh: intc - add missing vectors for SH7707 · 1301e715
      Magnus Damm 提交于
      This patch adds a few missing vectors for sh7707. The only interrupt
      controller differences between sh7707 and sh7709 seem to be added
      vectors for one LCD controller and two PCMCIA slots.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      1301e715
    • M
      sh: intc - add support for SH7706, SH7707, SH7708, SH7709 · ec58f1f3
      Magnus Damm 提交于
      This patch unifies the cpu specific interrupt setup code for
      sh7706, sh7707, sh7708 and sh7709 and moves the code into a new
      file called setup-sh770x.c.  It makes sense to share the setup code
      between these processors because most hardware blocks are identical
      from a software point of view. With this patch the sh770x processors
      now have a complete set of vectors that match with the information
      provided by the data sheets. This is a big improvement for sh7708.
      
      Vectors for IRQ4 and IRQ5 are enabled by default. Use
      plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.
      
      This patch also unifies the platform device setup code which means
      that the rtc driver now has platform data for all sh770x processors.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      ec58f1f3
    • M
      sh: intc - add support for SH7710 · 28b146c8
      Magnus Damm 提交于
      This patch converts the cpu specific interrupt setup code
      for sh7710 from ipr to intc. While at it new vectors are added
      to match the information provided by the datasheet. Version two
      simplifies the Kconfig part.
      
      Vectors for IRQ4 and IRQ5 are enabled by default. Use
      plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.
      
      This patch also adds sh7710 specific platform data for the rtc
      driver. The base address of SCIF1 is adjusted to match the
      datasheet.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      28b146c8
    • M
      sh: intc - add support for SH7705 · 70e8be0a
      Magnus Damm 提交于
      This patch converts the cpu specific interrupt setup code for
      sh7705 from ipr to intc. While at it new vectors are added to
      match the information provided by the datasheet.
      
      Vectors for IRQ4 and IRQ5 are enabled by default.
      
      Use plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.
      
      This patch also adds sh7705 specific platform data for the rtc driver.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      70e8be0a
  2. 22 8月, 2007 1 次提交
  3. 01 8月, 2007 1 次提交
    • P
      sh: Fix lockdep debugging oops on SH-3/4. · c347d12c
      Paul Mundt 提交于
      In the SH-3/4 TLB access violation path we were enabling IRQs before
      the call in to trace_hardirqs_on(), which ended up triggering:
      
              if (DEBUG_LOCKS_WARN_ON(!irqs_disabled()))
                      return;
      
      in kernel/lockdep.c:2031. Fix this up by removing the early re-enable,
      we were already re-enabling IRQs post-trace_hardirqs_on() already, so
      the semantics are now as was initially intended.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      c347d12c
  4. 26 7月, 2007 2 次提交
  5. 25 7月, 2007 2 次提交
  6. 20 7月, 2007 10 次提交
  7. 16 7月, 2007 1 次提交
  8. 20 6月, 2007 2 次提交
  9. 15 6月, 2007 2 次提交
    • M
      sh: rework ipr code · 68abdbbb
      Magnus Damm 提交于
      This patch reworks the ipr code by grouping the offset array together
      with the ipr_data structure in a new data structure called ipr_desc.
      This new structure also contains the name of the controller in struct
      irq_chip. The idea behind putting struct irq_chip in there is that we
      can use offsetof() to locate the base addresses in the irq_chip
      callbacks. This strategy has much in common with the recently merged
      intc2 code.
      
      One logic change has been made - the original ipr code enabled the
      interrupts by default but with this patch they are all disabled by
      default.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      68abdbbb
    • M
      sh: rework intc2 code · d619500a
      Magnus Damm 提交于
      The shared intc2 code currently contains cpu-specific #ifdefs.
      This is a tad unclean and it prevents us from using the shared code
      to drive board-specific irqs on the se7780 board.
      
      This patch reworks the intc2 code by moving the base addresses of
      the intc2 registers into struct intc2_desc. This new structure also
      contains the name of the controller in struct irq_chip. The idea
      behind putting struct irq_chip in there is that we can use offsetof()
      to locate the base addresses in the irq_chip callbacks.
      
      One logic change has been made - the original shared intc2 code
      enabled the interrupts by default but with this patch they are all
      disabled by default.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      d619500a
  10. 11 6月, 2007 2 次提交
  11. 08 6月, 2007 4 次提交
  12. 04 6月, 2007 2 次提交
  13. 31 5月, 2007 2 次提交
  14. 21 5月, 2007 3 次提交