1. 15 4月, 2014 5 次提交
    • N
      ASoC: fsl_sai: Add clock controls for SAI · ca3e35c7
      Nicolin Chen 提交于
      The SAI mainly has the following clocks:
        bus clock
          control and configure registers and to generate synchronous
          interrupts and DMA requests.
      
        mclk1, mclk2, mclk3
          to generate the bit clock when the receiver or transmitter is
          configured for an internally generated bit clock.
      
      So this patch adds these clocks and their clock controls to the driver.
      
      [ To concern the old DTB cases, I've added a bit of extra code to make
        the driver compatible with them. And by marking clock NULL if failed
        to get, the clk_prepare() or clk_get_rate() would easily return 0
        so no further path should be broken. -- by Nicolin ]
      Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
      Acked-by: NXiubo Li <Li.Xiubo@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      ca3e35c7
    • N
      ASoC: fsl_sai: Add imx6sx platform support · c7540644
      Nicolin Chen 提交于
      The next coming i.MX6 Solo X SoC also contains SAI module while we use
      imp_pcm_init() for i.MX platform.
      
      So this patch adds one compatible route for imx6sx and updates the DT
      doc accordingly.
      Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      c7540644
    • N
      ASoC: fsl_sai: Separately enable interrupts for Tx and Rx streams · 8abba5d6
      Nicolin Chen 提交于
      We only enable one side interrupt for each stream since over/underrun
      on the opposite stream would be resulted from what we previously did,
      enabling TERE but remaining FRDE disabled, even though the xrun on the
      opposite direction will not break the current stream.
      Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
      Acked-by: NXiubo Li <Li.Xiubo@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      8abba5d6
    • N
      ASoC: fsl_sai: Fix buggy configurations in trigger() · e6b39846
      Nicolin Chen 提交于
      The current trigger() has two crucial problems:
      1) The DMA request enabling operations (FSL_SAI_CSR_FRDE) for Tx and Rx are
         now totally exclusive: It would fail to run simultaneous Tx-Rx cases.
      2) The TERE disabling operation depends on an incorrect condition -- active
         reference count that only gets increased in snd_pcm_open() and decreased
         in snd_pcm_close(): The TERE would never get cleared.
      
      So this patch overwrites the trigger function by following these rules:
      A) We continue to support tx-async-while-rx-sync-to-tx case alone, which's
         originally limited by this fsl_sai driver, but we make the code easy to
         modify for the further support of the opposite case.
      B) We enable both TE and RE for PLAYBACK stream or CAPTURE stream but only
         enabling the DMA request bit (FSL_SAI_CSR_FRDE) of the current direction
         due to the requirement of SAI -- For tx-async-while-rx-sync-to-tx case,
         the receiver is enabled only when both the transmitter and receiver are
         enabled.
      
      Tested cases:
      a) aplay test.wav -d5
      b) arecord -r44100 -c2 -fS16_LE test.wav -d5
      c) arecord -r44100 -c2 -fS16_LE -d5 | aplay
      d) (aplay test2.wav &); sleep 1; arecord -r44100 -c2 -fS16_LE test.wav -d1
      e) (arecord -r44100 -c2 -fS16_LE test.wav -d5 &); sleep 1; aplay test.wav -d1
      Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
      Acked-by: NXiubo Li <Li.Xiubo@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      e6b39846
    • N
      ASoC: fsl_sai: Improve fsl_sai_isr() · 413312aa
      Nicolin Chen 提交于
      This patch improves fsl_sai_isr() in these ways:
      1, Add comment for mask fetching code.
      2, Return IRQ_NONE if the IRQ is not for the device.
      3, Use regmap_write() instead of regmap_update_bits().
      Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      413312aa
  2. 08 4月, 2014 1 次提交
    • N
      ASoC: fsl_sai: Fix Bit Clock Polarity configurations · ef33bc32
      Nicolin Chen 提交于
      The BCP bit in TCR4/RCR4 register rules as followings:
        0 Bit clock is active high with drive outputs on rising edge
          and sample inputs on falling edge.
        1 Bit clock is active low with drive outputs on falling edge
          and sample inputs on rising edge.
      
      For all formats currently supported in the fsl_sai driver, they're exactly
      sending data on the falling edge and sampling on the rising edge.
      
      However, the driver clears this BCP bit for all of them which results click
      noise when working with SGTL5000 and big noise with WM8962.
      
      Thus this patch corrects the BCP settings for all the formats here to fix
      the nosie issue.
      Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
      Acked-by: NXiubo Li <Li.Xiubo@freescale.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      ef33bc32
  3. 27 3月, 2014 1 次提交
  4. 27 2月, 2014 1 次提交
  5. 26 2月, 2014 1 次提交
  6. 10 2月, 2014 1 次提交
  7. 08 1月, 2014 1 次提交
  8. 31 12月, 2013 2 次提交
  9. 30 12月, 2013 2 次提交
  10. 21 12月, 2013 9 次提交
  11. 19 12月, 2013 1 次提交