This SoC has two PWM channels
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

LPC32xx SoC has a 128 bits unique id that can be used as a system
serial number, if none has been provided by atags or dt.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch adjusts the LPC32xx platform support to the new pl08x DMA interface,
fixing the compile error resulting from changed pl08x structures.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Remove SPI0_CS, MMC_CD and MMC_WP gpios as they moved to devicetree.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

USB and I2C initialization can be removed safely from the board specific
phy3250.c, now that initialization moved to the generalized clock.c.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Tested-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

Move most of usb clock initialization from lpc32xx_udc and ohci-nxp to
clock.c. Also adds ohci clocks and otg clocks.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch fixes a bug, (wrongfully) resetting the value of
LPC32XX_CLKPWR_MS_CTRL back to its initial contents (after careful setup). This
was discovered only with a board/bootloader combination (EA3250) where the
contents of the respective register wasn't already at the correct value on
Linux boot.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch makes sure certain MMC bits are cleared as they should for
initialization.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch moves MMC/SD controller initialization from the board specific file
phy3250.c to clock.c.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

Move i2s1 dma init to be done when it's clock is enabled.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Move the irda configuration to serial.c where other special cases are
handled
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Remove SSP0, CLCD and DMA clocks that are already migrated to
the clock framework.
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Leave chipselect and spi devices binding to the devicetree
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

The lpc32xx spi0 chipselect will be requested directly from the
pl022 driver
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Add the reg, cs-gpios and max-frequencies that are needed for spi
device registry in phy3250.
Adds also the pl022 internal transfers details via dt
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Add ea3250.dtb and phy3250.dtb to the list of dtbs to be built
Signed-off-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patches fixes some status = "disable" strings to "disabled", the correct
way of disabling nodes in the devicetree.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

ARCH_NR_GPIOS was defined statically to include exactly all SoC specific GPIOs.
Now if additional GPIOs need to be added dynamically, e.g. via DT, none are
available. Removing the mach specific setting, leaving ARCH_NR_GPIOS to the
default of 256 (currently in include/asm-generic/gpio.h).
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the
LPC32xx SoC, adjusting the compatible strings, adding interrupts and status
configuration. On the PHY3250 reference board, UART2 is enabled.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch switches from static serial driver initialization to devicetree
configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled
individually via DT.

E.g., instead of Kconfig configuration, the phy3250.dts activates
UARTs 3 and 5.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Tested-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch adjusts the dts files to reference the pl18x primecell driver
correctly.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch adds support for the MMC controller of the LPC32xx SoC to the
platform initialization via the pl08x primecell driver. Lacking more complete
DT support, done via DT auxdata.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This defconfig update for the LPC32xx SoC platform adds the new drivers in v3.5
and drivers typically used in systems with the LPC32xx chip.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

The clock.c file needs to be changed to match the automatic device name to its
clock.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NRob Herring <rob.herring@calxeda.com>

This patch connects the lpc32xx-key driver to the LPC32xx platform (via
lpc32xx.dtsi), and more specifically to the reference board via its dts file.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

There is another reference/development board for the LPC32xx SoC (besides the
Phytec 3250): The Embedded Artists LPC3250 board. This patch adds a default dts
file for it.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Acked-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch takes into account that the MTD NAND MLC controller needs more
registers, located actually before the previously allocated memory range,
already starting at 200a8000 instead of 200b0000.

Further, the interrupt for the controller is configured.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Tested-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch adds DMA channel configuration to the LPC32xx platform file.  The
configured DMA signalling is generic for LPC32xx SoC and is not board specific.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

Since we now support two MTD NAND controllers (MLC and SLC) for LPC32xx via DT,
we don't initialize the SLC controller statically anymore, but do it via the
clock setup (see previous patch).
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Tested-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

This patch adds clock initialization for the MLC NAND controller of the LPC32xx
SoC and adjusts it for the SLC controller.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

This patch adds necessary NAND flash timings to the board specific dts file of
the PHY3250 reference board of the LPC32xx SoC.
Signed-off-by: NRoland Stigge <stigge@antcom.de>
Tested-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com>

If the privileges given to root threads (3% of allowable memory) or a
negative value of /proc/pid/oom_score_adj happen to exceed the amount of
rss of a thread, its badness score overflows as a result of commit
a7f638f9 ("mm, oom: normalize oom scores to oom_score_adj scale only
for userspace").

Fix this by making the type signed and return 1, meaning the thread is
still eligible for kill, if the value is negative.
Reported-by: NDave Jones <davej@redhat.com>
Acked-by: NOleg Nesterov <oleg@redhat.com>
Signed-off-by: NDavid Rientjes <rientjes@google.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Pull scheduler fixes from Ingo Molnar.

* 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  sched: Fix the relax_domain_level boot parameter
  sched: Validate assumptions in sched_init_numa()
  sched: Always initialize cpu-power
  sched: Fix domain iteration
  sched/rt: Fix lockdep annotation within find_lock_lowest_rq()
  sched/numa: Load balance between remote nodes
  sched/x86: Calculate booted cores after construction of sibling_mask

Fix lots of new kernel-doc warnings in kernel/sched/fair.c:

  Warning(kernel/sched/fair.c:3625): No description found for parameter 'env'
  Warning(kernel/sched/fair.c:3625): Excess function parameter 'sd' description in 'update_sg_lb_stats'
  Warning(kernel/sched/fair.c:3735): No description found for parameter 'env'
  Warning(kernel/sched/fair.c:3735): Excess function parameter 'sd' description in 'update_sd_pick_busiest'
  Warning(kernel/sched/fair.c:3735): Excess function parameter 'this_cpu' description in 'update_sd_pick_busiest'
  .. more warnings
Signed-off-by: NRandy Dunlap <rdunlap@xenotime.net>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This reverts commit 9e612a00.

It incorrectly finds VGA connectors where none are attached, apparently
not noticing that nothing replied to the EDID queries, and happily using
the default EDID modes that have nothing to do with actual hardware.

That in turn then causes X to fall down to the lowest common
denominator, which is usually the default 1024x768 mode that is in the
default EDID and pretty much anything supports).

I'd suggest that if not relying on the HDP pin, the code should at least
check whether it gets valid EDID data back, rather than just assume
there's something on the VGA connector.

Cc: Dave Airlie <airlied@linux.ie>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Pull ext4 bug fixes from Theodore Ts'o:
 "This update contains two bug fixes, both destined for the stable tree.
  Perhaps the most important is one which fixes ext4 when used with file
  systems originally formatted for use with ext3, but then later
  converted to take advantage of ext4."

* tag 'ext4_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4:
  ext4: don't set i_flags in EXT4_IOC_SETFLAGS
  ext4: fix the free blocks calculation for ext3 file systems w/ uninit_bg

Pull powerpc fixes from Paul Mackerras:
 "Two small fixes for powerpc:
   - a fix for a regression since 3.2 that causes 4-second (or longer)
     pauses
   - a fix for a potential oops when loading kernel modules on 32-bit
     embedded systems."

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
  powerpc: Fix kernel panic during kernel module load
  powerpc/time: Sanity check of decrementer expiration is necessary

Pull UBI/UBIFS fixes from Artem Bityutskiy:
 "Fix UBI and UBIFS - they refuse to work without debugfs.  This was
  broken by the 3.5-rc1 UBI/UBIFS changes when we removed the debugging
  Kconfig switches.

  Also, correct locking in 'ubi_wl_flush()' - it was extended to support
  flushing a specific LEB in 3.5-rc1, and the locking was sub-optimal."

* tag 'upstream-3.5-rc2' of git://git.infradead.org/linux-ubifs:
  UBI: correct ubi_wl_flush locking
  UBIFS: fix debugfs-less systems support
  UBI: fix debugfs-less systems support