1. 22 9月, 2015 1 次提交
  2. 23 7月, 2015 2 次提交
  3. 31 5月, 2015 1 次提交
  4. 24 3月, 2015 1 次提交
    • L
      usb: xhci: apply XHCI_AVOID_BEI quirk to all Intel xHCI controllers · 227a4fd8
      Lu Baolu 提交于
      When a device with an isochronous endpoint is plugged into the Intel
      xHCI host controller, and the driver submits multiple frames per URB,
      the xHCI driver will set the Block Event Interrupt (BEI) flag on all
      but the last TD for the URB. This causes the host controller to place
      an event on the event ring, but not send an interrupt. When the last
      TD for the URB completes, BEI is cleared, and we get an interrupt for
      the whole URB.
      
      However, under Intel xHCI host controllers, if the event ring is full
      of events from transfers with BEI set,  an "Event Ring is Full" event
      will be posted to the last entry of the event ring,  but no interrupt
      is generated. Host will cease all transfer and command executions and
      wait until software completes handling the pending events in the event
      ring.  That means xHC stops, but event of "event ring is full" is not
      notified. As the result, the xHC looks like dead to user.
      
      This patch is to apply XHCI_AVOID_BEI quirk to Intel xHC devices. And
      it should be backported to kernels as old as 3.0, that contains the
      commit 69e848c2 ("Intel xhci: Support EHCI/xHCI port switching.").
      Signed-off-by: NLu Baolu <baolu.lu@linux.intel.com>
      Tested-by: NAlistair Grant <akgrant0710@gmail.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      227a4fd8
  5. 07 3月, 2015 1 次提交
  6. 10 1月, 2015 1 次提交
    • H
      xhci: Add broken-streams quirk for Fresco Logic FL1000G xhci controllers · 7f5c4d63
      Hans de Goede 提交于
      Streams do not work reliabe on Fresco Logic FL1000G xhci controllers,
      trying to use them results in errors like this:
      
      21:37:33 kernel: xhci_hcd 0000:04:00.0: ERROR Transfer event for disabled endpoint or incorrect stream ring
      21:37:33 kernel: xhci_hcd 0000:04:00.0: @00000000368b3570 9067b000 00000000 05000000 01078001
      21:37:33 kernel: xhci_hcd 0000:04:00.0: ERROR Transfer event for disabled endpoint or incorrect stream ring
      21:37:33 kernel: xhci_hcd 0000:04:00.0: @00000000368b3580 9067b400 00000000 05000000 01038001
      
      As always I've ordered a pci-e addon card with a Fresco Logic controller for
      myself to see if I can come up with a better fix then the big hammer, in
      the mean time this will make uas devices work again (in usb-storage mode)
      for FL1000G users.
      Reported-by: NMarcin Zajączkowski <mszpak@wp.pl>
      Cc: stable@vger.kernel.org # 3.15
      Signed-off-by: NHans de Goede <hdegoede@redhat.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      7f5c4d63
  7. 22 11月, 2014 1 次提交
  8. 04 11月, 2014 2 次提交
  9. 04 10月, 2014 3 次提交
  10. 28 8月, 2014 1 次提交
  11. 20 8月, 2014 1 次提交
    • H
      usb: xhci: amd chipset also needs short TX quirk · 2597fe99
      Huang Rui 提交于
      AMD xHC also needs short tx quirk after tested on most of chipset
      generations. That's because there is the same incorrect behavior like
      Fresco Logic host. Please see below message with on USB webcam
      attached on xHC host:
      
      [  139.262944] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.266934] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.270913] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.274937] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.278914] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.282936] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.286915] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.290938] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.294913] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      [  139.298917] xhci_hcd 0000:00:10.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      Reported-by: NArindam Nath <arindam.nath@amd.com>
      Tested-by: NShriraj-Rai P <shriraj-rai.p@amd.com>
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NHuang Rui <ray.huang@amd.com>
      Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      2597fe99
  12. 02 8月, 2014 2 次提交
    • H
      xhci: Rename Asrock P67 pci product-id to EJ168 · 170625e9
      Hans de Goede 提交于
      The 7023 product id is the generic product id for the Etron EJ168, it is
      not specific to the version found on the Asrock P67 motherboard. The same id
      is e.g. also used on Gigabyte motherboards and on no-name pci-e usb-3 addon
      cards.
      Signed-off-by: NHans de Goede <hdegoede@redhat.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      170625e9
    • H
      xhci: Blacklist using streams on the Etron EJ168 controller · 8f873c1f
      Hans de Goede 提交于
      Streams on the EJ168 do not work as they should. I've spend 2 days trying
      to get them to work, but without success.
      
      The first problem is that when ever you ring the stream-ring doorbell, the
      controller starts executing trbs at the beginning of the first ring segment,
      event if it ended somewhere else previously. This can be worked around by
      allowing enqueing only one td (not a problem with how streams are typically
      used) and then resetting our copies of the enqueueing en dequeueing pointers
      on a td completion to match what the controller seems to be doing.
      
      This way things seem to start working with uas and instead of being able
      to complete only the very first scsi command, the scsi core can probe the disk.
      
      But then things break later on when td-s get enqueued with more then one
      trb. The controller does seem to increase its dequeue pointer while executing
      a stream-ring (data transfer events I inserted for debugging do trigger).
      However execution seems to stop at the final normal trb of a multi trb td,
      even if there is a data transfer event inserted after the final trb.
      
      The first problem alone is a serious deviation from the spec, and esp.
      dealing with cancellation would have been very tricky if not outright
      impossible, but the second problem simply is a deal breaker altogether,
      so this patch simply disables streams.
      
      Note this will cause the usb-storage + uas driver pair to automatically switch
      to using usb-storage instead of uas on these devices, essentially reverting
      to the 3.14 and earlier behavior when uas was marked CONFIG_BROKEN.
      
      https://bugzilla.redhat.com/show_bug.cgi?id=1121288
      https://bugzilla.kernel.org/show_bug.cgi?id=80101
      
      Cc: stable@vger.kernel.org # 3.15
      Signed-off-by: NHans de Goede <hdegoede@redhat.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      8f873c1f
  13. 28 5月, 2014 2 次提交
  14. 26 4月, 2014 2 次提交
  15. 07 3月, 2014 1 次提交
  16. 05 3月, 2014 2 次提交
    • O
      storage: accept some UAS devices if streams are unavailable · 14aec589
      Oliver Neukum 提交于
      On some older XHCIs streams are not supported and the UAS driver
      will fail at probe time. For those devices storage should try
      to bind to UAS devices.
      This patch adds a flag for stream support to HCDs and evaluates
      it.
      
      [Note: Sarah fixed a bug where the USB 2.0 root hub, not USB 3.0 root
      hub would get marked as being able to support streams.]
      Signed-off-by: NOliver Neukum <oliver@neukum.org>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Acked-by: NHans de Goede <hdegoede@redhat.com>
      14aec589
    • S
      usb/xhci: Change how we indicate a host supports Link PM. · 25cd2882
      Sarah Sharp 提交于
      The xHCI driver currently uses a USB core internal field,
      udev->lpm_capable, to indicate the xHCI driver knows how to calculate
      the LPM timeout values.  If this value is set for the host controller
      udev, it means Link PM can be enabled for child devices under that host.
      
      Change the code so the xHCI driver isn't mucking with USB core internal
      fields.  Instead, indicate the xHCI driver doesn't support Link PM on
      this host by clearing the U1 and U2 exit latencies in the roothub
      SuperSpeed Extended Capabilities BOS descriptor.
      
      The code to check for the roothub setting U1 and U2 exit latencies to
      zero will also disable LPM for external devices that do that same.  This
      was already effectively done with commit
      ae8963ad "usb: Don't enable LPM if the
      exit latency is zero."  Leave that code in place, so that if a device
      sets one exit latency value to zero, but the other is set to a valid
      value, LPM is only enabled for the U1 or U2 state that had the valid
      value.  This is the same behavior the code had before.
      
      Also, change messages about missing Link PM information from warning
      level to info level.  Only print a warning about the first device that
      doesn't support LPM, to avoid log spam.  Further, cleanup some
      unnecessary line breaks to help people to grep for the error messages.
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Cc: Alan Stern <stern@rowland.harvard.edu>
      25cd2882
  17. 23 1月, 2014 1 次提交
  18. 11 12月, 2013 2 次提交
    • D
      usb: xhci: change enumeration scheme to 'new scheme' by default · 48fc7dbd
      Dan Williams 提交于
      Change the default enumeration scheme for xhci attached non-SuperSpeed
      devices from:
      
         Reset
         SetAddress [xhci address-device BSR = 0]
         GetDescriptor(8)
         GetDescriptor(18)
      
      ...to:
      
         Reset
         [xhci address-device BSR = 1]
         GetDescriptor(64)
         Reset
         SetAddress [xhci address-device BSR = 0]
         GetDescriptor(18)
      
      ...as some devices misbehave when encountering a SetAddress command
      prior to GetDescriptor.  There are known legacy devices that require
      this scheme, but testing has found at least one USB3 device that fails
      enumeration when presented with this ordering.  For now, follow the ehci
      case and enable 'new scheme' by default for non-SuperSpeed devices.
      
      To support this enumeration scheme on xhci the AddressDevice operation
      needs to be performed twice.  The first instance of the command enables
      the HC's device and slot context info for the device, but omits sending
      the device a SetAddress command (BSR == block set address request).
      Then, after GetDescriptor completes, follow up with the full
      AddressDevice+SetAddress operation.
      
      As mentioned before, this ordering of events with USB3 devices causes an
      extra state transition to be exposed to xhci.  Previously USB3 devices
      would transition directly from 'enabled' to 'addressed' and never need
      to underrun responses to 'get descriptor'. We do see the 64-byte
      descriptor fetch the correct data, but the following 18-byte descriptor
      read after the reset gets:
      
      bLength            = 0
      bDescriptorType    = 0
      bcdUSB             = 0
      bDeviceClass       = 0
      bDeviceSubClass    = 0
      bDeviceProtocol    = 0
      bMaxPacketSize0    = 9
      
      instead of:
      
      bLength            = 12
      bDescriptorType    = 1
      bcdUSB             = 300
      bDeviceClass       = 0
      bDeviceSubClass    = 0
      bDeviceProtocol    = 0
      bMaxPacketSize0    = 9
      
      which results in the discovery process looping until falling back to
      'old scheme' enumeration.
      Acked-by: NAlan Stern <stern@rowland.harvard.edu>
      Reported-by: NDavid Moore <david.moore@gmail.com>
      Suggested-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      48fc7dbd
    • T
      xhci: Limit the spurious wakeup fix only to HP machines · 6962d914
      Takashi Iwai 提交于
      We've got regression reports that my previous fix for spurious wakeups
      after S5 on HP Haswell machines leads to the automatic reboot at
      shutdown on some machines.  It turned out that the fix for one side
      triggers another BIOS bug in other side.  So, it's exclusive.
      
      Since the original S5 wakeups have been confirmed only on HP machines,
      it'd be safer to apply it only to limited machines.  As a wild guess,
      limiting to machines with HP PCI SSID should suffice.
      
      This patch should be backported to kernels as old as 3.12, that
      contain the commit 638298dc "xhci: Fix
      spurious wakeups after S5 on Haswell".
      
      Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=66171
      Cc: stable@vger.kernel.org
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Tested-by: <dashing.meng@gmail.com>
      Reported-by: NNiklas Schnelle <niklas@komani.de>
      Reported-by: NGiorgos <ganastasiouGR@gmail.com>
      Reported-by: <art1@vhex.net>
      6962d914
  19. 10 10月, 2013 2 次提交
    • T
      xhci: Fix spurious wakeups after S5 on Haswell · 638298dc
      Takashi Iwai 提交于
      Haswell LynxPoint and LynxPoint-LP with the recent Intel BIOS show
      mysterious wakeups after shutdown occasionally.  After discussing with
      BIOS engineers, they explained that the new BIOS expects that the
      wakeup sources are cleared and set to D3 for all wakeup devices when
      the system is going to sleep or power off, but the current xhci driver
      doesn't do this properly (partly intentionally).
      
      This patch introduces a new quirk, XHCI_SPURIOUS_WAKEUP, for
      fixing the spurious wakeups at S5 by calling xhci_reset() in the xhci
      shutdown ops as done in xhci_stop(), and setting the device to PCI D3
      at shutdown and remove ops.
      
      The PCI D3 call is based on the initial fix patch by Oliver Neukum.
      
      [Note: Sarah changed the quirk name from XHCI_HSW_SPURIOUS_WAKEUP to
      XHCI_SPURIOUS_WAKEUP, since none of the other quirks have system names
      in them.  Sarah also fixed a collision with a quirk submitted around the
      same time, by changing the xhci->quirks bit from 17 to 18.]
      
      This patch should be backported to kernels as old as 3.0, that
      contain the commit 1c12443a "xhci: Add
      Lynx Point to list of Intel switchable hosts."
      
      Cc: Oliver Neukum <oneukum@suse.de>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Cc: stable@vger.kernel.org
      638298dc
    • O
      xhci: quirk for extra long delay for S4 · 455f5892
      Oliver Neukum 提交于
      It has been reported that this chipset really cannot
      sleep without this extraordinary delay.
      
      This patch should be backported, in order to ensure this host functions
      under stable kernels.  The last quirk for Fresco Logic hosts (commit
      bba18e33 "xhci: Extend Fresco Logic MSI
      quirk.") was backported to stable kernels as old as 2.6.36.
      Signed-off-by: NOliver Neukum <oneukum@suse.de>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Cc: stable@vger.kernel.org
      455f5892
  20. 26 9月, 2013 1 次提交
  21. 14 8月, 2013 1 次提交
  22. 25 7月, 2013 1 次提交
    • G
      usb: host: xhci: Enable XHCI_SPURIOUS_SUCCESS for all controllers with xhci 1.0 · 07f3cb7c
      George Cherian 提交于
      Xhci controllers with hci_version > 0.96 gives spurious success
      events on short packet completion. During webcam capture the
      "ERROR Transfer event TRB DMA ptr not part of current TD" was observed.
      The same application works fine with synopsis controllers hci_version 0.96.
      The same issue is seen with Intel Pantherpoint xhci controller. So enabling
      this quirk in xhci_gen_setup if controller verion is greater than 0.96.
      For xhci-pci move the quirk to much generic place xhci_gen_setup.
      
      Note from Sarah:
      
      The xHCI 1.0 spec changed how hardware handles short packets.  The HW
      will notify SW of the TRB where the short packet occurred, and it will
      also give a successful status for the last TRB in a TD (the one with the
      IOC flag set).  On the second successful status, that warning will be
      triggered in the driver.
      
      Software is now supposed to not assume the TD is not completed until it
      gets that last successful status.  That means we have a slight race
      condition, although it should have little practical impact.  This patch
      papers over that issue.
      
      It's on my long-term to-do list to fix this race condition, but it is a
      much more involved patch that will probably be too big for stable.  This
      patch is needed for stable to avoid serious log spam.
      
      This patch should be backported to kernels as old as 3.0, that
      contain the commit ad808333 "Intel xhci:
      Ignore spurious successful event."
      
      The patch will have to be modified for kernels older than 3.2, since
      that kernel added the xhci_gen_setup function for xhci platform devices.
      The correct conflict resolution for kernels older than 3.2 is to set
      XHCI_SPURIOUS_SUCCESS in xhci_pci_quirks for all xHCI 1.0 hosts.
      Signed-off-by: NGeorge Cherian <george.cherian@ti.com>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Cc: stable@vger.kernel.org
      07f3cb7c
  23. 24 7月, 2013 1 次提交
    • M
      Intel xhci: refactor EHCI/xHCI port switching · 26b76798
      Mathias Nyman 提交于
      Make the Linux xHCI driver automatically try to switchover the EHCI ports to
      xHCI when an Intel xHCI host is detected, and it also finds an Intel EHCI host.
      
      This means we will no longer have to add Intel xHCI hosts to a quirks list when
      the PCI device IDs change.  Simply continuing to add new Intel xHCI PCI device
      IDs to the quirks list is not sustainable.
      
      During suspend ports may be swicthed back to EHCI by BIOS and not properly
      restored to xHCI at resume. Previously both EHCI and xHCI resume functions
      switched ports back to XHCI, but it's enough to do it in xHCI only
      because the hub driver doesn't start running again until after both hosts are resumed.
      Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      26b76798
  24. 25 5月, 2013 1 次提交
    • S
      xhci: Disable D3cold for buggy TI redrivers. · c3897aa5
      Sarah Sharp 提交于
      Some xHCI hosts contain a "redriver" from TI that silently drops port
      status connect changes if the port slips into Compliance Mode.  If the
      port slips into compliance mode while the host is in D0, there will not
      be a port status change event.  If the port slips into compliance mode
      while the host is in D3, the host will not send a PME.  This includes
      when the system is suspended (S3) or hibernated (S4).
      
      If this happens when the system is in S3/S4, there is nothing software
      can do.  Other port status change events that would normally cause the
      host to wake the system from S3/S4 may also be lost.  This includes
      remote wakeup, disconnects and connects on other ports, and overrcurrent
      events.  A decision was made to _NOT_ disable system suspend/hibernate
      on these systems, since users are unlikely to enable wakeup from S3/S4
      for the xHCI host.
      
      Software can deal with this issue when the system is in S0.  A work
      around was put in to poll the port status registers for Compliance Mode.
      The xHCI driver will continue to poll the registers while the host is
      runtime suspended.  Unfortunately, that means we can't allow the PCI
      device to go into D3cold, because power will be removed from the host,
      and the config space will read as all Fs.
      
      Disable D3cold in the xHCI PCI runtime suspend function.
      
      This patch should be backported to kernels as old as 3.2, that
      contain the commit 71c731a2 "usb: host:
      xhci: Fix Compliance Mode on SN65LVPE502CP Hardware"
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Cc: Huang Ying <ying.huang@intel.com>
      Cc: stable@vger.kernel.org
      c3897aa5
  25. 26 3月, 2013 1 次提交
    • L
      usb: add find_raw_port_number callback to struct hc_driver() · 3f5eb141
      Lan Tianyu 提交于
      xhci driver divides the root hub into two logical hubs which work
      respectively for usb 2.0 and usb 3.0 devices. They are independent
      devices in the usb core. But in the ACPI table, it's one device node
      and all usb2.0 and usb3.0 ports are under it. Binding usb port with
      its acpi node needs the raw port number which is reflected in the xhci
      extended capabilities table. This patch is to add find_raw_port_number
      callback to struct hc_driver(), fill it with xhci_find_raw_port_number()
      which will return raw port number and add a wrap usb_hcd_find_raw_port_number().
      
      Otherwise, refactor xhci_find_real_port_number(). Using
      xhci_find_raw_port_number() to get real index in the HW port status
      registers instead of scanning through the xHCI roothub port array.
      This can help to speed up.
      
      All addresses in xhci->usb2_ports and xhci->usb3_ports array are
      kown good ports and don't include following bad ports in the extended
      capabilities talbe.
           (1) root port that doesn't have an entry
           (2) root port with unknown speed
           (3) root port that is listed twice and with different speeds.
      
      So xhci_find_raw_port_number() will only return port num of good ones
      and never touch bad ports above.
      Signed-off-by: NLan Tianyu <tianyu.lan@intel.com>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      3f5eb141
  26. 13 11月, 2012 2 次提交
    • F
      usb: host: xhci: move HC_STATE_SUSPENDED check to xhci_suspend() · 77b84767
      Felipe Balbi 提交于
      that check will have to be done by all users
      of xhci_suspend() so it sounds a lot better to
      move the check to xhci_suspend() in order to
      avoid code duplication.
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      77b84767
    • S
      xhci: Extend Fresco Logic MSI quirk. · bba18e33
      Sarah Sharp 提交于
      Ali reports that plugging a device into the Fresco Logic xHCI host with
      PCI device ID 1400 produces an IRQ error:
      
       do_IRQ: 3.176 No irq handler for vector (irq -1)
      
      Other early Fresco Logic host revisions don't support MSI, even though
      their PCI config space claims they do.  Extend the quirk to disabling
      MSI to this chipset revision.  Also enable the short transfer quirk,
      since it's likely this revision also has that quirk, and it should be
      harmless to enable.
      
      04:00.0 0c03: 1b73:1400 (rev 01) (prog-if 30 [XHCI])
              Subsystem: 1d5c:1000
              Physical Slot: 3
              Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
              Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
              Latency: 0, Cache Line Size: 64 bytes
              Interrupt: pin A routed to IRQ 51
              Region 0: Memory at d4600000 (32-bit, non-prefetchable) [size=64K]
              Capabilities: [50] Power Management version 3
                      Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-)
                      Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
              Capabilities: [68] MSI: Enable+ Count=1/1 Maskable- 64bit+
                      Address: 00000000feeff00c  Data: 41b1
              Capabilities: [80] Express (v1) Endpoint, MSI 00
                      DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <2us, L1 <32us
                              ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
                      DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                              RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                              MaxPayload 128 bytes, MaxReadReq 512 bytes
                      DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                      LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 unlimited
                              ClockPM- Surprise- LLActRep- BwNot-
                      LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
                              ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                      LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
              Kernel driver in use: xhci_hcd
      
      This patch should be backported to stable kernels as old as 2.6.36, that
      contain the commit f5182b41 "xhci:
      Disable MSI for some Fresco Logic hosts."
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Reported-by: NA Sh <smr.ash1991@gmail.com>
      Tested-by: NA Sh <smr.ash1991@gmail.com>
      Cc: stable@vger.kernel.org
      bba18e33
  27. 26 9月, 2012 1 次提交
    • S
      xhci: Intel Panther Point BEI quirk. · 80fab3b2
      Sarah Sharp 提交于
      When a device with an isochronous endpoint is behind a hub plugged into
      the Intel Panther Point xHCI host controller, and the driver submits
      multiple frames per URB, the xHCI driver will set the Block Event
      Interrupt (BEI) flag on all but the last TD for the URB.  This causes
      the host controller to place an event on the event ring, but not send an
      interrupt.  When the last TD for the URB completes, BEI is cleared, and
      we get an interrupt for the whole URB.
      
      However, under a Panther Point xHCI host controller, if the parent hub
      is unplugged when one or more events from transfers with BEI set are on
      the event ring, a port status change event is placed on the event ring,
      but no interrupt is generated.  This means URBs stop completing, and the
      USB device disconnect is not noticed.  Something like a USB headset will
      cause mplayer to hang when the device is disconnected.
      
      If another transfer is sent (such as running `sudo lsusb -v`), the next
      transfer event seems to "unstick" the event ring, the xHCI driver gets
      an interrupt, and the disconnect is reported to the USB core.
      
      The fix is not to use the BEI flag under the Panther Point xHCI host.
      This will impact power consumption and system responsiveness, because
      the xHCI driver will receive an interrupt for every frame in all
      isochronous URBs instead of once per URB.
      
      Intel chipset developers confirm that this bug will be hit if the BEI
      flag is used on any endpoint, not just ones that are behind a hub.
      
      This patch should be backported to kernels as old as 3.0, that contain
      the commit 69e848c2 "Intel xhci: Support
      EHCI/xHCI port switching."
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Cc: stable@vger.kernel.org
      80fab3b2
  28. 10 8月, 2012 1 次提交
    • S
      xhci: Switch PPT ports to EHCI on shutdown. · e95829f4
      Sarah Sharp 提交于
      The Intel desktop boards DH77EB and DH77DF have a hardware issue that
      can be worked around by BIOS.  If the USB ports are switched to xHCI on
      shutdown, the xHCI host will send a spurious interrupt, which will wake
      the system.  Some BIOS will work around this, but not all.
      
      The bug can be avoided if the USB ports are switched back to EHCI on
      shutdown.  The Intel Windows driver switches the ports back to EHCI, so
      change the Linux xHCI driver to do the same.
      
      Unfortunately, we can't tell the two effected boards apart from other
      working motherboards, because the vendors will change the DMI strings
      for the DH77EB and DH77DF boards to their own custom names.  One example
      is Compulab's mini-desktop, the Intense-PC.  Instead, key off the
      Panther Point xHCI host PCI vendor and device ID, and switch the ports
      over for all PPT xHCI hosts.
      
      The only impact this will have on non-effected boards is to add a couple
      hundred milliseconds delay on boot when the BIOS has to switch the ports
      over from EHCI to xHCI.
      
      This patch should be backported to kernels as old as 3.0, that contain
      the commit 69e848c2 "Intel xhci: Support
      EHCI/xHCI port switching."
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Reported-by: NDenis Turischev <denis@compulab.co.il>
      Tested-by: NDenis Turischev <denis@compulab.co.il>
      Cc: stable@vger.kernel.org
      e95829f4
  29. 08 8月, 2012 1 次提交
    • S
      xhci: Add Etron XHCI_TRUST_TX_LENGTH quirk. · 5cb7df2b
      Sarah Sharp 提交于
      Gary reports that with recent kernels, he notices more xHCI driver
      warnings:
      
      xhci_hcd 0000:03:00.0: WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?
      
      We think his Etron xHCI host controller may have the same buggy behavior
      as the Fresco Logic xHCI host.  When a short transfer is received, the
      host will mark the transfer as successfully completed when it should be
      marking it with a short completion.
      
      Fix this by turning on the XHCI_TRUST_TX_LENGTH quirk when the Etron
      host is discovered.  Note that Gary has revision 1, but if Etron fixes
      this bug in future revisions, the quirk will have no effect.
      
      This patch should be backported to kernels as old as 2.6.36, that
      contain a backported version of commit
      1530bbc6 "xhci: Add new short TX quirk
      for Fresco Logic host."
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Reported-by: NGary E. Miller <gem@rellim.com>
      Cc: stable@vger.kernel.org
      5cb7df2b