1. 08 2月, 2009 3 次提交
  2. 02 2月, 2009 3 次提交
  3. 31 1月, 2009 4 次提交
  4. 30 1月, 2009 8 次提交
  5. 29 1月, 2009 4 次提交
    • L
      Linux 2.6.29-rc3 · 18e352e4
      Linus Torvalds 提交于
      18e352e4
    • L
      Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc · c4568d6c
      Linus Torvalds 提交于
      * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
        powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup code
        powerpc/pseries: Correct VIO bus accounting problem in CMO env.
        powerpc: More printing warning fixes for the l64 to ll64 conversion
        powerpc: Remove arch/ppc cruft from Kconfig
        powerpc: Printing fix for l64 to ll64 conversion: phyp_dump.c
        powerpc/embedded6xx: Update defconfigs
        powerpc/8xx: Update defconfigs
        powerpc/86xx: Update defconfigs
        powerpc/83xx: Update defconfigs
        powerpc/85xx: Update defconfigs
        powerpc/mpc8313erdb: fix kernel panic because mdio device is not probed
        powerpc/4xx: Update multi-board PowerPC 4xx defconfigs
        powerpc/44x: Update PowerPC 44x defconfigs
        powerpc/40x: Update PowerPC 40x defconfigs
        powerpc/85xx: Fix typo in mpc8572ds dts
        powerpc/44x: Warp patches for the new NDFC driver
        powerpc/4xx: DTS: Add Add'l SDRAM0 Compatible and Interrupt Info
      c4568d6c
    • N
      [ARM] 5366/1: fix shared memory coherency with VIVT L1 + L2 caches · 08e445bd
      Nicolas Pitre 提交于
      When there are multiple L1-aliasing userland mappings of the same physical
      page, we currently remap each of them uncached, to prevent VIVT cache
      aliasing issues. (E.g. writes to one of the mappings not being immediately
      visible via another mapping.)  However, when we do this remapping, there
      could still be stale data in the L2 cache, and an uncached mapping might
      bypass L2 and go straight to RAM.  This would cause reads from such
      mappings to see old data (until the dirty L2 line is eventually evicted.)
      
      This issue is solved by forcing a L2 cache flush whenever the shared page
      is made L1 uncacheable.
      
      Ideally, we would make L1 uncacheable and L2 cacheable as L2 is PIPT. But
      Feroceon does not support that combination, and the TEX=5 C=0 B=0 encoding
      for XSc3 doesn't appear to work in practice.
      Signed-off-by: NNicolas Pitre <nico@marvell.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      08e445bd
    • L
      Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu · 78a768b6
      Linus Torvalds 提交于
      * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
        m68knommu: fix 5329 ColdFire periphal addressing
        uclinux: add process name to allocation error message
        m68knommu: correct the mii calculations for 532x ColdFire FEC
        m68knommu: add ColdFire M532x to the FEC configuration options
        m68knommu: fix syscall restarting
        m68knommu: remove the obsolete and long unused comempci chip support
        m68knommu: remove the no longer used PCI support option
        m68knommu: remove obsolete and unused eLIA board
        m68knommu: set NO_DMA
        m68knommu: fix cache flushing for the 527x ColdFire processors
        m68knommu: fix ColdFire 5272 serial baud rates in mcf.c
        m68knommu: use one exist from execption
      78a768b6
  6. 28 1月, 2009 18 次提交