1. 07 2月, 2008 1 次提交
    • E
      get rid of NR_OPEN and introduce a sysctl_nr_open · 9cfe015a
      Eric Dumazet 提交于
      NR_OPEN (historically set to 1024*1024) actually forbids processes to open
      more than 1024*1024 handles.
      
      Unfortunatly some production servers hit the not so 'ridiculously high
      value' of 1024*1024 file descriptors per process.
      
      Changing NR_OPEN is not considered safe because of vmalloc space potential
      exhaust.
      
      This patch introduces a new sysctl (/proc/sys/fs/nr_open) wich defaults to
      1024*1024, so that admins can decide to change this limit if their workload
      needs it.
      
      [akpm@linux-foundation.org: export it for sparc64]
      Signed-off-by: NEric Dumazet <dada1@cosmosbay.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Cc: Richard Henderson <rth@twiddle.net>
      Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      9cfe015a
  2. 01 11月, 2007 1 次提交
  3. 09 8月, 2007 1 次提交
  4. 22 7月, 2007 1 次提交
  5. 21 7月, 2007 1 次提交
    • D
      [SPARC]: Fix serial console device detection. · c73fcc84
      David S. Miller 提交于
      The current scheme works on static interpretation of text names, which
      is wrong.
      
      The output-device setting, for example, must be resolved via an alias
      or similar to a full path name to the console device.
      
      Paths also contain an optional set of 'options', which starts with a
      colon at the end of the path.  The option area is used to specify
      which of two serial ports ('a' or 'b') the path refers to when a
      device node drives multiple ports.  'a' is assumed if the option
      specification is missing.
      
      This was caught by the UltraSPARC-T1 simulator.  The 'output-device'
      property was set to 'ttya' and we didn't pick upon the fact that this
      is an OBP alias set to '/virtual-devices/console'.  Instead we saw it
      as the first serial console device, instead of the hypervisor console.
      
      The infrastructure is now there to take advantage of this to resolve
      the console correctly even in multi-head situations in fbcon too.
      
      Thanks to Greg Onufer for the bug report.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c73fcc84
  6. 16 7月, 2007 2 次提交
    • D
      [SPARC64]: More sensible udelay implementation. · 8b99cfb8
      David S. Miller 提交于
      Take a page from the powerpc folks and just calculate the
      delay factor directly.
      
      Since frequency scaling chips use a system-tick register,
      the value is going to be the same system-wide.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8b99cfb8
    • D
      [SPARC64]: Initial LDOM cpu hotplug support. · 4f0234f4
      David S. Miller 提交于
      Only adding cpus is supports at the moment, removal
      will come next.
      
      When new cpus are configured, the machine description is
      updated.  When we get the configure request we pass in a
      cpu mask of to-be-added cpus to the mdesc CPU node parser
      so it only fetches information for those cpus.  That code
      also proceeds to update the SMT/multi-core scheduling bitmaps.
      
      cpu_up() does all the work and we return the status back
      over the DS channel.
      
      CPUs via dr-cpu need to be booted straight out of the
      hypervisor, and this requires:
      
      1) A new trampoline mechanism.  CPUs are booted straight
         out of the hypervisor with MMU disabled and running in
         physical addresses with no mappings installed in the TLB.
      
         The new hvtramp.S code sets up the critical cpu state,
         installs the locked TLB mappings for the kernel, and
         turns the MMU on.  It then proceeds to follow the logic
         of the existing trampoline.S SMP cpu bringup code.
      
      2) All calls into OBP have to be disallowed when domaining
         is enabled.  Since cpus boot straight into the kernel from
         the hypervisor, OBP has no state about that cpu and therefore
         cannot handle being invoked on that cpu.
      
         Luckily it's only a handful of interfaces which can be called
         after the OBP device tree is obtained.  For example, rebooting,
         halting, powering-off, and setting options node variables.
      
      CPU removal support will require some infrastructure changes
      here.  Namely we'll have to process the requests via a true
      kernel thread instead of in a workqueue.  workqueues run on
      a per-cpu thread, but when unconfiguring we might need to
      force the thread to execute on another cpu if the current cpu
      is the one being removed.  Removal of a cpu also causes the kernel
      to destroy that cpu's workqueue running thread.
      
      Another issue on removal is that we may have interrupts still
      pointing to the cpu-to-be-removed.  So new code will be needed
      to walk the active INO list and retarget those cpus as-needed.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4f0234f4
  7. 08 6月, 2007 1 次提交
  8. 26 4月, 2007 1 次提交
  9. 13 2月, 2007 2 次提交
  10. 22 7月, 2006 1 次提交
  11. 06 7月, 2006 1 次提交
  12. 01 7月, 2006 1 次提交
  13. 20 6月, 2006 2 次提交
    • D
      [SPARC64]: Don't double-export synchronize_irq. · c8bfcd95
      David S. Miller 提交于
      It is done by the generic IRQ layer now.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c8bfcd95
    • D
      [SPARC64]: Move over to GENERIC_HARDIRQS. · e18e2a00
      David S. Miller 提交于
      This is the long overdue conversion of sparc64 over to
      the generic IRQ layer.
      
      The kernel image is slightly larger, but the BSS is ~60K
      smaller due to the reduced size of struct ino_bucket.
      
      A lot of IRQ implementation details, including ino_bucket,
      were moved out of asm-sparc64/irq.h and are now private to
      arch/sparc64/kernel/irq.c, and most of the code in irq.c
      totally disappeared.
      
      One thing that's different at the moment is IRQ distribution,
      we do it at enable_irq() time.  If the cpu mask is ALL then
      we round-robin using a global rotating cpu counter, else
      we pick the first cpu in the mask to support single cpu
      targetting.  This is similar to what powerpc's XICS IRQ
      support code does.
      
      This works fine on my UP SB1000, and the SMP build goes
      fine and runs on that machine, but lots of testing on
      different setups is needed.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e18e2a00
  14. 12 6月, 2006 1 次提交
  15. 11 4月, 2006 1 次提交
  16. 27 3月, 2006 2 次提交
  17. 20 3月, 2006 4 次提交
  18. 19 1月, 2006 1 次提交
  19. 11 1月, 2006 1 次提交
  20. 15 9月, 2005 1 次提交
    • D
      [LIB]: Consolidate _atomic_dec_and_lock() · 4db2ce01
      David S. Miller 提交于
      Several implementations were essentialy a common piece of C code using
      the cmpxchg() macro.  Put the implementation in one spot that everyone
      can share, and convert sparc64 over to using this.
      
      Alpha is the lone arch-specific implementation, which codes up a
      special fast path for the common case in order to avoid GP reloading
      which a pure C version would require.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4db2ce01
  21. 11 9月, 2005 1 次提交
    • I
      [PATCH] spinlock consolidation · fb1c8f93
      Ingo Molnar 提交于
      This patch (written by me and also containing many suggestions of Arjan van
      de Ven) does a major cleanup of the spinlock code.  It does the following
      things:
      
       - consolidates and enhances the spinlock/rwlock debugging code
      
       - simplifies the asm/spinlock.h files
      
       - encapsulates the raw spinlock type and moves generic spinlock
         features (such as ->break_lock) into the generic code.
      
       - cleans up the spinlock code hierarchy to get rid of the spaghetti.
      
      Most notably there's now only a single variant of the debugging code,
      located in lib/spinlock_debug.c.  (previously we had one SMP debugging
      variant per architecture, plus a separate generic one for UP builds)
      
      Also, i've enhanced the rwlock debugging facility, it will now track
      write-owners.  There is new spinlock-owner/CPU-tracking on SMP builds too.
      All locks have lockup detection now, which will work for both soft and hard
      spin/rwlock lockups.
      
      The arch-level include files now only contain the minimally necessary
      subset of the spinlock code - all the rest that can be generalized now
      lives in the generic headers:
      
       include/asm-i386/spinlock_types.h       |   16
       include/asm-x86_64/spinlock_types.h     |   16
      
      I have also split up the various spinlock variants into separate files,
      making it easier to see which does what. The new layout is:
      
         SMP                         |  UP
         ----------------------------|-----------------------------------
         asm/spinlock_types_smp.h    |  linux/spinlock_types_up.h
         linux/spinlock_types.h      |  linux/spinlock_types.h
         asm/spinlock_smp.h          |  linux/spinlock_up.h
         linux/spinlock_api_smp.h    |  linux/spinlock_api_up.h
         linux/spinlock.h            |  linux/spinlock.h
      
      /*
       * here's the role of the various spinlock/rwlock related include files:
       *
       * on SMP builds:
       *
       *  asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
       *                        initializers
       *
       *  linux/spinlock_types.h:
       *                        defines the generic type and initializers
       *
       *  asm/spinlock.h:       contains the __raw_spin_*()/etc. lowlevel
       *                        implementations, mostly inline assembly code
       *
       *   (also included on UP-debug builds:)
       *
       *  linux/spinlock_api_smp.h:
       *                        contains the prototypes for the _spin_*() APIs.
       *
       *  linux/spinlock.h:     builds the final spin_*() APIs.
       *
       * on UP builds:
       *
       *  linux/spinlock_type_up.h:
       *                        contains the generic, simplified UP spinlock type.
       *                        (which is an empty structure on non-debug builds)
       *
       *  linux/spinlock_types.h:
       *                        defines the generic type and initializers
       *
       *  linux/spinlock_up.h:
       *                        contains the __raw_spin_*()/etc. version of UP
       *                        builds. (which are NOPs on non-debug, non-preempt
       *                        builds)
       *
       *   (included on UP-non-debug builds:)
       *
       *  linux/spinlock_api_up.h:
       *                        builds the _spin_*() APIs.
       *
       *  linux/spinlock.h:     builds the final spin_*() APIs.
       */
      
      All SMP and UP architectures are converted by this patch.
      
      arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
      crosscompilers.  m32r, mips, sh, sparc, have not been tested yet, but should
      be mostly fine.
      
      From: Grant Grundler <grundler@parisc-linux.org>
      
        Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
        Builds 32-bit SMP kernel (not booted or tested).  I did not try to build
        non-SMP kernels.  That should be trivial to fix up later if necessary.
      
        I converted bit ops atomic_hash lock to raw_spinlock_t.  Doing so avoids
        some ugly nesting of linux/*.h and asm/*.h files.  Those particular locks
        are well tested and contained entirely inside arch specific code.  I do NOT
        expect any new issues to arise with them.
      
       If someone does ever need to use debug/metrics with them, then they will
        need to unravel this hairball between spinlocks, atomic ops, and bit ops
        that exist only because parisc has exactly one atomic instruction: LDCW
        (load and clear word).
      
      From: "Luck, Tony" <tony.luck@intel.com>
      
         ia64 fix
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NArjan van de Ven <arjanv@infradead.org>
      Signed-off-by: NGrant Grundler <grundler@parisc-linux.org>
      Cc: Matthew Wilcox <willy@debian.org>
      Signed-off-by: NHirokazu Takata <takata@linux-m32r.org>
      Signed-off-by: NMikael Pettersson <mikpe@csd.uu.se>
      Signed-off-by: NBenoit Boissinot <benoit.boissinot@ens-lyon.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      fb1c8f93
  22. 09 9月, 2005 1 次提交
    • D
      [SPARC64]: Inline membar()'s again. · 4d803fcd
      David S. Miller 提交于
      Since GCC has to emit a call and a delay slot to the
      out-of-line "membar" routines in arch/sparc64/lib/mb.S
      it is much better to just do the necessary predicted
      branch inline instead as:
      
      	ba,pt	%xcc, 1f
      	 membar	#whatever
      1:
      
      instead of the current:
      
      	call	membar_foo
      	 dslot
      
      because this way GCC is not required to allocate a stack
      frame if the function can be a leaf function.
      
      This also makes this bug fix easier to backport to 2.4.x
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4d803fcd
  23. 02 9月, 2005 1 次提交
  24. 30 8月, 2005 2 次提交
  25. 11 7月, 2005 1 次提交
  26. 28 6月, 2005 1 次提交
  27. 06 5月, 2005 1 次提交
  28. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4