1. 14 9月, 2014 1 次提交
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      net:fec: add enet refrence clock for i.MX 6SX chip · 9b5330ed
      Fugang Duan 提交于
      i.MX6sx enet has below clocks for user config:
      clk_ipg: ipg_clk_s, ipg_clk_mac0_s, 66Mhz
      clk_ahb: enet system clock, it is enet AXI clock for imx6sx.
      	 For imx6sx, it alos is the clock source of interrupt coalescing.
      	 The clock range: 200Mhz ~ 266Mhz.
      clk_ref: refrence clock for tx and rx. For imx6sx enet RGMII mode,
      	 the refrence clock is 125Mhz coming from internal PLL or external.
      	 In i.MX6sx-arm2 board, the clock is from internal PLL.
      	 clk_ref is optional, depends on board.
      clk_enet_out: The clock can be output from internal PLL. It can supply 50Mhz
      	 clock for phy. clk_enet_out is optional, depends on chip and board.
      clk_ptp: 1588 ts clock. It is optional, depends on chip.
      
      The patch add clk_ref to distiguish the different clocks.
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NFrank Li <Frank.Li@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9b5330ed
  2. 23 8月, 2014 1 次提交
    • N
      net: fec: ptp: avoid register access when ipg clock is disabled · 91c0d987
      Nimrod Andy 提交于
      The current kernel hang on i.MX6SX with rootfs mount from MMC.
      The root cause is that ptp uses a periodic timer to access enet register
      even if ipg clock is disabled.
      
      FEC ptp driver start one period timer to read 1588 counter register in the
      ptp init function that is called after FEC driver is probed.
      
      To save power, after FEC probe finish, FEC driver disable all clocks including
      ipg clock that is needed for register access.
      
      i.MX5x, i.MX6q/dl/sl FEC register access don't cause system hang when ipg clock
      is disabled, just return zero value. But for i.MX6sx SOC, it cause system hang.
      
      To avoid the issue, we need to check ptp clock status before ptp timer count access.
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      91c0d987
  3. 12 8月, 2014 1 次提交
  4. 25 7月, 2014 1 次提交
  5. 09 7月, 2014 17 次提交
  6. 08 7月, 2014 12 次提交
  7. 18 6月, 2014 1 次提交
    • F
      net: fec: Don't clear IPV6 header checksum field when IP accelerator enable · 62a02c98
      Fugang Duan 提交于
      The commit 96c50caa (net: fec: Enable IP header hardware checksum)
      enable HW IP header checksum for IPV4 and IPV6, which causes IPV6 TCP/UDP
      cannot work. (The issue is reported by Russell King)
      
      For FEC IP header checksum function: Insert IP header checksum. This "IINS"
      bit is written by the user. If set, IP accelerator calculates the IP header
      checksum and overwrites the IINS corresponding header field with the calculated
      value. The checksum field must be cleared by user, otherwise the checksum
      always is 0xFFFF.
      
      So the previous patch clear IP header checksum field regardless of IP frame
      type.
      
      In fact, IP HW detect the packet as IPV6 type, even if the "IINS" bit is set,
      the IP accelerator is not triggered to calculates IPV6 header checksum because
      IPV6 frame format don't have checksum.
      
      So this results in the IPV6 frame being corrupted.
      
      The patch just add software detect the current packet type, if it is IPV6
      frame, it don't clear IP header checksum field.
      
      Cc: Russell King <linux@arm.linux.org.uk>
      Reported-and-tested-by: NRussell King <linux@arm.linux.org.uk>
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      62a02c98
  8. 13 6月, 2014 6 次提交
    • N
      net: fec: Add software TSO support · 79f33912
      Nimrod Andy 提交于
      Add software TSO support for FEC.
      This feature allows to improve outbound throughput performance.
      
      Tested on imx6dl sabresd board, running iperf tcp tests shows:
      - 16.2% improvement comparing with FEC SG patch
      - 82% improvement comparing with NO SG & TSO patch
      
      $ ethtool -K eth0 tso on
      $ iperf -c 10.192.242.167 -t 3 &
      [  3] local 10.192.242.108 port 35388 connected with 10.192.242.167 port 5001
      [ ID] Interval       Transfer     Bandwidth
      [  3]  0.0- 3.0 sec   181 MBytes   506 Mbits/sec
      
      During the testing, CPU loading is 30%.
      Since imx6dl FEC Bandwidth is limited to SOC system bus bandwidth, the
      performance with SW TSO is a milestone.
      
      CC: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
      CC: Eric Dumazet <eric.dumazet@gmail.com>
      CC: David Laight <David.Laight@ACULAB.COM>
      CC: Li Frank <B20596@freescale.com>
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      79f33912
    • N
      net: fec: Add Scatter/gather support · 6e909283
      Nimrod Andy 提交于
      Add Scatter/gather support for FEC.
      This feature allows to improve outbound throughput performance.
      
      Tested on imx6dl sabresd board:
      Running iperf tests shows a 55.4% improvement.
      
      $ ethtool -K eth0 sg off
      $ iperf -c 10.192.242.167 -t 3 &
      [  3] local 10.192.242.108 port 52618 connected with 10.192.242.167 port 5001
      [ ID] Interval       Transfer     Bandwidth
      [  3]  0.0- 3.0 sec  99.5 MBytes   278 Mbits/sec
      
      $ ethtool -K eth0 sg on
      $ iperf -c 10.192.242.167 -t 3 &
      [  3] local 10.192.242.108 port 52617 connected with 10.192.242.167 port 5001
      [ ID] Interval       Transfer     Bandwidth
      [  3]  0.0- 3.0 sec   154 MBytes   432 Mbits/sec
      
      CC: Li Frank <B20596@freescale.com>
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6e909283
    • N
      net: fec: Increase buffer descriptor entry number · 55d0218a
      Nimrod Andy 提交于
      In order to support SG, software TSO, let's increase BD entry number.
      
      CC: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
      CC: Eric Dumazet <eric.dumazet@gmail.com>
      CC: David Laight <David.Laight@ACULAB.COM>
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      55d0218a
    • N
      net: fec: Factorize feature setting · 09d1e541
      Nimrod Andy 提交于
      In order to enhance the code readable, let's factorize the
      feature list.
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      09d1e541
    • N
      net: fec: Enable IP header hardware checksum · 96c50caa
      Nimrod Andy 提交于
      IP header checksum is calcalated by network layer in default.
      To support software TSO, it is better to use HW calculate the
      IP header checksum.
      
      FEC hw checksum feature request the checksum field in frame
      is zero, otherwise the calculative CRC is not correct.
      
      For segmentated TCP packet, HW calculate the IP header checksum again,
      it doesn't bring any impact. For SW TSO, HW calculated checksum bring
      better performance.
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      96c50caa
    • N
      net: fec: Factorize the .xmit transmit function · 61a4427b
      Nimrod Andy 提交于
      Make the code more readable and easy to support other features like
      SG, TSO, moving the common transmit function to one api.
      
      And the patch also factorize the getting BD index to it own function.
      
      CC: David Laight <David.Laight@ACULAB.COM>
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      61a4427b