Add the mailbox device DT node for OMAP5 SoC. The OMAP5 mailbox
IP is identical to that used in OMAP4.

The OMAP5 hwmod data no longer publishes the module address space,
so this patch fixes the WARN_ON backtrace associated with the
following trace during the kernel boot:
"omap_hwmod: mailbox: doesn't have mpu register target base".

Otherwise we get a warning like this:

WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2538 _init+0x1c0/0x3dc()
omap_hwmod: mailbox: doesn't have mpu register target base
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.15.0-rc2-00001-gb5e85a0 #45
[<c0015724>] (unwind_backtrace) from [<c00120f4>] (show_stack+0x10/0x14)
[<c00120f4>] (show_stack) from [<c05a1ccc>] (dump_stack+0x78/0x94)
[<c05a1ccc>] (dump_stack) from [<c0042a74>] (warn_slowpath_common+0x6c/0x8c)
[<c0042a74>] (warn_slowpath_common) from [<c0042b28>] (warn_slowpath_fmt+0x30/0x40)
[<c0042b28>] (warn_slowpath_fmt) from [<c0803b40>] (_init+0x1c0/0x3dc)
[<c0803b40>] (_init) from [<c0029c8c>] (omap_hwmod_for_each+0x34/0x5c)
[<c0029c8c>] (omap_hwmod_for_each) from [<c08042b0>] (__omap_hwmod_setup_all+0x24/0x40)
[<c08042b0>] (__omap_hwmod_setup_all) from [<c00088b8>] (do_one_initcall+0x34/0x160)
[<c00088b8>] (do_one_initcall) from [<c07f7bf4>] (kernel_init_freeable+0xfc/0x1c8)
[<c07f7bf4>] (kernel_init_freeable) from [<c059c4f4>] (kernel_init+0x8/0xe4)
[<c059c4f4>] (kernel_init) from [<c000eaa8>] (ret_from_fork+0x14/0x2c)
Signed-off-by: NSuman Anna <s-anna@ti.com>
[tony@atomide.com: updated description to for the warning]
Signed-off-by: NTony Lindgren <tony@atomide.com>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NTony Lindgren <tony@atomide.com>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: linux-omap@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NTony Lindgren <tony@atomide.com>

The USB3 PHY driver (ti-pipe3) was updated so that the relevant
clock phandles are expected in the DT node.
Provide the necessary clocks.
Reported-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Use a meaningful name for the reference clocks so that it indicates the
function.

Update the OMAP4+ USB Host node as well to be in sync with the changes.
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The GPMC clock is derived from l3_ick. The simplest solution is
to reference directly l3_ick to provide the GPMC fck in order to
get correct timings. The real management of the clock is left to
hwmod.

Cc: stable@vger.kernel.org # v3.14+
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The IOMMU DT nodes have been added for the DSP and IPU
subsystems. The MMUs in OMAP5 are identical to those in
OMAP4, including the bus error back capability on IPU.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Added device tree bindings for dwc3, usb2 and usb3 PHYs. The documentation
of these can be found at Documentation/devicetree/bindings/phy/phy-bindings.txt
and Documentation/devicetree/bindings/phy/ti-phy.txt.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The OMAP EHCI and OHCI controllers are not compatible with drivers
other than "ti,ehci-omap" and "ti,ohci-omap3" respectively, so get
rid of the incompatible ids.

CC: Alan Stern <stern@rowland.harvard.edu>
CC: Nishant Menon <nm@ti.com>
CC: Kevin Hilman <khilman@linaro.org>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add pbias regulator node as a child of system control
module - syscon.
Signed-off-by: NBalaji T K <balajitk@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Tested-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Tested-by: NStefan Roese <sr@denx.de>
Signed-off-by: NChris Ball <chris@printf.net>

Add Dynamic Memory Manager (DMM) bindings for OMAP4 and OMAP5 and DRA7x devices.
DMM only requires address and irq information.

Add documentation for the DMM bindings.

Originally worked on by Andy Gross <andygro@gmail.com>

Cc: Andy Gross <andygro@gmail.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock.

OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use
dpll_mpu clock.

Latency used is the generic latency defined in omap-cpufreq
driver.
Signed-off-by: NNishanth Menon <nm@ti.com>
Acked-by: NAcked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Board dts files will need to enable the IP nodes which they are using and
does not have to care about the not used ones (to disable them).
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add a new generic property "#hwlock-cells" to the hwspinlock
DT nodes on OMAP4, OMAP5 and AM33xx. This common property allows
different platform implementations to define the args specifier
length. OMAP implementations will always use a value of 1.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

OMAP5 devices can reach high temperatures and thus
needs to have cpufreq-cooling on systems running on it.

This patch adds the required cooling device properties
so that cpufreq-cpu0 driver loads the cooling device.

Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>

This patch changes the dtsi entry on omap5 to contain
the thermal data. This data will enable the passive
cooling with CPUfreq cooling device at 100C. The
system will do a thermal shutdown at 125C whenever
any of its sensors sees this level.

Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>

Add the hwspinlock device tree node for OMAP5 SoCs.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add DT OPP table for OMAP54xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.

The data is based on OMAP543x ES2.0 DM Operating Condition Addendum
Version 0.6(April 2013)

NOTE: The voltage and frequency values work well only on NOM samples
and are supposed to work properly only with ABB/AVS for ALL OPPs.

TODO: Add SPEED BIN OPP after ABB and AVS support so the cpufreq works
on all samples seamlessly. Clock node is pending alignment for clock
dts conversion

[nm@ti.com: sync to latest and fixes]
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

regulator smps123 supply from Palmas PMIC powers CPU0 on OMAP5uEVM.

Based on a patch by J Keerthy <j-keerthy@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

Currently, on OMAP5, i2c1 and i2c5 defer probe due to pinctrl
dependencies. This changes the i2c ID each bus is registered with in
i2c-dev interface. As a result of this, many userspace tools break and
there is no consistent manner to fix the same if the i2c dev interface
have no consistent numbering.

Since this could happen for other OMAP derivatives, provide i2c alias
for all OMAP3+ SoCs to allow ordering the i2c devices correctly.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

Added dr_mode property in dwc3 and set its default mode to device.
Signed-off-by: NGeorge Cherian <george.cherian@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to pass this information from DT.

Update the am33xx/omap4 and omap5 dtsi files with the
new bindings for modules which either should not be
idled. reset or both. A later patch would cleanup the
same information that exists today as part of the hwmod
data files.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

The arm arch timers frequency are now programmed in the CNTFREQ
per-cpu register by the timer code using the secure API [1].
So remove the redundant entry from the dts.

[1] http://marc.info/?l=linux-omap&m=138139106312786&w=2Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

Without this node, there will be no palmas driver to notify
dwc3 that a cable has been connected and, without that, dwc3
will never initialize.
Signed-off-by: NFelipe Balbi <balbi@ti.com>
[kishon@ti.com: added dt properties for enabling vbus/id interrupts
and fixed vbus-supply value after SMPS10 is modeled as 2 regulators]
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

Split USB2 PHY and USB3 PHY into separate omap-control-usb
nodes. Get rid of "ti,type" property.

CC: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Fix the DTS data for ocp2scp node by adding the
missing reg property.
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

USB3 block has a 64KiB space, another 64KiB is
used for the wrapper.

Without this change, resource_size() will get
confused and driver won't probe because size
will be negative.
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>

all other drivers using Synopsys IPs with DT
have a compatible of snps,$driver, in order
to add consistency, we are switching over to
snps,dwc3 but keeping synopsys,dwc3 in the core
driver to maintain backwards compatibility.

New DTS bindings should NOT use synopsys,dwc3.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Add bandgap device DT entry for OMAP5 dtsi.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
[benoit.cousson@linaro.org: Fix alignement and use the macros
for IRQ attributes]
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Provide the RESET regulators for the USB PHYs, the USB Host
port modes and the PHY devices.

Also provide pin multiplexer information for the USB host
pins.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
[r.sricharan@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Using constants for pinctrl allows a better readability, and removes
redundancy with comments.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Use the constants defined in include/dt-bindings/interrupt-controller/
to enhance readability.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Use standard GPIO constants to enhance the readability of DT GPIOs.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Replace /include/ by #include for OMAP2+ DT, in order to use the
C pre-processor, making use of #define features possible.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

The carveouts that have been reserved for multimedia usecases
are not being used currently by any driver and so have been
cleaned up. Memory will be allocated runtime through CMA for
enabling the multimedia usecases.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM.
The PWM capability property is missing from the node definitions of
couple of timers.

Add ti,timer-pwm attribute for timer 5, 6, 8 and 11.
Signed-off-by: NSuman Anna <s-anna@ti.com>
[benoit.cousson@linaro.org: Update changelog and subject to highlight
the fix]
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

This patch updates the in-kernel dts files according to the latest cpus
and cpu bindings updates for ARM.
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Add the "ti,gpio-always-on" property to the appropriate GPIO banks to
indicate which banks are always powered and will never lose logic state.
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>