1. 13 8月, 2014 1 次提交
  2. 14 8月, 2013 1 次提交
  3. 02 5月, 2013 1 次提交
  4. 30 4月, 2012 1 次提交
  5. 08 4月, 2012 1 次提交
  6. 20 12月, 2011 3 次提交
    • S
      powerpc/44x: Enable CONFIG_RELOCATABLE for PPC44x · 26ecb6c4
      Suzuki Poulose 提交于
      The following patch adds relocatable kernel support - based on processing
      of dynamic relocations - for PPC44x kernel.
      
      We find the runtime address of _stext and relocate ourselves based
      on the following calculation.
      
      	virtual_base = ALIGN(KERNELBASE,256M) +
      			MODULO(_stext.run,256M)
      
      relocate() is called with the Effective Virtual Base Address (as
      shown below)
      
                  | Phys. Addr| Virt. Addr |
      Page (256M) |------------------------|
      Boundary    |           |            |
                  |           |            |
                  |           |            |
      Kernel Load |___________|_ __ _ _ _ _|<- Effective
      Addr(_stext)|           |      ^     |Virt. Base Addr
                  |           |      |     |
                  |           |      |     |
                  |           |reloc_offset|
                  |           |      |     |
                  |           |      |     |
                  |           |______v_____|<-(KERNELBASE)%256M
                  |           |            |
                  |           |            |
                  |           |            |
      Page(256M)  |-----------|------------|
      Boundary    |           |            |
      
      The virt_phys_offset is updated accordingly, i.e,
      
      	virt_phys_offset = effective. kernel virt base - kernstart_addr
      
      I have tested the patches on 440x platforms only. However this should
      work fine for PPC_47x also, as we only depend on the runtime address
      and the current TLB XLAT entry for the startup code, which is available
      in r25. I don't have access to a 47x board yet. So, it would be great if
      somebody could test this on 47x.
      Signed-off-by: NSuzuki K. Poulose <suzuki@in.ibm.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Kumar Gala <galak@kernel.crashing.org>
      Cc: Tony Breeds <tony@bakeyournoodle.com>
      Cc: Josh Boyer <jwboyer@gmail.com>
      Cc: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
      Signed-off-by: NJosh Boyer <jwboyer@gmail.com>
      26ecb6c4
    • S
      powerpc/44x: Enable DYNAMIC_MEMSTART for 440x · 23913245
      Suzuki Poulose 提交于
      DYNAMIC_MEMSTART(old RELOCATABLE) was restricted only to PPC_47x variants
      of 44x. This patch enables DYNAMIC_MEMSTART for 440x based chipsets.
      Signed-off-by: NSuzuki K. Poulose <suzuki@in.ibm.com>
      Cc: Josh Boyer <jwboyer@gmail.com>
      Cc: Kumar Gala <galak@kernel.crashing.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: linux ppc dev <linuxppc-dev@lists.ozlabs.org>
      Signed-off-by: NJosh Boyer <jwboyer@gmail.com>
      23913245
    • S
      powerpc: Rename mapping based RELOCATABLE to DYNAMIC_MEMSTART for BookE · 0f890c8d
      Suzuki Poulose 提交于
      The current implementation of CONFIG_RELOCATABLE in BookE is based
      on mapping the page aligned kernel load address to KERNELBASE. This
      approach however is not enough for platforms, where the TLB page size
      is large (e.g, 256M on 44x). So we are renaming the RELOCATABLE used
      currently in BookE to DYNAMIC_MEMSTART to reflect the actual method.
      
      The CONFIG_RELOCATABLE for PPC32(BookE) based on processing of the
      dynamic relocations will be introduced in the later in the patch series.
      
      This change would allow the use of the old method of RELOCATABLE for
      platforms which can afford to enforce the page alignment (platforms with
      smaller TLB size).
      
      Changes since v3:
      
      * Introduced a new config, NONSTATIC_KERNEL, to denote a kernel which is
        either a RELOCATABLE or DYNAMIC_MEMSTART(Suggested by: Josh Boyer)
      Suggested-by: NScott Wood <scottwood@freescale.com>
      Tested-by: NScott Wood <scottwood@freescale.com>
      Signed-off-by: NSuzuki K. Poulose <suzuki@in.ibm.com>
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: Kumar Gala <galak@kernel.crashing.org>
      Cc: Josh Boyer <jwboyer@gmail.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: linux ppc dev <linuxppc-dev@lists.ozlabs.org>
      Signed-off-by: NJosh Boyer <jwboyer@gmail.com>
      0f890c8d
  7. 09 12月, 2011 1 次提交
  8. 20 9月, 2011 1 次提交
    • S
      powerpc/32: Pass device tree address as u64 to machine_init · 6dece0eb
      Scott Wood 提交于
      u64 is used rather than phys_addr_t to keep things simple, as
      this is called from assembly code.
      
      Update callers to pass a 64-bit address in r3/r4.  Other unused
      register assignments that were once parameters to machine_init
      are dropped.
      
      For FSL BookE, look up the physical address of the device tree from the
      effective address passed in r3 by the loader.  This is required for
      situations where memory does not start at zero (due to AMP or IOMMU-less
      virtualization), and thus the IMA doesn't start at zero, and thus the
      device tree effective address does not equal the physical address.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      6dece0eb
  9. 12 7月, 2011 1 次提交
  10. 31 3月, 2011 1 次提交
  11. 29 11月, 2010 1 次提交
  12. 23 8月, 2010 1 次提交
  13. 05 5月, 2010 3 次提交
  14. 27 8月, 2009 1 次提交
    • B
      powerpc/mm: Cleanup handling of execute permission · ea3cc330
      Benjamin Herrenschmidt 提交于
      This is an attempt at cleaning up a bit the way we handle execute
      permission on powerpc. _PAGE_HWEXEC is gone, _PAGE_EXEC is now only
      defined by CPUs that can do something with it, and the myriad of
      #ifdef's in the I$/D$ coherency code is reduced to 2 cases that
      hopefully should cover everything.
      
      The logic on BookE is a little bit different than what it was though
      not by much. Since now, _PAGE_EXEC will be set by the generic code
      for executable pages, we need to filter out if they are unclean and
      recover it. However, I don't expect the code to be more bloated than
      it already was in that area due to that change.
      
      I could boast that this brings proper enforcing of per-page execute
      permissions to all BookE and 40x but in fact, we've had that now for
      some time as a side effect of my previous rework in that area (and
      I didn't even know it :-) We would only enable execute permission if
      the page was cache clean and we would only cache clean it if we took
      and exec fault. Since we now enforce that the later only work if
      VM_EXEC is part of the VMA flags, we de-fact already enforce per-page
      execute permissions... Unless I missed something
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ea3cc330
  15. 20 8月, 2009 1 次提交
    • B
      powerpc: Use names rather than numbers for SPRGs (v2) · ee43eb78
      Benjamin Herrenschmidt 提交于
      The kernel uses SPRG registers for various purposes, typically in
      low level assembly code as scratch registers or to hold per-cpu
      global infos such as the PACA or the current thread_info pointer.
      
      We want to be able to easily shuffle the usage of those registers
      as some implementations have specific constraints realted to some
      of them, for example, some have userspace readable aliases, etc..
      and the current choice isn't always the best.
      
      This patch should not change any code generation, and replaces the
      usage of SPRN_SPRGn everywhere in the kernel with a named replacement
      and adds documentation next to the definition of the names as to
      what those are used for on each processor family.
      
      The only parts that still use the original numbers are bits of KVM
      or suspend/resume code that just blindly needs to save/restore all
      the SPRGs.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ee43eb78
  16. 27 4月, 2009 1 次提交
  17. 29 12月, 2008 1 次提交
  18. 21 12月, 2008 2 次提交
  19. 10 7月, 2008 1 次提交
  20. 18 6月, 2008 1 次提交
  21. 03 6月, 2008 1 次提交
  22. 06 5月, 2008 1 次提交
    • S
      [POWERPC] 4xx: Fix problem with new TLB storage attibute fields on 440x6 core · a96df496
      Stefan Roese 提交于
      The new 440x6 core used on AMCC 460EX/GT introduces new storage attibure
      fields to the TLB2 word. Those are:
      
      Bit  11   12   13   14   15
           WL1  IL1I IL1D IL2I IL2D
      
      With these bits the cache (L1 and L2) can be configured in a more flexible
      way, instruction- and data-cache independently now. The "old" I and W bits
      are still available and setting these old bits will automically set these
      new bits too (for backward compatibilty).
      
      The current code does not clear these fields resulting in disabling the cache
      by chance. This patch now makes sure that these new bits are cleared when
      the TLB2 word is written.
      Signed-off-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      a96df496
  23. 17 4月, 2008 1 次提交
    • K
      [POWERPC] Rework Book-E debug exception handling · eb0cd5fd
      Kumar Gala 提交于
      The architecture allows for "Book-E" style debug interrupts to either go
      to critial interrupts of their own debug interrupt level.  To allow for
      a dynamic kernel to support machines of either type we want to be able to
      compile in the interrupt handling code for both exception levels.
      
      Towards this goal we renamed the debug handling macros to specify the
      interrupt level in their name (DEBUG_CRIT_EXCEPTION/DebugCrit and
      DEBUG_DEBUG_EXCEPTION/DebugDebug).
      
      Additionally, on the Freescale Book-e parts we expanded the exception
      stacks to cover the maximum case of needing three exception stacks (normal,
      machine check and debug).
      
      There is some kernel text space optimization to be gained if a kernel is
      configured for a specific Freescale implementation but we aren't handling
      that now to allow for the single kernel image support.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      eb0cd5fd
  24. 24 12月, 2007 1 次提交
  25. 07 12月, 2007 1 次提交
  26. 12 10月, 2007 1 次提交
  27. 03 10月, 2007 1 次提交
  28. 19 9月, 2007 1 次提交
  29. 14 9月, 2007 1 次提交
    • K
      [POWERPC] Fix modpost warnings from head*.S on ppc32 · 748a7683
      Kumar Gala 提交于
      We get warnings like the following from the various ppc32 head*.S files:
      
      WARNING: vmlinux.o(.text+0x358): Section mismatch: reference to .init.text:early_init (between 'skpinv' and 'interrupt_base')
      WARNING: vmlinux.o(.text+0x380): Section mismatch: reference to .init.text:machine_init (between 'skpinv' and 'interrupt_base')
      WARNING: vmlinux.o(.text+0x384): Section mismatch: reference to .init.text:MMU_init (between 'skpinv' and 'interrupt_base')
      WARNING: vmlinux.o(.text+0x3aa): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base')
      WARNING: vmlinux.o(.text+0x3ae): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base')
      
      Added a .text.head section simliar to what other architectures do since
      modpost already excludes this from its warnings.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      748a7683
  30. 07 9月, 2007 1 次提交
  31. 08 5月, 2007 2 次提交
    • D
      [POWERPC] Early serial debug support for PPC44x · d9b55a03
      David Gibson 提交于
      This adds support for early serial debugging via the built in
      port on IBM/AMCC PowerPC 44x CPUs.  It uses a bolted TLB entry in
      address space 1 for the UART's mapping, allowing robust debugging both
      before and after the initialization of the MMU.
      Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d9b55a03
    • D
      [POWERPC] Add powerpc/platforms/44x, disable platforms/4xx for now · 2cd97647
      David Gibson 提交于
      This prepares for Ebony/440 support by creating an
      arch/powerpc/platforms/44x directory.  It is populated with a single
      misc_44x.S file, into which is moved the 44x specific reset code from
      head_44x.S (on the grounds that we should really stop clogging up the
      head_* files with random asm helper routines).
      
      At the same time, we disable the (empty save Kconfig and Makefile)
      arch/powerpc/platforms/4xx directory from the arch/powerpc/platforms
      Makefile.  Contrary to the comment in
      arch/powerpc/platforms/4xx/Makefile, attempting to build such an empty
      Makefile will fail, thus breaking compile for the 44x platforms we're
      about to add.  It can go back in once we start porting some of the 40x
      platforms (and thus it becomes non-empty).
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      2cd97647
  32. 02 5月, 2007 1 次提交
  33. 13 2月, 2007 1 次提交
  34. 01 7月, 2006 1 次提交