Add WM8903 codec nodes, and top-level sound complex node for basic
analog audio over headset jack and internal speakers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Add nodes for the Tegra30 AHUB and I2S controllers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Both the Tegra30 I2S and AHUB modules used clocks, and hence currently
require AUXDATA in order to get specific device names so that clock
lookups work.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Set up the audio clock tree for Tegra30 in an equivalent fashion to the
existing setup for Tegra20.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

pll_a uses pll_p_out1 as its parent. Therefore this clock needs to be
initialized to make sure pll_a has a known input clock. Failure to do so
will cause the system to crash early in the bootup.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra30 AHUB driver must call tegra_periph_reset_deassert() for all
devices on the AHUB's configlink bus. The AHUB driver must be able to
call clk_get_sys() to retrieve the clock parameter for this function.
Add the necessary clock aliases to allow this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Print an explicit error message in various failure cases to allow
easier diagnosis.

WARN_ON() some internal failures that users/clients shouldn't be able to
trigger.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

* Only provide debugfs-relates ops when CONFIG_DEBUG_FS is enabled.
* Implement pin_config_group_dbg_show op.
* Implement pin_config_config_dbg_show op.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Rather than having a single tegra-pinctrl driver that determines whether
it's running on Tegra20 or Tegra30, instead have separate drivers for
each that call into utility functions to implement the majority of the
driver. This change is based on review feedback of the SPEAr pinctrl
driver, which had originally copied to Tegra driver structure.

This requires that the two drivers have unique names. Update a couple
spots in arch/arm/mach-tegra for the name change.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

This adds a complete pinmux configuration to all Tegra20 device tree
files. This allows removal of board-dt-tegra20.c's use of the pinmux
board files, and the special device tree handling in board-pinmux.c.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>

This adds a minimal pinmux configuration to the Tegra Cardhu device
tree. Initially, just the built-in eMMC and SD card slot are configured.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net

The pinctrl driver is now active and used by all boards. Remove the
old pinmux driver.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>

* Rename old pinmux and new pinctrl platform driver and DT match table
  entries, so the new driver gets instantiated.
* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the
  pinmux.
* Re-write board-*-pinmux.c so that the pinmux configuration tables are
  in pinctrl format.

Ventana's pin mux table needed some edits on top of the basic format
conversion, since some mux options that were previously marked as
reserved are now valid in the new pinctrl driver. Attempting to use the
old reserved names will result in a failure. Specifically, groups lpw0,
lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,
and group pta was changed from function rsvd2 to hdmi.

All boards' pin mux tables needed some edits on top of the based format
conversion, since function i2c was split into i2c1 (first general I2C
controller) and i2cp (power I2C controller) to better align function
definitions with HW blocks.

Due to the split of mux tables into pure mux and pull/tristate tables,
many entries in the separate Seaboard/Ventana tables could be merged
into the common table, since the entries differed only in the portion
in one of the tables, not both.

Most pin groups allow configuration of mux, tri-state, and pull. However,
some don't allow pull configuration, which is instead configured by new
groups that only allow pull configuration. This is a reflection of the
true HW capabilities, which weren't fully represented by the old pinmux
driver. This required adding new pull table entries for those new groups,
and setting many other entries' pull configuration to
TEGRA_PINCONFIG_DONT_SET.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>

Recent pinctrl discussions concluded that gpiolib APIs should in fact do
whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
required. This change implements this for the Tegra GPIO driver, and removes
calls to the Tegra-specific APIs from drivers and board files.

Cc: Chris Ball <cjb@laptop.org>
Cc: linux-mmc@vger.kernel.org
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: Chris Ball <cjb@laptop.org> # for sdhci-tegra.c
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>

Don't call gpio_request() or gpio_direction_input() for ISL29018_IRQ.
This pin is only used as an IRQ, and hence no GPIO configuration should
be necessary; the GPIO/IRQ driver should (and does) perform any required
setup when the IRQ is requested.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

When a Tegra GPIO is used as an IRQ, it should be enabled as a GPIO (so
the pinmux module isn't driving it as an output) and configured as a GPIO
input (so the GPIO module isn't driving it as an output). Set this up
automatically whenever an IRQ is requested, so that users of IRQs don't
need to do this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Instead of having board files manually request and initialize USB VBUS
GPIOs, fill in the USB driver's platform data and have it do it.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Add a vbus_gpio field to platform data. This mirrors the device tree
property nvidia,vbus-gpio. This makes the VBUS GPIO handling identical
between booting with board files and device tree; the driver always does
it.

This removes the need for board files to request and initialize the GPIO
early during their boot process, perhaps even before the GPIO driver is
ready to process the request.

Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: linux-usb@vger.kernel.org
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>

Pin name is more useful to users.

After change, when cat pingroups in sysfs, it becomes:
root@freescale /sys/kernel/debug/pinctrl/20e0000.iomuxc$ cat pingroups
registered pin groups:
group: uart4grp-1
pin 219 (MX6Q_PAD_KEY_ROW0)
pin 218 (MX6Q_PAD_KEY_COL0)

group: usdhc4grp-1
pin 305 (MX6Q_PAD_SD4_CMD)
pin 306 (MX6Q_PAD_SD4_CLK)
pin 315 (MX6Q_PAD_SD4_DAT0)
pin 316 (MX6Q_PAD_SD4_DAT1)
pin 317 (MX6Q_PAD_SD4_DAT2)
pin 318 (MX6Q_PAD_SD4_DAT3)
pin 319 (MX6Q_PAD_SD4_DAT4)
pin 320 (MX6Q_PAD_SD4_DAT5)
pin 321 (MX6Q_PAD_SD4_DAT6)
pin 322 (MX6Q_PAD_SD4_DAT7)
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Pin name is more useful to users.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

These functions allow the driver core to automatically clean up any
allocations made by drivers, thus leading to simplified drivers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When we compile pinctrl layer for platforms without CONFIG_PINCONF, we get
following compilation errors:

drivers/built-in.o: In function `pinctrl_show':
linux-2.6/drivers/pinctrl/core.c:1116: undefined
reference to `pinconf_show_setting'
drivers/built-in.o: In function `pinctrl_maps_show':
linux-2.6/drivers/pinctrl/core.c:1071: undefined
reference to `pinconf_show_map'
drivers/built-in.o: In function `pinctrl_init_device_debugfs':
linux-2.6/drivers/pinctrl/core.c:1224: undefined
reference to `pinconf_init_device_debugfs'
make[1]: *** [.tmp_vmlinux1] Error 1

This patch fixes this.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a pinconf op so that pin controller drivers can decode their pin
config settings for debugfs.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Only provide prototypes for pin{mux,conf}.c debugfs-related functions
when both CONFIG_PIN* /and/ CONFIG_DEBUG_FS are enabled, otherwise
provide static inlines.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

With the finalization of the external driver API and the device
tree support, this subsystem is now mature and can be promoted to
non-experimental status.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Implement pinctrl_ops dt_node_to_map() and dt_free_map(). These allow
complete specification of the desired pinmux configuration using device
tree.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Define a new binding for the Tegra pin controller, which is capable of
defining all aspects of desired pin multiplexing and pin configuration.
This is all based on the new common pinctrl bindings.

Add Tegra30 binding based on Tegra20 binding.

Add some basic stuff that was missing before:
* How many and what reg property entries must be provided.
* An example.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This places the file in the new location for all pin controller bindings.

Also, rename the file using the full compatible value for easier
avoidance of conflicts between multiple bindings.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The core pin controller bindings define:
* The fact that pin controllers expose pin configurations as nodes in
  device tree.
* That the bindings for those pin configuration nodes is defined by the
  individual pin controller drivers.
* A standardized set of properties for client devices to define numbered
  or named pin configuration states, each referring to some number of the
  afore-mentioned pin configuration nodes.
* That the bindings for the client devices determines the set of numbered
  or named states that must exist.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds macros of_property_for_each_u32() and
of_property_for_each_string(), which iterate over an array of values
within a device-tree property. Usage is for example:

struct property *prop;
const __be32 *p;
u32 u;
of_property_for_each_u32(np, "propname", prop, p, u)
	printk("U32 value: %x\n", u);

struct property *prop;
const char *s;
of_property_for_each_string(np, "propname", prop, s)
	printk("String value: %s\n", s);

Based on work by Rob Herring <robherring2@gmail.com>

Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If drivers try to obtain pinctrl handles for a pin controller that
has not yet registered to the subsystem, we need to be able to
back out and retry with deferred probing. So let's return
-EPROBE_DEFER whenever this location fails. Also downgrade the
errors to info, maybe we will even set them to debug once the
deferred probing is commonplace.

Cc: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch can avoid kernel oops in case the mux or config
function is not supported by driver.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Do not use get_functions_count before checking.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Most of the SoC drivers implement list_groups() and list_functions()
routines for pinctrl and pinmux. These routines continue returning
zero until the selector argument is greater than total count of
available groups or functions.

This patch replaces these list_*() routines with get_*_count()
routines, which returns the number of available selection for SoC
driver. pinctrl layer will use this value to check the range it can
choose.

This patch fixes all user drivers for this change. There are other
routines in user drivers, which have checks to check validity of
selector passed to them. It is also no more required and hence
removed.

Documentation updated as well.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
[Folded in fix and fixed a minor merge artifact manually]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

As long as there is no other non-const variable marked __initdata in the
same compilation unit it doesn't hurt. If there were one however
compilation would fail with

	error: $variablename causes a section type conflict

because a section containing const variables is marked read only and so
cannot contain non-const variables.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Randy Dunlap <rdunlap@xenotime.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Missed one group from the documentation when proofreading.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

pinctrl/devicetree.c won't compile when !CONFIG_PINCTRL, since the
pinctrl headers don't declare some types when !PINCTRL. Make sure
pinctrl/Makefile only attempts to compile devicetree.c when OF &&
PINCTRL.
Acked-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

During pinctrl_get(), if the client device has a device tree node, look
for the common pinctrl properties there. If found, parse the referenced
device tree nodes, with the help of the pinctrl drivers, and generate
mapping table entries from them.

During pinctrl_put(), free any results of device tree parsing.
Acked-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Most code assumes that the pinctrl ops are present. Validate this when
registering a pinctrl driver. Remove the one place in the code that
was checking whether one of these non-optional ops was present.
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>