- 27 9月, 2015 1 次提交
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由 Chen-Yu Tsai 提交于
A23/A33 have a PWM controller that is compatible to the one on the A20. Add a device node for it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 12 8月, 2015 1 次提交
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由 Maxime Ripard 提交于
The A23 and A33 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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- 28 7月, 2015 1 次提交
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由 Maxime Ripard 提交于
The current DTs were setting the cell size to 2, but used the default xlate function that was assuming an interrupt cell size of 1, leading to the second part of the cell (the flags) being ignored, while we were having an inconsistent binding between the interrupts and gpio (that could also be used as interrupts). That "binding" doesn't work either with newer SoCs that have multiple irq banks. Now that we fixed the pinctrl driver to handle this like it should always have been handled, convert the DT users, and while we're at it, remove the size-cells property of PIO that is completely useless. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org>
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- 06 7月, 2015 1 次提交
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由 Chen-Yu Tsai 提交于
A23/A33 has one pair of EHCI/OHCI USB controllers. There are 2 USB PHYs, one for the USB OTG controller, one for the EHCI/OHCI pair. The latter may also support HSIC, though none of the available boards utilize this, so this is not supported yet. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 03 6月, 2015 1 次提交
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由 Chen-Yu Tsai 提交于
mmc2 is mostly used with eMMC flash chips, as an alternative to raw NAND flash chips. 8 bit mmc is commonly used. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 02 6月, 2015 2 次提交
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由 Hans de Goede 提交于
Add an usb_clk node for a23/a33. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NChen-Yu Tsai <wens@csie.org>
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由 Vishnu Patekar 提交于
Rename sun8i-a23.dtsi to sun8i-a23-a33.dtsi as the base dtsi for the A33 is 99% the same and add a new sun8i-a23.dtsi including sun8i-a23-a33.dtsi and setting the few things not shared with the A33 (mbus-clk, pio compatible and interrupts). Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Tested-by: NChen-Yu Tsai <wens@csie.org>
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- 10 5月, 2015 2 次提交
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由 Maxime Ripard 提交于
A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 27 4月, 2015 3 次提交
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由 Chen-Yu Tsai 提交于
Add enable-method property to enable SMP support. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The A23 SoC has the architected timer, but the existing firmware from Allwinner does not set CNTFRQ at all. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 26 1月, 2015 1 次提交
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由 Maxime Ripard 提交于
Commit f77d55a3 ("serial: 8250_dw: get index of serial line from DT aliases") made the serial driver now use the serial aliases to get the tty number, pointing out that our aliases have been wrong all along. Remove them from the DTSI and add custom ones in the relevant boards. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 21 1月, 2015 5 次提交
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由 Hans de Goede 提交于
The A23 has the same lradc controller as previous Allwinner SoCs. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
Add simplefb nodes for "[de_fe0-]de_be0-lcd0" and "[de_fe0-]de_be0-lcd0-tve0" display pipelines for when u-boot has set up a pipeline to drive a LCD panel / VGA output rather then the HDMI output. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The pinctrl nodes require some extra opaque arguments for the pull up and drive strength values. Introduce a new header file and convert the device trees to replace these opaque numbers by defines. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
Prepare the device trees to use the C preprocessor. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 14 1月, 2015 1 次提交
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由 Maxime Ripard 提交于
Add the sample and output clocks for the MMC phase support. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NChen-Yu Tsai <wens@csie.org> Tested-by: NChen-Yu Tsai <wens@csie.org>
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- 22 12月, 2014 2 次提交
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由 Chen-Yu Tsai 提交于
Now that the clock driver supports PLL6 and MBUS on sun8i correctly, add the corresponding clock nodes to the dtsi. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The clock driver has unified support for the ahb1 clock. Unify the clock nodes so it works. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 25 11月, 2014 1 次提交
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由 Arnd Bergmann 提交于
This reverts commit 338302ae. This is one of two commits that resulted in a boot regression. Conflicts: arch/arm/boot/dts/sun6i-a31.dtsi Signed-off-by: NArnd Bergmann <arnd@arndb.de> Link: http://lkml.kernel.org/r/7h1toxr0ku.fsf@deeprootsystems.com
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- 24 11月, 2014 1 次提交
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由 Chen-Yu Tsai 提交于
The apb2 clocks are actually the same as apb1 clocks on the other sunxi platforms, hence compatible with "allwinner,sun4i-a10-apb1-clk". Update the dtsi to use the new unified apb1 clk. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 23 11月, 2014 1 次提交
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由 Maxime Ripard 提交于
During the GPL to GPL/X11 licensing migration, the GPL notice introduced mentionned the device trees as a library, which is not really accurate. It began to spread by copy and paste. Fix all these library mentions to reflect the file that it's actually just a file. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 11 11月, 2014 1 次提交
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由 Chen-Yu Tsai 提交于
The apb2 clocks are actually the same as apb1 clocks on the other sunxi platforms, hence compatible with "allwinner,sun4i-a10-apb1-clk". Update the dtsi to use the new unified apb1 clk. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 28 10月, 2014 1 次提交
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由 Maxime Ripard 提交于
During the GPL to GPL/X11 licensing migration, the GPL notice introduced mentionned the device trees as a library, which is not really accurate. It began to spread by copy and paste. Fix all these library mentions to reflect the file that it's actually just a file. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 20 9月, 2014 1 次提交
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由 Chen-Yu Tsai 提交于
Add the DMA controller node and DMA bindings to the supported devices. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 07 9月, 2014 1 次提交
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由 Maxime Ripard 提交于
The current GPL only licensing on the DTSI makes it very impractical for other software components licensed under another license. In order to make it easier for them to reuse our device trees, relicense our DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NArnd Bergmann <arnd@arndb.de>
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- 19 8月, 2014 1 次提交
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由 Chen-Yu Tsai 提交于
Add nodes for the 3 i2c controllers found on A23 SoCs to the sun8i DTSI. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 17 8月, 2014 9 次提交
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由 Chen-Yu Tsai 提交于
This adds pin-muxing info for the i2c controller / port combinations which are known to be used on actual boards. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Add nodes for the 3 mmc controllers found on A23 SoCs to the sun8i DTSI. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
The MMC module clocks on sun8i are the same as those found on previous Allwinner SoCs, module 0 clocks. This patch adds the clocks nodes to the dtsi with existing drivers. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
R_UART is available on extra pads on certain tablets, which makes it ideal for use as a console. Here we add the pins for it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
uart0 on sun8i is only muxed with mmc0, which makes it a poor choice for the console. However, some tablets only have pads for uart0 available on the circuit board. Here we add the uart0 pinmux set for people who need it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Now that we have a driver for the R_PIO controller, add the corresponding device node to the dtsi. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
Now that we have a driver for the sun8i PIO controller, add the corresponding device node to the dtsi. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Chen-Yu Tsai 提交于
sun8i shares the same rtc hardware as sun6i. Now that we have a driver for it, add a device node to the DTSI for it so we can use it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 15 7月, 2014 1 次提交
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由 Chen-Yu Tsai 提交于
With sun8i PRCM support available, we can add the PRCM clock and reset controller nodes to the DTSI. Also update R_UART's clock phandle and add it's reset control phandle. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 07 7月, 2014 1 次提交
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由 Chen-Yu Tsai 提交于
The A23 has the same MMIO reset controllers matching the clocks gates, just like in the A31. This patch adds the reset controller nodes and the reset control phandles for the peripherals needing them to the DTSI. Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some additions to the machine code. It is used to support the hstimer. However the hstimer on sun8i only has 1 timer, which is somewhat useless. Support for it will probably not be added. Hence the decision to use sun6i-a31-clock-reset here to avoid the changes to sun8i machine code. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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