- 14 5月, 2015 12 次提交
-
-
由 Rafał Miłecki 提交于
Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Rafał Miłecki 提交于
Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Florian Fainelli 提交于
Add a "brcm,bcm6328-timer" and "syscon-reboot" nodes to allow the generic syscon-reboot driver to reset a BCM63138 SoC. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Brian Norris 提交于
Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Ray Jui 提交于
Enable NAND support for Broadcom Cygnus SoC Signed-off-by: NRay Jui <rjui@broadcom.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Brian Norris 提交于
Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Tested-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Brian Norris 提交于
Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Rafał Miłecki 提交于
Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Felix Fietkau 提交于
Signed-off-by: NFelix Fietkau <nbd@openwrt.org> Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Felix Fietkau 提交于
Signed-off-by: NFelix Fietkau <nbd@openwrt.org> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Florian Fainelli 提交于
Update bcm63138.dtsi with the following: - enable-method for both CPU nodes - brcm,bcm63138-bootlut node - resets properties to point to the correct PMB controller to release the secondary CPU from reset Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
由 Florian Fainelli 提交于
Add the two BCM63138 PMB busses nodes found on this System-on-a-Chip as described in their corresponding binding document. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
-
- 13 5月, 2015 6 次提交
-
-
由 Dinh Nguyen 提交于
Add the dts node for the A9 SCU. Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
-
由 Linus Walleij 提交于
This adds the device tree data for the LIS331DL and the AK8974 magnetometer to the STUIB board device tree include file. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Linus Walleij 提交于
The ST sensors on the Ux500 boards were not utilizing the IRQs for data ready sample triggers. Enable this by assigning the right GPIO lines and interrupt lines (when the GPIO lines are used for IRQs) to the accelerometer, gyro and magnetometer sensors. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Linus Walleij 提交于
The magnetometer found on the Ux500 TVK and Snowball boards is a LSM303DLH not a LSM303DLM, small differences but still different. Put in the right compatible strings and things start working smoothly. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Linus Walleij 提交于
This registers all the CoreSight blocks on the DB8500 SoC: each core has a PTM (v1.0, r1p0-00rel0) connected, both connected to a funnel (DK-TM908-r0p1-00rel0) which in turn connects to a replicator (DM-TM909-r0p1-00rel0). The replicator has two outputs, port 0 to a TPIU interface and port 1 to an ETB (DK-TM907-r0p3-00rel0). The CoreSight blocks are all clocked by the APEATCLK from the PRCMU and their AHB interconnect is clocked from a separate clock called APETRACECLK. The SoC also has a CTI/CTM block which can be added later as we have upstream support in the CoreSight subsystem. Acked-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
-
由 Michael Niewöhner 提交于
The act8846 is the main pmic and system-power-controller on radxarock boards, so add the necessary property. Signed-off-by: NMichael Niewoehner <mniewoeh@stud.hs-offenburg.de> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
-
- 12 5月, 2015 12 次提交
-
-
由 Masahiro Yamada 提交于
Initial device trees for UniPhier SoCs: PH1-sLD3, PH1-LD4, PH1-Pro4, and PH1-sLD8. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Dinh Nguyen 提交于
Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
-
由 Vince Bridgers 提交于
Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga stmmac. These devicetree properties will be used to configure certain features of the stmmac on the socfpga. Signed-off-by: NVince Bridgers <vbridger@opensource.altera.com> Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
-
由 Vince Bridgers 提交于
Add multicast-filter-bins and perfect-filter-entries configuration properties to the socfpga devicetree for the Arria 10 socfpga. Signed-off-by: NVince Bridgers <vbridger@opensource.altera.com> Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
-
由 Dinh Nguyen 提交于
The CIU(Card Interface Unit) get its clock from the sdmmc_clk_divided clock which is used to clock the card. The sdmmc_clk_divided clock is the sdmmc_clk passed through a fixed divider of 4. This patch adds the sdmmc_clk_divided node and makes the sdmmc_clk it's parent. Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com> --- v2: renamed ciu_clk to sdmmc_clk_divided
-
由 Dinh Nguyen 提交于
Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
-
由 Dinh Nguyen 提交于
Arria10 devkit is using UART1 for the debug uart port. Remove unused aliases. Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add removal of unused aliases
-
由 Dinh Nguyen 提交于
Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
-
由 Dinh Nguyen 提交于
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
-
由 Walter Lozano 提交于
This patch adds the DTS bindings for the adxl34x digital accelerometer. Signed-off-by: NWalter Lozano <walter@vanguardiasur.com.ar> Acked-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
-
- 11 5月, 2015 4 次提交
-
-
由 Gaël PORTAY 提交于
The clock-frequency property became obsolete since the rework of the main clock driver in 3.16 (see commit 27cb1c20). It now get and uses the clock-frequency from the main_xtal node. Signed-off-by: NGaël PORTAY <g.portay@overkiz.com> Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
-
由 Gaël PORTAY 提交于
Add DT file for Kizbox 2 board. This board is based on Atmel's SAMA5D31 Cortex-A5 SoC. Signed-off-by: NGaël PORTAY <g.portay@overkiz.com> Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
-
由 Gaël PORTAY 提交于
Add DT file for Kizbox mini board. This board is based on Atmel's AT91SAM9G25 SoC. Signed-off-by: NGaël PORTAY <g.portay@overkiz.com> Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
-
由 Gaël PORTAY 提交于
Defines the pinctrl configurations for PWM0. Signed-off-by: NGaël PORTAY <g.portay@overkiz.com> Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
-
- 10 5月, 2015 4 次提交
-
-
由 Maxime Ripard 提交于
The pinctrl groups for SPI until now were also adding the chip selects in the SPI pinctrl group. This was causing a few issues, since a board was forced to use a random number of chipselects, even though it might use one of these chip selects for another pin. The number of chipselects defined was also not the same from one group to another because of different needs at the time these groups have been introduced, resulting in no clear view from the board DTS on what exactly is being muxed, which even might change in the future. Solve this by creating different pinctrl groups for the chipselects and the standard SPI pins (CLK, MOSI and MISO) so that we fix both issues. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Maxime Ripard 提交于
A few lines (probably copy pasted) have an indentation mixing tabs and spaces that triggers a checkpatch warning. Fix those, and while we're at it, fix the space-indented sections. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Maxime Ripard 提交于
A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Maxime Ripard 提交于
The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
- 09 5月, 2015 2 次提交
-
-
由 Javier Martinez Canillas 提交于
The Marvell mwifiex driver prevents the system to enter into a suspend state if the card power is not preserved during a suspend/resume cycle. So Suspend-to-RAM and Suspend-to-idle are failing on Exynos5250 Snow. Add the keep-power-in-suspend Power Management property to the SDIO/MMC node so the mwifiex suspend handler doesn't fail and the system is able to enter into a suspend state. Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NKukjin Kim <kgene@kernel.org>
-
由 Abhilash Kesavan 提交于
Remove the extra zero in the "cpu-crit-0" trip point for exynos5420 and exynos5440. Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: NKukjin Kim <kgene@kernel.org>
-