This patch adds all the resources for TV drivers and devices for Samsung
Exynos4 and S5PV210 platforms.
Signed-off-by: NTomasz Stanislawski <t.stanislaws@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
[m.szyprowski: squashed Exynos4 and S5PV210 patches and rewrote commit message]
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds two functions for gic interrupt handling.
1. Add interrupt handling of 4 cores.
2. Dynamically set gic bank offset according to the type of soc.
   Gic bank offset of EXYNOS4412 is 0x4000 while the offset of
   EXYNOS4210 and EXYNOS4212 is 0x8000.

This patch is necessary because EXYNOS4 socs cannot support
GIC register banking as described in commit aab74d3e.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds Samsung EXYNOS4412 SoC support.
The EXYNOS4412 integrates a ARM Cortex A9 quad-core.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

To support PPI in external GIC of EXYNOS4 SoCs,
gic_arch_extn.irq_eoi, irq_unmask and irq_mask are
fixed. This patch is necessary because external GIC of EXYNOS4
cannot support register banking.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch splits EXYNOS4 clock code to EXYNOS4 common,
EXYNOS4210 and EXYNOS4212 for supporting new EXYNOS4212
SoC with one kernel image. Of course, this patch adds
some clock codes for EXYNOS4212 SoC.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds Samsung EXYNOS4212 SoC support.
The EXYNOS4212 integrates a ARM Cortex A9 multi-core.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch uses samsung_rev() to support variable silicon revision of
EXYNOS4210 so that can support for EXYNOS4210 REV0, REV1.0 and REV1.1.

Note: Need to change timer setting on REV0.
Acked-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This is required to use SWRESET.
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Remove duplicated #include('s) in
  arch/arm/mach-exynos4/cpu.c
Signed-off-by: NHuang Weiyi <weiyi.huang@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds platform device s5p_device_fimd0 for EXYNOS4 FIMD0.
EXYNOS4 has two FIMDs(FIMD0, FIMD1). FIMD1 will be added later.
Some definitions used to enable EXYNOS4 FIMD0 are added.
Signed-off-by: NJonghun Han <jonghun.han@samsung.com>
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Signed-off-by: NMyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

External GIC cannot support PPI (Private Peripheral Interrupt) for
ARM private timers. Thus MCT should be selected as clock event timers
by default.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

For full support of power modes, this patch adds implementation
external GIC on EXYNOS4.

External GIC of Exynos4 cannot support register banking so
several interrupt related code for CPU1 should be different
from that of CPU0.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

To support external GIC needs to update mapping of interrupt number.
This patch modifies it for external GIC and accordingly removes
the unused code.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds external GIC io memory mapping
to support external GIC on EXYNOS4.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Set up a correct I2C bus controller variant name for Exynos4.
Without this change the I2C bus driver fails to acquire its
clocks.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Basically, other S3C SoCs and S5PC100 use 'S3C_VA_USB_HSPHY'
commonly. It should be changed to 'S3C_VA_USB_HSPHY' for common
usage and others. Now happens build error on S5PC100.

Cc: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

EXYNOS4 has 2 phys for usb host and usb device. This patch supports to
control usb host phy of EXYNOS4.
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Add support for fourth FIMC platform device definition and define
resources for FIMC modules on EXYNOS4 machines.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The MCT(Multi-Core Timer) is used for implementing kernel timers
for EXYNOS4210.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds EXYNOS4 CPU support files in mach-exynos4,
and basically they are moved from mach-s5pv310 so that it
can support Samsung's new CPU name, EXYNOS4.
The EXYNOS4 ingegrates a ARM Cortex A9 multi-core.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds support Power Domain for S5PV310 and S5PC210.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch is applied according to the commit 1a8e41cd
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).

Actually, S5PV310 has same cache controller(PL310).

Following is from Catalin Marinas' commit.

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Cc: <stable@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds DMC io mapping for access it and adds registers.
This is used in checking DRAM memory type.
Signed-off-by: NSunyoung Kang <sy0816.kang@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Every architecture using the GIC has a gic_cpu_base_addr pointer for
GIC 0 for their entry assembly code to use to decode the cause of the
current interrupt.  Move this into the common GIC code.
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide gic_init() which initializes the GIC distributor and current
CPU's GIC interface for the boot (or single) CPU.
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the
interrupt combiner. This patch limits the irqs which should be initialized
to support cascade interrupt.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds support SROMC for S5PV310 and S5PC210.
Signed-off-by: NDaein Moon <moon9124@samsung.com>
Signed-off-by: NSangbeom Kim <sbkim73@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds L2 cache initialization code in cpu.c of ARCH_S5PV310.
It includes TAG and Data latency, Prefetch, and Power configurations.
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds initial map for GPIO2 and GPIO3.
S5PV310/S5PC210 has separated GPIO1, GPIO2 and GPIO3.
Signed-off-by: NJongpill Lee <boyko.lee@samsung.com>
Signed-off-by: NSangbeom Kim <sbkim73@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds initialization HSMMC device information.
And HSMMC platform data like card detect, data bus width
and capability is configured.
Signed-off-by: NHyuk Lee <hyuk1.lee@samsung.com>
Signed-off-by: NJeongbae Seo <jeongbae.seo@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch fixes build error about GPIO address due to
conflict of commit 4d914705 and 19a2c065.

- commit 4d914705: Fix on GPIO base addresses
- commit 19a2c065: Moves initial map for merging S5P64X0
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch moves some initial maps from plat-s5p to machine,
so that can merge mach-s5p6440 and mach-s5p6450.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Following occurs on boot message without this patch.
    CPU1: processor failed to boot
    Brought up 1 CPUs
    SMP: Total of 1 processors activated...

This patch adds SYSRAM mapping for fixing Secondary CPU startup.
    CPU1: Booted secondary processor
    Brought up 2 CPUs
    SMP: Total of 2 processors activated...
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds CMU block for S5PV310/S5PC210 clock.
(CMU: Clock Management Unit)
Of course, changed current clock addresses for it together.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds Samsung S5PV310/S5PC210 CPU support.
The S5PV310/S5PC210 integrates a ARM Cortex A9 multi-core.
Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: NJongpill Lee <boyko.lee@samsung.com>
Signed-off-by: NJiseong Oh <jiseong.oh@samsung.com>
[kgene.kim@samsung.com: fix build errors]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>