The ACCES 104-IDI-48 family of PC/104 utility boards feature 48
individually optically isolated digital inputs. Enabled inputs feature
change-of-state detection capability; if change-of-state detection is
enabled, an interrupt is fired off if a change of input level
(low-to-high or high-to-low) is detected. Change-of-state IRQs are
enabled/disabled on 8-bit boundaries, for a total of six boundaries.

This driver provides GPIO and IRQ support for these 48 channels of
digital input. The base port address for the device may be configured
via the idi_48_base module parameter. The interrupt line number for the
device may be configured via the idi_48_irq module parameter.
Signed-off-by: NWilliam Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The ACCES 104-IDIO-16 family of PC/104 utility boards feature 16
optically isolated inputs and 16 optically isolated FET solid state
outputs. This driver provides GPIO support for these 32 channels of
digital I/O. Change-of-State detection interrupts are not supported.

GPIO 0-15 correspond to digital outputs 0-15, while GPIO 16-31
correspond to digital inputs 0-15. The base port address for the device
may be set via the idio_16_base module parameter.
Signed-off-by: NWilliam Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds a new GPIO driver for AMD Promontory chip.

This GPIO controller is enumerated by ACPI and the ACPI compliant
hardware ID is AMDF030.

Change history:

v2: 1. fix coding style
    2. registers renaming
v3: 1. change include file
    2. fix coding style
    3. remove module_init/exit, add module_platform_driver
    4. remove MODULE_ALIAS
v4: 1. change TOTAL_GPIO_PINS to PT_TOTAL_GPIO
    2. remove PCI dependency in Kconfig
    3. fix subject line
Signed-off-by: NYD Tseng <Yd_Tseng@asmedia.com.tw>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds support for the GPIOs found on the ITE super-I/O chips
IT87xx.
Signed-off-by: NDiego Elio Pettenò <flameeyes@flameeyes.eu>
Signed-off-by: NChristophe Vu-Brugier <cvubrugier@fastmail.fm>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Remove this driver now that Bjorn has introduced a pinctrl driver
for msm8660 and the dts files have been updated with the pinctrl
compatibles.

Cc: Andy Gross <agross@codeaurora.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

GPIO drivers should be in drivers/gpio
Signed-off-by: NAlban Bedel <albeu@free.fr>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10597/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add ZTE zx296702 GPIO controller support
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a GPIO driver for the General I/O block on Axis ETRAX FS SoCs.
Signed-off-by: NRabin Vincent <rabin@rab.in>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds support for the GPIO IP "UPG GIO" used on
Broadcom STB SoCs (BCM7XXX and some others). Uses
basic_mmio_gpio to instantiate a gpio_chip for each bank.
The driver assumes that it handles the base set of GPIOs
on the system and that it can start its numbering sequence
from 0, so any GPIO expanders used with it must dynamically
assign GPIO numbers after this driver has finished
registering its GPIOs.

Does not implement the interrupt-controller portion yet,
will be done in a future commit.

v2:
- change include to use <linux/gpio/driver.h> instead of
  <linux/gpio.h>
- get rid of unnecessary imask member in struct bank
- rename GPIO_PER_BANK -> MAX_GPIO_PER_BANK
- always have 32 GPIOs per bank and add 'width' member in
  struct bank to hold actual number of GPIOs in use
- mark of_match table as const
List-usage-fixed-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NGregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add GPIO controller driver for Netlogic XLP MIPS64 SOCs.

This driver is instantiated by device tree and supports interrupts
for GPIOs.
Signed-off-by: NKamlakant Patel <kamlakant.patel@broadcom.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Driver for the GPIO block found on NXP LPC18xx/43xx devices.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Move Loongson-2's GPIO driver to drivers/gpio and add Kconfig options.
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Reviewed-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This driver is orphaned now that mach-msm has been removed.
Delete it.

Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Adds a new driver for Altera soft GPIO IP. The driver is able to do
read/write and allows GPIO to be a interrupt controller.

Tested on Altera GHRD on interrupt handling and IO.

v10:
- Updated conflicting device tree parameters
- Removed unused headers
- Used macro instead of magic numbers for ngpio
- Code readability cleanup using ?: and temporal variables
- Removed leftover garbage and unnecessary function calls
- Checked bgpio_init but unusable because Altera GPIO may not
  be a multiple of 8 bits

v9:
- Removed duplicated initialization on set_type using temporals
  to improve code readability in calling generic_handle_irq
- Using ?: ternary to reduce code size

v8:
- Using for_each_set_bit
- Added const for struct definition
- Removed naggy pr_err
- Sort alpha header
- Remove unused macros
- Use fixed width data types instead of unsigned long
- Whitespace issue fixes
- Removed _relaxed function for better compatibility across different
  CPU
- Changed irq_create_mapping to platform_get_irq updated implementation
  to use gpiochip_irqchip_add
- Reserve interrupt-cells number 2 in device tree binding for future
  use
- Remove confusing sections on devicetree bindings
- Added tristate Kconfig help text

v7:
- Used dev_warn instead of pr_warn
- Clean up unnecesarry if else indentation

v6:
- Added irq_startup and irq_shutdown
- Changed bitwise clamping style
- Cleanup bitwise operation to improve readability change naming of
  mapped irqs from virq to mapped_irq

v5:
- Dispose irq_domain mapping correctly
- Update optional binding description in binding docs

v4:
- Added vendor prefix to devicetree binding for IP specific properties
  using MMIO GPIO helper library instead of manually map PIO to memory
- altera_gpio_chip inline struct documentation to kerneldoc
- Using dev_ print to print a better failure message

v2, v3:
- Do not reference NO_IRQ
- Updated irq_set_type to only allow the hardware configured irq type
Signed-off-by: NTien Hock Loh <thloh@altera.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Driver for Fujitsu MB86S7x SoCs that have a memory mapped GPIO controller.
Signed-off-by: NJassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NVincent Yang <Vincent.Yang@tw.fujitsu.com>
Signed-off-by: NTetsuya Nuriya <nuriya.tetsuya@jp.fujitsu.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Driver for standby GPIO controller of APM X-Gene SoCs on arm64.
Signed-off-by: NY Vo <yvo@apm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds GPIO and IRQ support for the Diolan DLN-2 GPIO module.

Information about the USB protocol interface can be found in the
Programmer's Reference Manual [1], see section 2.9 for the GPIO
module commands and responses.

[1] https://www.diolan.com/downloads/dln-api-manual.pdfSigned-off-by: NDaniel Baluta <daniel.baluta@intel.com>
Signed-off-by: NOctavian Purdila <octavian.purdila@intel.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NJohan Hovold <johan@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add a gpiolib and IRQ chip driver for Vybrid ARM SoC using the
Vybrid's GPIO and PORT module. The driver is instanced once per
each GPIO/PORT module pair and handles 32 GPIO's.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Acked-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds driver to support GPIO functionality for 74xx-compatible
ICs with MMIO access. Compatible models include:
 1 bit:   741G125 (Input), 741G74 (Output)
 2 bits:  742G125 (Input), 7474 (Output)
 4 bits:  74125 (Input), 74175 (Output)
 6 bits:  74365 (Input), 74174 (Output)
 8 bits:  74244 (Input), 74273 (Output)
 16 bits: 741624 (Input), 7416374 (Output)
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Reviewed-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add APM X-Gene SoC gpio controller driver.
Signed-off-by: NFeng Kan <fkan@apm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add support for GPIO controller used by Xilinx Zynq.

v3 changes:
 - Use linux/gpio/driver.h instead of linux/gpio.h
 - Make irq a local variable in probe

v2 changes:
 - convert to pm_runtime_force_(suspend|resume)
 - add pm_runtime_set_active in probe()
 - also (un)prepare clocks when they are dis-/enabled
 - add some missing calls to pm_runtime_get()
 - use pm_runtime_put() instead of sync variant
 - remove gpio chip in driver remove()
 - remove redundant type casts
 - directly use IO helpers
 - use BIT macro to set/clear bits
 - migrate to GPIOLIB_IRQCHIP
Signed-off-by: NHarini Katakam <harinik@xilinx.com>
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The old integer GPIO interface is, in effect, a privileged user of the
gpiod interface. Reflect this fact further by moving legacy GPIO support
into its own source file. This makes the code clearer and will allow us
to disable legacy GPIO support in the (far) future.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

sysfs support is currently entangled within the core GPIO support, while
it should relly just be a (privileged) user of the integer GPIO API.
This patch is a first step towards making the gpiolib code more readable
by splitting it into logical parts.

Move all sysfs support to their own source file, and share static
members of gpiolib that need to be in the private gpiolib.h file. In
the future we will want to put some of them back into gpiolib.c, but this
first patch let us at least identify them.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Devices based on Intel SoC products such as Baytrail have a Power
Management IC. In the PMIC there are subsystems for voltage regulation,
A/D conversion, GPIO and PWMs. The PMIC in Baytrail-T platform is
called Crystal Cove.

This patch adds support for the GPIO function in Crystal Cove.
Signed-off-by: NYang, Bin <bin.yang@intel.com>
Signed-off-by: NZhu, Lejun <lejun.zhu@linux.intel.com>
Reviewed-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: NAlexandre Courbot <acourbot@nvidia.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The ARCH_OMAP config option was used to built the GPIO OMAP
driver but this is not consistent with the rest of the GPIO
drivers that have their own Kconfig option.

Also, this make it harder to add dependencies or reverse
dependencies (i.e: select) since that would mean touching the
sub-arch config option.

So is better to add a boolean Kconfig option for this driver
that defaults to true if ARCH_OMAP is enabled.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

SYSCON driver was designed for using memory areas (registers)
that are used in several subsystems. There are systems (CPUs)
which use bits in one register for various purposes and thus
should be handled by various kernel subsystems. This driver
allows you to use the individual SYSCON bits as GPIOs.
ARM CLPS711X SYSFLG1 input lines has been added as first user
of this driver.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The tnetv107x platform is getting removed, so this driver won't
be needed any more.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-gpio@vger.kernel.org
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.

v12: - Add irq_startup/shutdown
     - do irq_create_mapping() in probe, irq_find_mapping() in to_irq()
     - Adjust mappings to show support for 1 gpio per port.
     - gpio-cells = <1>
v11: - Use NULL when checking existence of 'interrupts' property
     - Bindings descriptions cleanup
v10: - in documentation nr-gpio -> nr-gpios
v9:  - cleanup in dt bindings doc
     - use of_get_child_count()
v8:  - remove socfpga.dtsi changes
     - minor cleanup in devicetree documentation
v7:  - use irq_generic_chip
     - support one irq per gpio line or one irq for many
     - s/bank/port/ and other cleanup
v6:  - (atull) squash the set of patches
     - use linear irq domain
     - build fixes. Original driver was reviewed on v3.2.
     - Fix setting irq edge type for 'rising' and 'both'.
     - Support as a loadable module.
     - Use bgpio_chip's spinlock during register access.
     - Clean up register names to match spec
     - s/bank/port/ because register names use the word 'port'
     - s/nr-gpio/nr-gpios/
     - don't get/put the of_node
     - remove signoffs/acked-by's because of changes
     - other cleanup
v5:  - handle sparse bank population correctly
v3:  - depend on rather than select IRQ_DOMAIN
     - split IRQ support into a separate patch
v2:  - use Rob Herring's irqdomain in generic irq chip patches
     - use reg property to indicate bank index
     - support irqs on both edges based on LinusW's u300 driver
Signed-off-by: NJamie Iles <jamie@jamieiles.com>
Signed-off-by: NAlan Tull <atull@altera.com>
Reviewed-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This driver supports the GPIO controller found in LSI ZEVIO SoCs.
It has been successfully tested on a TI nspire CX calculator.
Signed-off-by: NFabian Vogt <fabian@ritter-vogt.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This is one of LP3943 MFD driver.
LP3943 is configurable as a GPIO expander, up to 16 GPIOs.

* Application note: how to configure LP3943 as a GPIO expander
  http://www.ti.com/lit/an/snva287a/snva287a.pdf

* Supported GPIO controller operations
  request, free, direction_input, direction_output, get and set

* GPIO direction register not supported
  LP3943 doesn't have the GPIO direction register. It only provides input and
  output status registers.
  So, private data for the direction should be handled manually.
  This variable is updated whenever the direction is changed and
  used in 'get' operation.

* Pin assignment
  A driver data, 'pin_used' is checked when a GPIO is requested.
  If the GPIO is already assigned, then returns as failure.
  If the GPIO is available, 'pin_used' is set.
  When the GPIO is not used anymore, then it is cleared.
  It is defined as unsigned long type for atomic bit operation APIs,
  but only LSB 16bits are used because LP3943 has 16 outputs.
Signed-off-by: NMilo Kim <milo.kim@ti.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The compatible to Davinci GPIO HW block is used by other TI SoCs, like
Keystone, where GPIO support is declared as optional.

Hence, introduce GPIO_DAVINCI Kconfig option which will allow to enable
Davinci GPIO driver for Keystone SoCs when needed. At same time, kept
Davinci GPIO driver enabled for Davinci SoCs by default.
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NLad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

This patch adds support for the GPIOs found on the SMSC "Super I/
SCH311x.

The chip detection and I/O functions are copied from sch311x_wdt.
Signed-off-by: NBruno Randolf <br1@einfach.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

GPIO32 is a standard optional extension to the Xtensa architecture
core that provides preconfigured output and input ports for intra
SoC signaling. The GPIO32 option is implemented as 32bit Tensilica
Instruction Extension (TIE) output state called EXPSTATE, and 32bit
input wire called IMPWIRE. This driver treats input and output
states as two distinct devices.

v3:
* Use BUG() in xtensa_impwire_set_value() to indicate that
  it should never be called (Linus Walleij)
v2:
* Address the comments of Linus Walleij:
  - Add a few comments
  - Expand commit log message
  - Use the BIT() macro for bit offsets
  - Rewrite CPENABLE handling as static inlines
  - Use device_initcall()
* Depend on !SMP for reason explained in the comments (Marc Gauthier)
* Use XCHAL_CP_ID_XTIOP to enable/disable GPIO32 only
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add GPIO driver for MOXA ART SoCs.
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The GPIO driver for the Abilis Systems TB10x series of SOCs based on ARC700
CPUs. It supports GPIO control and GPIO interrupt generation. This driver
works in conjunction with the TB10x pinctrl driver.
Signed-off-by: NSascha Leuenberger <sascha.leuenberger@abilis.com>
Signed-off-by: NChristian Ruppert <christian.ruppert@abilis.com>
Acked-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

gpio-langwell is a deprecated name. Despite the driver was made
initially for Langwell, it supports now other Intel Mid SoC's.

This patch does no change beside the file renaming with Kconfig/Makefile
update.
Signed-off-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Move the IOP GPIO driver to live with its siblings in the
GPIO subsystem.

Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Mikael Pettersson <mikpe@it.uu.se>
Tested-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the GPIO driver for the Broadcom bcm281xx family of mobile SoCs.
These GPIO controllers may contain up to 8 banks where each bank
includes 32 pins that can be driven high or low and act as an edge
sensitive interrupt.
Signed-off-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NChristian Daudt <csd@broadcom.com>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMatt Porter <matt.porter@linaro.org>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
[Added depends on OF_GPIO]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds support for the GPIOs found on the Fintek super-I/O
chips F71882FG and F71889F.

A super-I/O is a legacy I/O controller embedded on x86 motherboards. It
is used to connect the low-bandwidth devices. Among others functions the
F71882FG/F71889F provides: a parallel port, two serial ports, a keyboard
controller, an hardware monitoring controller and some GPIO pins.

Note that this super-I/Os are embedded on some Atom-based LaCie NASes.
The GPIOs are used to control the LEDs and the hard drive power.

Changes since v3:
- Use request_muxed_region to protect the I/O ports against concurrent
  accesses.

Changes since v2:
- Remove useless NULL setters for driver data.

Changes since v1:
- Enhance the commit message by describing what is a Super-I/O.
- Use self-explanatory names for the GPIO register macros.
- Add a comment to explain the platform device and driver registration.
- Fix gpio_get when GPIO is configured in input mode. I only had
  the hardware to check this mode recently...
Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
GPIO pins, this driver handles them all.  Configuring the pins as
interrupt sources is handled elsewhere (OCTEON's irq handling code).
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/5633/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>