1. 18 3月, 2009 7 次提交
    • S
      x86: fix broken irq migration logic while cleaning up multiple vectors · 68a8ca59
      Suresh Siddha 提交于
      Impact: fix spurious IRQs
      
      During irq migration, we send a low priority interrupt to the previous
      irq destination. This happens in non interrupt-remapping case after interrupt
      starts arriving at new destination and in interrupt-remapping case after
      modifying and flushing the interrupt-remapping table entry caches.
      
      This low priority irq cleanup handler can cleanup multiple vectors, as
      multiple irq's can be migrated at almost the same time. While
      there will be multiple invocations of irq cleanup handler (one cleanup
      IPI for each irq migration), first invocation of the cleanup handler
      can potentially cleanup more than one vector (as the first invocation can
      see the requests for more than vector cleanup). When we cleanup multiple
      vectors during the first invocation of the smp_irq_move_cleanup_interrupt(),
      other vectors that are to be cleanedup can still be pending in the local
      cpu's IRR (as smp_irq_move_cleanup_interrupt() runs with interrupts disabled).
      
      When we are ready to unhook a vector corresponding to an irq, check if that
      vector is registered in the local cpu's IRR. If so skip that cleanup and
      do a self IPI with the cleanup vector, so that we give a chance to
      service the pending vector interrupt and then cleanup that vector
      allocation once we execute the lowest priority handler.
      
      This fixes spurious interrupts seen when migrating multiple vectors
      at the same time.
      
      [ This is apparently possible even on conventional xapic, although to
        the best of our knowledge it has never been seen.  The stable
        maintainers may wish to consider this one for -stable. ]
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Eric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      Cc: stable@kernel.org
      68a8ca59
    • S
      x86, ioapic: Fix non atomic allocation with interrupts disabled · 05c3dc2c
      Suresh Siddha 提交于
      Impact: fix possible race
      
      save_mask_IO_APIC_setup() was using non atomic memory allocation while getting
      called with interrupts disabled. Fix this by splitting this into two different
      function. Allocation part save_IO_APIC_setup() now happens before
      disabling interrupts.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      05c3dc2c
    • S
      x86, x2apic: cleanup ifdef CONFIG_INTR_REMAP in io_apic code · 29b61be6
      Suresh Siddha 提交于
      Impact: cleanup
      
      Clean up #ifdefs and replace them with helper functions.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      29b61be6
    • S
      x86, x2apic: cleanup the IO-APIC level migration with interrupt-remapping · 0280f7c4
      Suresh Siddha 提交于
      Impact: simplification
      
      In the current code, for level triggered migration, we need to modify the
      io-apic RTE with the update vector information, along with modifying interrupt
      remapping table entry(IRTE) with vector and destination. This is to ensure that
      remote IRR bit inthe IOAPIC RTE gets cleared when the cpu does EOI.
      
      With this patch, for level triggered, we eliminate the io-apic RTE modification
      (with the updated vector information), by using a virtual vector (io-apic pin
      number).  Real vector that is used for interrupting cpu will be coming from
      the interrupt-remapping table entry. Trigger mode in the IRTE will always be
      edge, and the actual level or edge trigger will be setup in the IO-APIC RTE.
      So a level triggered interrupt will appear as an edge to the local apic
      cpu but still as level to the IO-APIC.
      
      With this change, level irq migration can be done by simply modifying
      the interrupt-remapping table entry with out changing the io-apic RTE.
      And as the interrupt appears as edge at the cpu, in addition to do the
      local apic EOI, we need to do IO-APIC directed EOI to clear the remote
      IRR bit in  the IO-APIC RTE.
      
      This simplies the irq migration in the presence of interrupt-remapping.
      Idea-by: NRajesh Sankaran <rajesh.sankaran@intel.com>
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Eric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      0280f7c4
    • S
      x86, x2apic: fix clear_local_APIC() in the presence of x2apic · cf6567fe
      Suresh Siddha 提交于
      Impact: cleanup, paranoia
      
      We were not clearing the local APIC in clear_local_APIC() in the
      presence of x2apic. Fix it.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      cf6567fe
    • S
      x86, x2apic: use virtual wire A mode in disable_IO_APIC() with interrupt-remapping · 7c6d9f97
      Suresh Siddha 提交于
      Impact: make kexec work with x2apic
      
      disable_IO_APIC() gets called during crashdump aswell, which configures the
      IO-APIC/LAPIC so that legacy interrupts can be delivered for the kexec'd kernel.
      
      In the presence of interrupt-remapping, we need to change the
      interrupt-remapping configuration aswell as modifying IO-APIC for virtual wire
      B mode.
      
      To keep things simple during the crash, use virtual wire A mode
      (for which we don't need to touch io-apic and interrupt-remapping tables).
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Eric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      7c6d9f97
    • S
      x86, x2apic: enable fault handling for intr-remapping · 9d783ba0
      Suresh Siddha 提交于
      Impact: interface augmentation (not yet used)
      
      Enable fault handling flow for intr-remapping aswell. Fault handling
      code now shared by both dma-remapping and intr-remapping.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      9d783ba0
  2. 02 3月, 2009 7 次提交
  3. 26 2月, 2009 4 次提交
  4. 25 2月, 2009 2 次提交
  5. 23 2月, 2009 2 次提交
    • I
      x86: refactor x86_quirks support · 8e6dafd6
      Ingo Molnar 提交于
      Impact: cleanup
      
      Make x86_quirks support more transparent. The highlevel
      methods are now named:
      
        extern void x86_quirk_pre_intr_init(void);
        extern void x86_quirk_intr_init(void);
      
        extern void x86_quirk_trap_init(void);
      
        extern void x86_quirk_pre_time_init(void);
        extern void x86_quirk_time_init(void);
      
      This makes it clear that if some platform extension has to
      do something here that it is considered ... weird, and is
      discouraged.
      
      Also remove arch_hooks.h and move it into setup.h (and other
      header files where appropriate).
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8e6dafd6
    • S
      x86: select x2apic ops in early apic probe only if x2apic mode is enabled · ef1f87aa
      Suresh Siddha 提交于
      If BIOS hands over the control to OS in legacy xapic mode, select
      legacy xapic related ops in the early apic probe and shift to x2apic
      ops later in the boot sequence, only after enabling x2apic mode.
      
      If BIOS hands over the control in x2apic mode, select x2apic related
      ops in the early apic probe.
      
      This fixes the early boot panic, where we were selecting x2apic ops,
      while the cpu is still in legacy xapic mode.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ef1f87aa
  6. 18 2月, 2009 3 次提交