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  1. 29 10月, 2014 2 次提交
    • M
      ASoC: Intel: Add dependency on DesignWare DMA controller · 63ae1fe7
      由 Mark Brown 提交于 
      We have calls into the controller so we need to ensure it is being
built.
Signed-off-by: NMark Brown <broonie@kernel.org>
      63ae1fe7
    • L
      ASoC: Intel: Make ADSP memory block allocation more generic · e9600bc1
      由 Liam Girdwood 提交于 
      Current block allocation is tied to block type and requestor type. Make the
allocation more generic by removing the struct module parameter and adding
a generic block allocator structure. Also pass in the list that the blocks
have to be added too in order to remove dependence on block requestor type.

ASoC: Intel: update scratch allocator to use generic block allocator

Update the scratch allocator to use the generic block allocator and calculate
total scratch buffer size.

ASoC: Intel: Add call to calculate offsets internally within the DSP.

A call to calculate internal DSP memory addresses used to allocate persistent
and scartch buffers.

ASoC: Intel: Add runtime module support.

Add support for runtime module objects that can be created for every FW
module that is parsed from the FW file. This gives a 1:N mapping between
the FW module from file and the runtime instantiations of that module.

We also need to make sure we remove every module and runtime module when
we unload the FW.

ASoC: Intel: Add DMA firmware loading support

Add support for DMA to load firmware modules to the DSP memory blocks.
Two DMA engines are supported, DesignWare and Intel MID.

ASoC: Intel: Add runtime module lookup API call

Add an API to allow quick lookup of runtime modules based on ID.

ASoC: Intel: Provide streams with dynamic module information

Remove the hard coded module paramaters and provide each module with
dynamically generated buffer information for scratch and persistent
buffers.
Signed-off-by: NLiam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      e9600bc1
  3. 28 10月, 2014 1 次提交
  5. 22 10月, 2014 5 次提交
  7. 20 10月, 2014 19 次提交
  9. 08 10月, 2014 6 次提交
  11. 07 10月, 2014 3 次提交
  13. 05 10月, 2014 1 次提交
  15. 04 10月, 2014 2 次提交
  17. 03 10月, 2014 1 次提交
    • D
      ASoC: tlv320aic3x: fix PLL D configuration · 31d9f8fa
      由 Dmitry Lavnikevich 提交于 
      Current caching implementation during regcache_sync() call bypasses
all register writes of values that are already known as default
(regmap reg_defaults). Same time in TLV320AIC3x codecs register 5
(AIC3X_PLL_PROGC_REG) write should be immediately followed by register
6 write (AIC3X_PLL_PROGD_REG) even if it was not changed. Otherwise
both registers will not be written.

This brings to issue that appears particulary in case of 44.1kHz
playback with 19.2MHz master clock. In this case AIC3X_PLL_PROGC_REG
is 0x6e while AIC3X_PLL_PROGD_REG is 0x0 (same as register
default). Thus AIC3X_PLL_PROGC_REG also remains not written and we get
wrong playback speed.

In this patch snd_soc_read() is used to get cached pll values and
snd_soc_write() (unlike regcache_sync() this function doesn't bypasses
hardware default values) to write them to registers.
Signed-off-by: NDmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
      31d9f8fa