1. 24 7月, 2007 2 次提交
    • R
      [POWERPC] 85xxCDS: Make sure restart resets the PCI bus. · 637e9e13
      Randy Vinson 提交于
      The current 85xxCDS restart code fails to reset the PCI bus which can
      lead to odd behavior after the restart. This patch uses the VIA Super
      Southbridge to perform a PCI reset which will reset the entire system.
      NOTE: Since the VIA chip is behind a PCI-to-PCI bridge which can be
      disabled with a switch setting, it may not be possible to perform the
      PCI bus reset. In this case, the code defaults to the previous restart
      mechanism.
      Signed-off-by: NRandy Vinson <rvinson@mvista.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      637e9e13
    • R
      [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line. · 3620fc1d
      Randy Vinson 提交于
      The Freescale MPC8555CDS and MPC8548CDS reference hardware has a legacy
      8259 interrupt controller pair contained within a VIA VT82C686B Southbridge
      on the main carrier board. The processor complex plugs into the carrier
      card using a PCI slot which limits the available interrupts to the
      INTA-INTD PCI interrupts. The output of the 8259 cascade pair is routed
      through a gate array and connected to the PCI INTA interrupt line.
      The normal interrupt chaining hook (set_irq_chained_handler) does
      not allow sharing of the chained interrupt which prevents the
      use of PCI INTA by PCI devices. This patch allows the 8259 cascade
      pair to share their interrupt line with PCI devices.
      
      NOTE: The addition of the .end routine for the MPIC is not strictly
      necessary for this patch. It's there so this code will run from within
      the threaded interrupt context used by the Real Time patch.
      Signed-off-by: NRandy Vinson <rvinson@mvista.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      3620fc1d
  2. 23 7月, 2007 3 次提交
  3. 10 7月, 2007 1 次提交
  4. 03 7月, 2007 1 次提交
  5. 29 6月, 2007 4 次提交
  6. 07 5月, 2007 1 次提交
  7. 13 4月, 2007 1 次提交
  8. 18 2月, 2007 1 次提交
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  10. 09 2月, 2007 1 次提交
  11. 07 10月, 2006 1 次提交
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  14. 23 8月, 2006 1 次提交
  15. 31 7月, 2006 1 次提交
  16. 05 4月, 2006 1 次提交