1. 08 4月, 2013 1 次提交
  2. 06 12月, 2011 1 次提交
  3. 21 9月, 2011 2 次提交
  4. 28 8月, 2011 1 次提交
    • R
      ARM: pm: CPU specific code should not overwrite r1 (v:p offset) · 6f354e5f
      Russell King 提交于
      r1 stores the v:p offset from the CPU invariant resume code, and is
      expected to be preserved by the CPU specific code.  Overwriting it is
      not a good idea.
      
      We've managed to get away with it on sa1100 platforms because most
      happen to have PHYS_OFFSET == PAGE_OFFSET, but that may not be the
      case depending on kernel configuration.  So fix this latent bug.
      
      This fixes xsc3 as well which was saving and restoring this register
      independently.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      6f354e5f
  5. 22 7月, 2011 1 次提交
  6. 07 7月, 2011 1 次提交
  7. 24 6月, 2011 1 次提交
  8. 02 4月, 2011 1 次提交
  9. 23 2月, 2011 1 次提交
  10. 08 10月, 2010 1 次提交
  11. 27 7月, 2010 1 次提交
    • R
      ARM: Factor out common code from cpu_proc_fin() · 9ca03a21
      Russell King 提交于
      All implementations of cpu_proc_fin() start by disabling interrupts
      and then flush caches.  Rather than have every processors proc_fin()
      implementation do this, move it out into generic code - and move the
      cache flush past setup_mm_for_reboot() (so it can benefit from having
      caches still enabled.)
      
      This allows cpu_proc_fin() to become independent of the L1/L2 cache
      types, and eventually move the L2 cache flushing into the L2 support
      code.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      9ca03a21
  12. 21 4月, 2010 1 次提交
    • R
      ARM: fix build error in arch/arm/kernel/process.c · 4260415f
      Russell King 提交于
      /tmp/ccJ3ssZW.s: Assembler messages:
      /tmp/ccJ3ssZW.s:1952: Error: can't resolve `.text' {.text section} - `.LFB1077'
      
      This is caused because:
      
      	.section .data
      	.section .text
      	.section .text
      	.previous
      
      does not return us to the .text section, but the .data section; this
      makes use of .previous dangerous if the ordering of previous sections
      is not known.
      
      Fix up the other users of .previous; .pushsection and .popsection are
      a safer pairing to use than .section and .previous.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      4260415f
  13. 03 10月, 2009 1 次提交
  14. 01 10月, 2008 2 次提交
  15. 07 8月, 2008 2 次提交
  16. 24 4月, 2008 1 次提交
  17. 19 4月, 2008 1 次提交
  18. 13 12月, 2006 1 次提交
    • R
      [ARM] Unuse another Linux PTE bit · ad1ae2fe
      Russell King 提交于
      L_PTE_ASID is not really required to be stored in every PTE, since we
      can identify it via the address passed to set_pte_at().  So, create
      set_pte_ext() which takes the address of the PTE to set, the Linux
      PTE value, and the additional CPU PTE bits which aren't encoded in
      the Linux PTE value.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      ad1ae2fe
  19. 30 11月, 2006 1 次提交
  20. 03 7月, 2006 1 次提交
  21. 30 6月, 2006 1 次提交
    • R
      [ARM] Set bit 4 on section mappings correctly depending on CPU · 8799ee9f
      Russell King 提交于
      On some CPUs, bit 4 of section mappings means "update the
      cache when written to".  On others, this bit is required to
      be one, and others it's required to be zero.  Finally, on
      ARMv6 and above, setting it turns on "no execute" and prevents
      speculative prefetches.
      
      With all these combinations, no one value fits all CPUs, so we
      have to pick a value depending on the CPU type, and the area
      we're mapping.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      8799ee9f
  22. 29 6月, 2006 2 次提交
    • R
      [ARM] nommu: provide a way for correct control register value selection · 22b19086
      Russell King 提交于
      Most MMU-based CPUs have a restriction on the setting of the data cache
      enable and mmu enable bits in the control register, whereby if the data
      cache is enabled, the MMU must also be enabled.  Enabling the data
      cache without the MMU is an invalid combination.
      
      However, there are CPUs where the data cache can be enabled without the
      MMU.
      
      In order to allow these CPUs to take advantage of that, provide a
      method whereby each proc-*.S file defines the control regsiter value
      for use with nommu (with the MMU disabled.)  Later on, when we add
      support for enabling the MMU on these devices, we can adjust the
      "crval" macro to also enable the data cache for nommu.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      22b19086
    • H
      [ARM] nommu: Initial uCLinux support for MMU-based CPUs · d090ddda
      Hyok S. Choi 提交于
      In noMMU mode, various of functions which are defined in mm/proc-*.S
      is not valid or needed to be avoided. i.g. switch_mm is not needed,
      just returns and this makes the I & D caches are valid which shows
      great improvement of performance including task switching and IPC.
      Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      d090ddda
  23. 07 4月, 2006 1 次提交
  24. 22 3月, 2006 1 次提交
  25. 20 9月, 2005 1 次提交
  26. 10 9月, 2005 1 次提交
  27. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4