- 15 5月, 2012 15 次提交
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由 Stephen Warren 提交于
It's already specified in skeleton.dtsi, included via tegra20.dtsi. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Place each reg "entry" on its own line, and wrap the whole list in <> rather than each individual entry. The convention chosen here is slightly arbitrary, but is not consistent throughout all Tegra files. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Ensure that all Tegraa GPIO specifiers contain a comment indicating which GPIO name the number refers to. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Consistently don't place a space after < or before >. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Cardhu's eMMC controller is on sdhci@78000600, not sdhci@78000400. Fix the typo. This roughly doubles the IO performance, since the support-8bit property actually takes effect. Signed-off-by: NStephen Warren <swarren@nvidia.com> Cc: stable@kernel.org # v3.4
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由 Laxman Dewangan 提交于
Add device info for the core regulator tps62360 in tegra-cardhu dts file. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: fixed node name to reflect actual device type] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 hdoyu@nvidia.com 提交于
Add a node for the Tegra30 SMMU Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 hdoyu@nvidia.com 提交于
Add a node for the Tegra20 GART Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 hdoyu@nvidia.com 提交于
Add Tegra MC(Memory Controller) nodes for tegra30.dtsi. Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 hdoyu@nvidia.com 提交于
Add Tegra MC(Memory Controller) nodes for tegra20.dtsi. Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi DOYU 提交于
Add AHB entry for tegra20/30. Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
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由 Stephen Warren 提交于
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- 04 5月, 2012 7 次提交
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由 Stephen Warren 提交于
* Add node for the audio codec * Enable Tegra's I2S1 controller and DAS * Add node for top-level sound complex Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
This is the micro-SD card slot. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
According to the device's datasheet, it can support an interrupt too. However, the existing board file doesn't specify an interrupt, and I don't have the schematics, so I can't add an interrupts property. The current Linux driver doesn't support anyway. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Olof Johansson 提交于
Add the known i2c devices on seaboard to the i2c table. Also rename the temperature sensor device node, and mark it as a nct1008 instead of an adt7461 (which it is -- the chips are compatible though). Signed-off-by: NOlof Johansson <olof@lixom.net> [swarren: Removed isl29018 from patch; it's already there now. Fixed interrupts properties now that Tegra GPIO is an interrupt controller. Moved smart-battery to the correct I2C bus.] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
The I2C2 controller can be routed to either pingroup DDC or PTA. Seaboard actually uses this as an I2C bus mux, and devices are connected to both pingroups. This change statically assigns the I2C2 controller to pingroup PTA, so that on-board devices can be accessed. The DDC pingroup is used for EDID/DDC accesses which are not yet required, given the absence of any Tegra graphics support. I2C muxing will be supported later. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
This I2C bus is used for EDID/DDC reads and other "slow" I2C devices. This requires a 100KHz SCL (clock) rate. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Add the device info for ALS and proximity sensor for tegra boards cardhu, ventana and seaboard. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: s/PZ02/PZ2/ in .dts files, s/seabridge/seaboard/ in commit description] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 26 4月, 2012 14 次提交
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由 Stephen Warren 提交于
Ensure that the USB ULPI signals are not tri-stated, and have no pull- up or pull-down. Ensure that the pingroup hosting the USB ULPI reset signal (GPIO PV0 or PV1 depending on the board, so UAC) is not tri-stated, and has no pull- up or pull-down. This change appears larger than it is due to the grouping and sorting of the pin configuration data. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
ULPI PHYs have a reset signal, and different boards use a different GPIO for this task. Add a property to device tree to represent this. I'm not sure if adding this property to the EHCI controller node is entirely correct; perhaps eventually we should have explicit separate nodes for the various PHYs. However, we don't have that right now, so this binding seems like a reasonable choice. Cc: <devicetree-discuss@lists.ozlabs.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: <linux-usb@vger.kernel.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Not all boards use GPIO_PV0 as the ULPI PHY reset signal. Instead of hard-coding this GPIO into devices.c, make the board files set it explicitly. This will allow the PHY code to differentiate between set and unset values, and hence know when to read the value from device tree. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin to provide a reference clock to a ULPI USB PHY. This reference clock must run at 24MHz, and the cdev2 output has no additional dividers. Remove board-paz00.c's now-duplicate initialization of this clock. Reported-by: NMarc Dietrich <marvin24@gmx.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the rate of hclk. Since pclk is derived from that, and only has integer dividers, the pclk rate needs to change in the same fashion, from 54MHz to 60MHz. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
pll_p_out4 needs to be used for other purposes. Reparent sclk so that it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this is the lowest precise rate that can be achieved by dividing the pll_c rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909..., 600/6=100). Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Allen Martin 提交于
pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[] so that it's possible to explicitly initialize the PLL. NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output, whereas the ChromeOS kernel contains entries for 600MHz output. I chose to upstream the ChromeOS values for now, since the 600MHz rate appears to match the default rate of this PLL when the HW boots, and it's not clear to me why 522 or 598MHz are more useful. Signed-off-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NOlof Johansson <olofj@chromium.org> Signed-off-by: NStephen Warren <swarren@nvidia.com> [swarren: wrote commit description]
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由 Stephen Warren 提交于
Add WM8903 codec nodes, and top-level sound complex node for basic analog audio over headset jack and internal speakers. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Add nodes for the Tegra30 AHUB and I2S controllers. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Both the Tegra30 I2S and AHUB modules used clocks, and hence currently require AUXDATA in order to get specific device names so that clock lookups work. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Set up the audio clock tree for Tegra30 in an equivalent fashion to the existing setup for Tegra20. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Peter De Schrijver 提交于
pll_a uses pll_p_out1 as its parent. Therefore this clock needs to be initialized to make sure pll_a has a known input clock. Failure to do so will cause the system to crash early in the bootup. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
The Tegra30 AHUB driver must call tegra_periph_reset_deassert() for all devices on the AHUB's configlink bus. The AHUB driver must be able to call clk_get_sys() to retrieve the clock parameter for this function. Add the necessary clock aliases to allow this. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
Print an explicit error message in various failure cases to allow easier diagnosis. WARN_ON() some internal failures that users/clients shouldn't be able to trigger. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 19 4月, 2012 4 次提交
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由 Stephen Warren 提交于
* Only provide debugfs-relates ops when CONFIG_DEBUG_FS is enabled. * Implement pin_config_group_dbg_show op. * Implement pin_config_config_dbg_show op. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Stephen Warren 提交于
Rather than having a single tegra-pinctrl driver that determines whether it's running on Tegra20 or Tegra30, instead have separate drivers for each that call into utility functions to implement the majority of the driver. This change is based on review feedback of the SPEAr pinctrl driver, which had originally copied to Tegra driver structure. This requires that the two drivers have unique names. Update a couple spots in arch/arm/mach-tegra for the name change. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Stephen Warren 提交于
This adds a complete pinmux configuration to all Tegra20 device tree files. This allows removal of board-dt-tegra20.c's use of the pinmux board files, and the special device tree handling in board-pinmux.c. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Stephen Warren 提交于
This adds a minimal pinmux configuration to the Tegra Cardhu device tree. Initially, just the built-in eMMC and SD card slot are configured. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net
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