ARM: tegra: change pll_p_out4's rate to 24MHz
pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin to provide a reference clock to a ULPI USB PHY. This reference clock must run at 24MHz, and the cdev2 output has no additional dividers. Remove board-paz00.c's now-duplicate initialization of this clock. Reported-by: NMarc Dietrich <marvin24@gmx.de> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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