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  1. 23 10月, 2010 1 次提交
    • A
      USB: add USB EHCI support for MPC5121 SoC · 230f7ede
      由 Anatolij Gustschin 提交于 
      Extends FSL EHCI platform driver glue layer to support
MPC5121 USB controllers. MPC5121 Rev 2.0 silicon EHCI
registers are in big endian format. The appropriate flags
are set using the information in the platform data structure.
MPC83xx system interface registers are not available on
MPC512x, so the access to these registers is isolated in
MPC512x case. Furthermore the USB controller clocks
must be enabled before 512x register accesses which is
done by providing platform specific init callback.

The MPC512x internal USB PHY doesn't provide supply voltage.
For boards using different power switches allow specifying
DRVVBUS and PWR_FAULT signal polarity of the MPC5121 internal
PHY using "fsl,invert-drvvbus" and "fsl,invert-pwr-fault"
properties in the device tree USB nodes. Adds documentation
for this new device tree bindings.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      230f7ede
  3. 24 11月, 2009 1 次提交
  5. 12 11月, 2009 2 次提交
  7. 19 6月, 2009 1 次提交
  9. 17 6月, 2009 1 次提交
  11. 16 4月, 2009 1 次提交
    • A
      powerpc/5200: Bring the legacy fsl_spi_platform_data hooks back · 41240102
      由 Anton Vorontsov 提交于 
      In commit 364fdbc0 ("spi_mpc83xx:
rework chip selects handling"), I merged activate_cs and deactivate_cs
hooks into cs_control, but I overlooked that mpc52xx_psc_spi driver
is using these hooks too. And that resulted in the following build
failure:

CC      drivers/spi/mpc52xx_psc_spi.o
drivers/spi/mpc52xx_psc_spi.c: In function 'mpc52xx_psc_spi_do_probe':
drivers/spi/mpc52xx_psc_spi.c:398: error: 'struct fsl_spi_platform_data'
has no member named 'activate_cs'
drivers/spi/mpc52xx_psc_spi.c:399: error: 'struct fsl_spi_platform_data'
has no member named 'deactivate_cs'
make[2]: *** [drivers/spi/mpc52xx_psc_spi.o] Error 1

This patch simply adds the legacy hooks back for 2.6.30, and for
2.6.31 we'll convert the driver to ->cs_control.
Reported-by: NSubrata Modak <subrata@linux.vnet.ibm.com>
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      41240102
  13. 08 4月, 2009 1 次提交
  15. 01 4月, 2009 2 次提交
  17. 31 3月, 2009 1 次提交
  19. 17 12月, 2008 1 次提交
  21. 31 10月, 2008 1 次提交
    • T
      gianfar: Fix race in TBI/SerDes configuration · c132419e
      由 Trent Piepho 提交于 
      The init_phy() function attaches to the PHY, then configures the
SerDes<->TBI link (in SGMII mode).  The TBI is on the MDIO bus with the PHY
(sort of) and is accessed via the gianfar's MDIO registers, using the
functions gfar_local_mdio_read/write(), which don't do any locking.

The previously attached PHY will start a work-queue on a timer, and
probably an irq handler as well, which will talk to the PHY and thus use
the MDIO bus.  This uses phy_read/write(), which have locking, but not
against the gfar_local_mdio versions.

The result is that PHY code will try to use the MDIO bus at the same time
as the SerDes setup code, corrupting the transfers.

Setting up the SerDes before attaching to the PHY will insure that there is
no race between the SerDes code and *our* PHY, but doesn't fix everything.
Typically the PHYs for all gianfar devices are on the same MDIO bus, which
is associated with the first gianfar device.  This means that the first
gianfar's SerDes code could corrupt the MDIO transfers for a different
gianfar's PHY.

The lock used by phy_read/write() is contained in the mii_bus structure,
which is pointed to by the PHY.  This is difficult to access from the
gianfar drivers, as there is no link between a gianfar device and the
mii_bus which shares the same MDIO registers.  As far as the device layer
and drivers are concerned they are two unrelated devices (which happen to
share registers).

Generally all gianfar devices' PHYs will be on the bus associated with the
first gianfar.  But this might not be the case, so simply locking the
gianfar's PHY's mii bus might not lock the mii bus that the SerDes setup
code is going to use.

We solve this by having the code that creates the gianfar platform device
look in the device tree for an mdio device that shares the gianfar's
registers.  If one is found the ID of its platform device is saved in the
gianfar's platform data.

A new function in the gianfar mii code, gfar_get_miibus(), can use the bus
ID to search through the platform devices for a gianfar_mdio device with
the right ID.  The platform device's driver data is the mii_bus structure,
which the SerDes setup code can use to lock the current bus.
Signed-off-by: NTrent Piepho <tpiepho@freescale.com>
CC: Andy Fleming <afleming@freescale.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
      c132419e
  23. 17 7月, 2008 2 次提交
  25. 30 4月, 2008 1 次提交
  27. 17 4月, 2008 1 次提交
  29. 19 7月, 2007 1 次提交
    • A
      Fix RGMII-ID handling in gianfar · 7132ab7f
      由 Andy Fleming 提交于 
      The TSEC/eTSEC can detect the interface to the PHY automatically,
but it isn't able to detect whether the RGMII connection needs internal
delay.  So we need to detect that change in the device tree, propagate
it to the platform data, and then check it if we're in RGMII.  This fixes
a bug on the 8641D HPCN board where the Vitesse PHY doesn't use the delay
for RGMII.
Signed-off-by: NAndy Fleming <afleming@freescale.com>
      7132ab7f
  31. 18 7月, 2007 1 次提交
  33. 10 7月, 2007 1 次提交
  35. 28 4月, 2007 1 次提交
    • K
      ucc_geth: migrate ucc_geth to phylib · 728de4c9
      由 Kim Phillips 提交于 
      migrate ucc_geth to use the common phylib code.

There are several side effects from doing this:

o deprecate 'interface' property specification present
  in some old device tree source files in
  favour of a split 'max-speed' and 'interface-type'
  description to appropriately match definitions
  in include/linux/phy.h.  Note that 'interface' property
  is still honoured if max-speed or interface-type
  are not present (backward compatible).
o compile-time CONFIG_UGETH_HAS_GIGA is eliminated
  in favour of probe time speed derivation logic.
o adjust_link streamlined to only operate on maccfg2
  and upsmr.r10m, instead of reapplying static initial
  values related to the interface-type.
o Addition of UEC MDIO of_platform driver requires
  platform code add 'mdio' type to id list
  prior to calling of_platform_bus_probe (separate patch).
o ucc_struct_init introduced to reduce ucc_geth_startup
  complexity.
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      728de4c9
  37. 11 12月, 2006 1 次提交
  39. 04 10月, 2006 1 次提交
    • L
      [POWERPC] Add QUICC Engine (QE) infrastructure · 98658538
      由 Li Yang 提交于 
      Add QUICC Engine (QE) configuration, header files, and
QE management and library code that are used by QE devices
drivers.

Includes Leo's modifications up to, and including, the
platform_device to of_device adaptation:

"The series of patches add generic QE infrastructure called
qe_lib, and MPC8360EMDS board support.  Qe_lib is used by
QE device drivers such as ucc_geth driver.

This version updates QE interrupt controller to use new irq
mapping mechanism, addresses all the comments received with
last submission and includes some style fixes.

v2: Change to use device tree for BCSR and MURAM;
Remove I/O port interrupt handling code as it is not generic
enough.

v3: Address comments from Kumar;  Update definition of several
device tree nodes;  Copyright style change."

In addition, the following changes have been made:

o removed typedefs
o uint -> u32 conversions
o removed following defines:
  QE_SIZEOF_BD, BD_BUFFER_ARG, BD_BUFFER_CLEAR, BD_BUFFER,
  BD_STATUS_AND_LENGTH_SET, BD_STATUS_AND_LENGTH, and BD_BUFFER_SET
  because they hid sizeof/in_be32/out_be32 operations from the reader.
o fixed qe_snums_init() serial num assignment to use a const array
o made CONFIG_UCC_FAST select UCC_SLOW
o reduced NR_QE_IC_INTS from 128 to 64
o remove _IO_BASE, etc. defines (not used)
o removed irrelevant comments, added others to resemble removed BD_ defines
o realigned struct definitions in headers
o various other style fixes including things like pinMask -> pin_mask
o fixed a ton of whitespace issues
o marked ioregs as __be32/__be16
o removed platform_device code and redundant get_qe_base()
o removed redundant comments
o added cpu_relax() to qe_reset
o uncasted all get_property() assignments
o eliminated unneeded casts
o eliminated immrbar_phys_to_virt (not used)
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NShlomi Gridish <gridish@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      98658538
  41. 22 5月, 2006 1 次提交
  43. 21 3月, 2006 1 次提交
    • R
      [PATCH] USB: EHCI for Freescale 83xx · 80cb9aee
      由 Randy Vinson 提交于 
      Adding a Host Mode USB driver for the Freescale 83xx.

This driver supports both the Dual-Role (DR) controller and the
Multi-Port-Host (MPH) controller present in the Freescale MPC8349. It has
been tested with the MPC8349CDS reference system. This driver depends on
platform support code for setting up the pins on the device package in a
manner appropriate for the board in use. Note that this patch requires
selecting the EHCI controller option under the USB Host menu.
Signed-off-by: NRandy Vinson <rvinson@mvista.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      80cb9aee
  45. 13 1月, 2006 2 次提交
  47. 14 11月, 2005 1 次提交
  49. 29 10月, 2005 1 次提交
  51. 22 6月, 2005 1 次提交
  53. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      由 Linus Torvalds 提交于 
      Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
      1da177e4