1. 11 6月, 2014 1 次提交
  2. 14 12月, 2013 2 次提交
  3. 31 5月, 2013 1 次提交
  4. 04 1月, 2013 2 次提交
  5. 22 7月, 2011 1 次提交
    • H
      PCI: PCIe AER: add aer_recover_queue · 0918472c
      Huang Ying 提交于
      In addition to native PCIe AER, now APEI (ACPI Platform Error
      Interface) GHES (Generic Hardware Error Source) can be used to report
      PCIe AER errors too.  To add support to APEI GHES PCIe AER recovery,
      aer_recover_queue is added to export the recovery function in native
      PCIe AER driver.
      
      Recoverable PCIe AER errors are reported via NMI in APEI GHES.  Then
      APEI GHES uses irq_work to delay the error processing into an IRQ
      handler.  But PCIe AER recovery can be very time-consuming, so
      aer_recover_queue, which can be used in IRQ handler, delays the real
      recovery action into the process context, that is, work queue.
      Signed-off-by: NHuang Ying <ying.huang@intel.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      0918472c
  6. 22 3月, 2011 2 次提交
    • H
      ACPI, APEI, Add PCIe AER error information printing support · c413d768
      Huang Ying 提交于
      The AER error information printing support is implemented in
      drivers/pci/pcie/aer/aer_print.c.  So some string constants, functions
      and macros definitions can be re-used without being exported.
      
      The original PCIe AER error information printing function is not
      re-used directly because the overall format is quite different.  And
      changing the original printing format may make some original users'
      scripts broken.
      Signed-off-by: NHuang Ying <ying.huang@intel.com>
      CC: Jesse Barnes <jbarnes@virtuousgeek.org>
      CC: Zhang Yanmin <yanmin.zhang@intel.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      c413d768
    • H
      PCIe, AER, use pre-generated prefix in error information printing · b64a4414
      Huang Ying 提交于
      When printing PCIe AER error information, each line is prefixed with
      PCIe device and driver information.  In original implementation, the
      prefix is generated when each line is printed.  In fact, all lines
      share the same prefix.  So this patch pre-generated the prefix, and
      use that one when each line is printed.
      
      In addition to common prefix can be pre-generated, the trailing white
      spaces in string constants and NULLs in char * array constants can be
      removed too.  These can reduce the object file size further.
      
      The size of object file before and after changing is as follow:
      
                 text    data     bss     dec
      before:    3038       0       0    3038
      after:     2118       0       0    2118
      Signed-off-by: NHuang Ying <ying.huang@intel.com>
      CC: Jesse Barnes <jbarnes@virtuousgeek.org>
      CC: Zhang Yanmin <yanmin.zhang@intel.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      b64a4414
  7. 17 12月, 2009 1 次提交
  8. 10 9月, 2009 9 次提交
    • H
      PCI: pcie, aer: change error print format · 79e4b89b
      Hidetoshi Seto 提交于
      Use dev_printk like format.
      
      Sample (real machine + dummy error injected by aer-inject):
      
      - Before:
      
      +------ PCI-Express Device Error ------+
      Error Severity          : Corrected
      PCIE Bus Error type     : Data Link Layer
      Bad TLP                 :
      Receiver ID             : 2800
      VendorID=8086h, DeviceID=1096h, Bus=28h, Device=00h, Function=00h
      +------ PCI-Express Device Error ------+
      Error Severity          : Corrected
      PCIE Bus Error type     : Data Link Layer
      Bad TLP                 :
      Bad DLLP                :
      Receiver ID             : 2801
      VendorID=8086h, DeviceID=1096h, Bus=28h, Device=00h, Function=01h
      Error of this Agent(2801) is reported first
      
      - After:
      
      pcieport-driver 0000:00:02.0: AER: Multiple Corrected error received: id=2801
      e1000e 0000:28:00.0: PCIE Bus Error: severity=Corrected, type=Data Link Layer, id=2800(Receiver ID)
      e1000e 0000:28:00.0:   device [8086:1096] error status/mask=00000040/00000000
      e1000e 0000:28:00.0:    [ 6] Bad TLP
      e1000e 0000:28:00.1: PCIE Bus Error: severity=Corrected, type=Data Link Layer, id=2801(Receiver ID)
      e1000e 0000:28:00.1:   device [8086:1096] error status/mask=000000c0/00000000
      e1000e 0000:28:00.1:    [ 6] Bad TLP
      e1000e 0000:28:00.1:    [ 7] Bad DLLP
      e1000e 0000:28:00.1:   Error of this Agent(2801) is reported first
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      79e4b89b
    • H
      PCI: pcie, aer: flags to bits · 273024de
      Hidetoshi Seto 提交于
      Compact struct and codes.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      273024de
    • H
      PCI: pcie, aer: report multiple/first error on a device · e7a0d92b
      Hidetoshi Seto 提交于
      Multiple bits might be set in the Uncorrectable Error Status
      register.  But aer_print_error_source() only report a error of
      the lowest bit set in the error status register.
      
      So print strings for all bits unmasked and set.
      
      And check First Error Pointer to mark the error occured first.
      This FEP is not valid when the corresponing bit of the Uncorrectable
      Error Status register is not set, or unimplemented or undefined.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      e7a0d92b
    • H
      PCI: pcie, aer: refer mask state in mask register properly · 0d90c3ac
      Hidetoshi Seto 提交于
      ERR_{,UN}CORRECTABLE_ERROR_MASK are set of error bits which linux know,
      set of PCI_ERR_COR_* and PCI_ERR_UNC_* defined in linux/pci_regs.h.
      This masks make aerdrv not to report errors of unknown bit, while aerdrv
      have ability to report such undefined errors as "Unknown Error Bit %2d".
      
      OTOH aerdrv_errprint does not have any check of setting in mask register.
      So it could report masked wrong error by finding bit in status without
      knowing that the bit is masked in the mask register.
      
      This patch changes aerdrv to use mask state in mask register propely
      instead of defined/hardcoded ERR_{,UN}CORRECTABLE_ERROR_MASK.
      This change prevents aerdrv from reporting masked error, and also enable
      reporting unknown errors.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Reviewed-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      0d90c3ac
    • H
      PCI: pcie, aer: remove spinlock in aerdrv_errprint.c · 24dbb7be
      Hidetoshi Seto 提交于
      The static buffer errmsg_buff[] is used only for building error
      message in fixed format, and is protected by a spinlock.
      
      This patch removes this buffer and the spinlock.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Reviewed-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      24dbb7be
    • H
      PCI: pcie, aer: fix report of multiple errors · 0d465f23
      Hidetoshi Seto 提交于
      The flag AER_MULTI_ERROR_VALID_FLAG in info->flag does mean that the
      root port receives multiple error messages.  Error messages can be
      posted from different devices, so it does not mean that each reported
      device has multiple errors.
      
      If there are multiple error devices and the root port has valid error
      source ID, it would be nice to report which device is the error source
      reported first.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      0d465f23
    • H
      PCI: pcie, aer: rework MASK macros in aerdrv_errprint.c · f1585756
      Hidetoshi Seto 提交于
      Definitions of MASK macros in aerdrv_errprint.c are tricky and unsafe.
      
      For example, AER_AGENT_TRANSMITTER_MASK(_sev, _stat) does work like:
        static inline func(int _sev, int _stat)
        {
          if (_sev == AER_CORRECTABLE)
            return (_stat & (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER));
          else
            return (_stat & PCI_ERR_COR_REP_ROLL);
        }
      In case of else path here, for uncorrectable errors, testing bits in
      _stat by PCI_ERR_COR_* does not make sense because _stat should have only
      PCI_ERR_UNC_* bits originated in uncorrectable error status register.
      But at this time this is safe because uncorrectable error using bit
      position same to PCI_ERR_COR_REP_ROLL(= bit position 8) is not defined.
      Likewise, AER_AGENT_COMPLETER_MASK is always PCI_ERR_UNC_COMP_ABORT but
      it works because bit 15 of correctable error status is not defined.
      
      It means that these MASK macros will turn to be wrong once if new error
      is defined. (In fact, bit 15 of correctable is now defined in PCIe 2.1)
      
      This patch changes these MASK macros to be more strict, not to return
      PCI_ERR_COR_* bits for uncorrectable error status and vise versa.
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Reviewed-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      f1585756
    • H
      PCI: pcie, aer: AER_PR for printing in aerdrv_errprint.c · bd8fedd0
      Hidetoshi Seto 提交于
      Add workaround macro to reduce the number of checkpatch warning:
       WARNING: printk() should include KERN_ facility level
      
      Before:
        total: 0 errors, 10 warnings, 247 lines checked
      After:
        total: 0 errors, 1 warnings, 243 lines checked
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      bd8fedd0
    • H
      PCI: pcie, aer: checkpatch style cleanup in pcie/aer/* · c9a91883
      Hidetoshi Seto 提交于
      Before:
       drivers/pci/pcie/aer/aer_inject.c
        total: 4 errors, 4 warnings, 473 lines checked
       drivers/pci/pcie/aer/aerdrv.c
        total: 5 errors, 2 warnings, 333 lines checked
       drivers/pci/pcie/aer/aerdrv.h
        total: 1 errors, 0 warnings, 139 lines checked
       drivers/pci/pcie/aer/aerdrv_core.c
        total: 4 errors, 3 warnings, 872 lines checked
       drivers/pci/pcie/aer/aerdrv_errprint.c
        total: 12 errors, 11 warnings, 248 lines checked
      
      After:
       drivers/pci/pcie/aer/aer_inject.c
        total: 0 errors, 0 warnings, 466 lines checked
       drivers/pci/pcie/aer/aerdrv.c
        total: 0 errors, 0 warnings, 335 lines checked
       drivers/pci/pcie/aer/aerdrv.h
        total: 0 errors, 0 warnings, 139 lines checked
       drivers/pci/pcie/aer/aerdrv_core.c
        total: 0 errors, 0 warnings, 869 lines checked
       drivers/pci/pcie/aer/aerdrv_errprint.c
        total: 0 errors, 10 warnings, 247 lines checked
      Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Reviewed-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      c9a91883
  9. 08 1月, 2009 1 次提交
  10. 27 9月, 2006 1 次提交
    • Z
      PCI-Express AER implemetation: AER core and aerdriver · 6c2b374d
      Zhang, Yanmin 提交于
      Patch 3 implements the core part of PCI-Express AER and aerdrv
      port service driver.
      
      When a root port service device is probed, the aerdrv will call
      request_irq to register irq handler for AER error interrupt.
      
      When a device sends an PCI-Express error message to the root port,
      the root port will trigger an interrupt, by either MSI or IO-APIC,
      then kernel would run the irq handler. The handler collects root
      error status register and schedules a work. The work will call
      the core part to process the error based on its type
      (Correctable/non-fatal/fatal).
      
      As for Correctable errors, the patch chooses to just clear the correctable
      error status register of the device.
      
      As for the non-fatal error, the patch follows generic PCI error handler
      rules to call the error callback functions of the endpoint's driver. If
      the device is a bridge, the patch chooses to broadcast the error to
      downstream devices.
      
      As for the fatal error, the patch resets the pci-express link and
      follows generic PCI error handler rules to call the error callback
      functions of the endpoint's driver. If the device is a bridge, the patch
      chooses to broadcast the error to downstream devices.
      Signed-off-by: NZhang Yanmin <yanmin.zhang@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      6c2b374d