The control register range for clktsio interferes with clkaemifspi clock.
And it causes issues for NAND/AEMIF. So fix it.
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

The domain register range for clkfftc1 has to be 0x0235004c
instead of 0x023504c0.
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Add AEMIF/NAND device entry.
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Keystone2 Edison (K2E) is a Quad Cortex A15 based SoC with
1 DSP. It has standard peripherals such as i2c, spi, uart, timer,
pcie, etc similar to k2hk, but without wireless hardwares. This
patch add support for k2 Edison SoC and EVM. This re-uses the common
keystone.dtsi to include common bindings across the various k2
devices.
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Keystone2 Lamarr (K2L) is a dual Cortex A15 core based SoC with
4 DSPs. It has standard peripherals such as i2c, spi, uart, timer,
pcie etc., similar to k2hk, but different set of wireless hardware.
This patch add support for k2 Lamarr SoC and EVM. This re-uses the
common keystone.dtsi to include common bindings across the various
k2 devices.

Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Current keystone.dtsi includes SoC specific definitions for K2HK
SoCs. In order to support two addition keystone devices, k2 Edison
and K2 Lamarr and corresponding EVMs, This patch restructure the
dts files for the following:-

 - All clock nodes that are only available in k2hk SoC are moved
   from keystone-clocks.dtsi to a new k2hk-clocks.dtsi include file
 - The CPU nodes are now part of the soc specific k2hk.dtsi.
 - Change the compatibility string to ti,k2hk-evm and change
   the model name accordingly
 - Finally include k2hk-clocks.dtsi in k2hk.dtsi and that in
   k2hk-evm.dts

Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

fix domain-id for debugsstrc to 1
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

At late init all unused clocks are disabled. So clocks that were not
get before will be gated. In Keysone 2 SoC we have at least one
necessary clock that is not used by any driver - "msmcsram". This
clock is necessary, because it supplies the Multicore Shared Memory
Controller (MSMC). MSMC is the coherency interconnect and all the
coherent masters are connected to it including devices which are not
under Linux OS control. MSMC clock should not be touched even in low
power states.

So drop the clock node, otherwise 'clk_ignore_unused' parameter will
disable the clock leading to system stall.
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Fix typo in clock(s) node name: "clock"-->"clocks".
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Keystone EVMK2HX supports 4 debug LEDs controlled by GPIO lines as
following (active level is high);

DBG_D1 green gpio12
DBG_D1 red   gpio13
DBG_D1 blue  gpio14
DBG_D1 blue  gpio15

For more information see schematics:
 http://wfcache.advantech.com/www/support/TI-EVM/download/Schematics/PDF/K2H_K2EVM-HK_SCH_A102_Rev1_0.pdfSigned-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

This patch adds Keystone GPIO IP device definitions in DT which supports
up to 32 GPIO lines and each GPIO line can be configured as separate
interrupt source (so called "unbanked" IRQ).

For more information see:
 http://www.ti.com/lit/ug/sprugv1/sprugv1.pdfSigned-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Add keystone timer entry to keystone device tree.
This 64-bit timer is used as backup clock event device.
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Add watchdog entry to keystone device tree.
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

The board schematic states that the "SD_CARD_DET_N gets pulled to GND
when card is inserted" so the polarity has been updated to active low.

Polarity is now specified with a GPIO define instead of a magic number.
Signed-off-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMatt Porter <matt.porter@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add nodes for the Arasan SDHCI controller to Zynq dts files.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add the necessary DT nodes to probe the clock controllers on MSM
devices as well as hook up the uart nodes to the clock
controllers. This should allow us to boot to a serial console on
all DT enabled MSM platforms.

Cc: David Brown <davidb@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add watchdog specific config for kizbox board.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

Set default watchdog options in every SoC compatible with the sam9 watchdog.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWim Van Sebroeck <wim@iguana.be>

Add support for the SolidRun Cubox-i devices.  This commit adds similar
basic support as the HummingBoard.  Further devices will be supported
in future patches.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add support for the SolidRun HummingBoard.  This commit adds support for
the following interfaces on this board:

- Consumer Ir receiver
- S/PDIF output
- Both USB interfaces
- Gigabit Ethernet using AR8035
- UART port
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

When a skeleton "clocks { .. }" remain in .dtsi, the child node can
be moved to .dts, "ref12" is then found by of_clk_get().
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Depending on the regulator version, the voltage table might be
different. Use version specific regulator tables in order to select
correct voltage table. For the following regulator versions different
voltage tables are now used:

  * TPS658623: Use correct voltage table for SM2
  * TPS658643: New voltage table for SM2

Both versions are in use on the Colibri T20 module. Make use of the
correct tables by requesting the correct SM2 voltage of 1.8V.

This change is not backward compatible since an old driver is not able
to correctly set that value. The value 1.8V is out of range for the old
driver and will refuse to probe the device. The regulator starts with
default settings and the driver shows appropriate error messages.

On Colibri T20, the old value used to work with TPS658623 since the
driver applied a wrong voltage table too. However, the TPS658643 used
on V1.2 devices uses yet another voltage table and those broke that
pseudo-compatibility. The regulator driver now has the correct voltage
table for both regulator versions and those the correct voltage can be
used in the device tree.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Acked-by: NMark Brown <broonie@linaro.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

The R8A7790's dtsi file i2c0, i2c1, i2c2, and i2c3 nodes have clock
references to the mstp3_clks clock node, however these clocks are in the
mstp9_clks node.

The error was introducted in 72197ca7 ("ARM: shmobile: r8a7790:
 Reference clocks") which is in Simon's current development tree.

This patch fixes the following error:

of_clk_src_onecell_get: invalid clock index 31
i2c-rcar e6508000.i2c: cannot get clock
i2c-rcar: probe of e6508000.i2c failed with error -2
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch creates a unique node for each clock in the OMAP3 power,
reset and clock manager (PRCM).
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch creates a unique node for each clock in the AM33xx power,
reset and clock manager (PRCM).
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Tested-by: NNishanth Menon <nm@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Tested-by: NNishanth Menon <nm@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Tested-by: NNishanth Menon <nm@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).

TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

device_type is deprecated and the kernel doesn't require it in most
cases. The only exceptions for flat tree users are the "gianfar",
"ucc_geth" and "ibm,emac" bindings, and arguably that requirement could
be relaxed for ucc_geth and ibm,emac (that is a task for separate
patches though).

This patch removes references to device_type="network" from the binding
documentation where possible and removes the properties from ARM and
microblaze dts files. This patch does not modify the powerpc .dts files
since there are a much larger number of them affected and I think the
ucc_geth, ibm,emac and gianfar users should be addressed before clearing
out the references to reduce the chance of breakage.
Signed-off-by: NGrant Likely <grant.likely@linaro.org>
Acked-by: NMichal Simek <monstr@monstr.eu>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>

Enable pinctrl for Broadcom Capri (BCM281xx) SoCs.
Signed-off-by: NSherman Yin <syin@broadcom.com>
Reviewed-by: NChristian Daudt <bcm@fixthebug.org>
Reviewed-by: NMatt Porter <matt.porter@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The device_type property is deprecated for the flattened device tree and
the value "ethernet-phy" has never been defined as having a useful
meaning. Neither the kernel nor u-boot depend on it. It should never
have appeared in PHY bindings. This patch removes all references to
"ethernet-phy" as a device_type value from the documentation and the
.dts files.

This patch was generated mechanically with the following command and
then verified by looking at the diff.

sed -i '/"ethernet-phy"/d' `git grep -l '"ethernet-phy"'`
Signed-off-by: NGrant Likely <grant.likely@linaro.org>
Acked-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>

This patch updates the Armada 370/XP SATA node with the new compatible
string "marvell,armada-370-sata".
Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Lior Amsalem <alior@marvell.com>
Cc: stable@vger.kernel.org # v3.6+
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NTejun Heo <tj@kernel.org>

This reverts commit b1d27c79.

Previously we switched the SSI scriprt to dual-fifo mode to reduce playback
underrun issue, which is only included by SDMA firmware version 2. However,
there are quite a lot people still using version 1 or default firmware in
the ROM code of SoC while these two kinds of firmwares do not support the
dual-fifo script and the audio function on their platform would be broken.

Thus this patch provisionally reverts the dual-fifo script to the original
single fifo script to meet all kinds of users' requirements, including the
version 1/2 or inner ROM firmware.
Reported-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The summary interrupt is #16 in the SPI space. Unfortunately,
when this device was translated from board files to DT we forgot
to subtract 16 from the interrupt number to translate it into a
SPI interrupt. Also, the register space is larger than 4k, increase
it appropriately so that the gpio driver doesn't try to access
registers outside of its mapping.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

add pin groups for USP0 only holding one of TX and RX frame sync. this
patch matches with the change in drivers/pinctrl/sirf.
Signed-off-by: NRongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: NBarry Song <Barry.Song@csr.com>