1. 17 10月, 2013 1 次提交
    • D
      ARM: at91: cpuidle: Convert to platform driver · 5ad945ea
      Daniel Lezcano 提交于
      Using the platform driver model is a good way to separate the cpuidle specific
      code from the low level pm code. It allows to remove the dependency between
      these two components.
      
      The platform_device is located in the pm code and a 'set' function has been
      added to set the standby function from the AT91_SOC_START initialization
      function. Each SoC with a cpuidle driver will set the standby function in the
      platform_data field at init time. Then pm code will register the cpuidle
      platform device.
      
      The cpuidle driver will register the platform_driver and use the device's
      platform_data as a standby callback in the idle path.
      
      The at91_pm_enter function contains a { if then else } based on cpu_is_xx
      similar to what was in cpuidle. This is considered dangerous when adding a new
      SoC. Like the cpuidle driver, a standby ops is defined and assigned when the
      SoC init function specifies what is its standby function and reused in the
      at91_pm_enter's 'case' block.
      Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
      Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
      5ad945ea
  2. 18 4月, 2013 1 次提交
  3. 17 4月, 2012 2 次提交
  4. 23 2月, 2012 2 次提交
  5. 03 2月, 2012 5 次提交
  6. 21 1月, 2012 1 次提交
  7. 26 10月, 2010 2 次提交
  8. 09 7月, 2010 1 次提交
    • N
      ARM: 6185/1: AT91: PM: dual ram controller support · 7dca3343
      Nicolas Ferre 提交于
      This rework allows to address tow memory controllers. AT91SAM9263 and
      AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management
      should take care of this.
      This patch modify the way RAM IP header files are implemented to allow
      access to registers of both controllers ; it also adds some macros.
      
      We also modify the power management files to use those modified header files.
      Slow clock (assembly) and regular power management functions are synchronized
      for setting of RAM self-refresh procedure:
      (lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESH
      
      Note that AT91RM9200 is not impacted by this modification.
      Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
      Acked-by: NAndrew Victor <linux@maxim.org.za>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      7dca3343
  9. 11 11月, 2009 1 次提交