1. 28 1月, 2008 5 次提交
  2. 07 11月, 2007 2 次提交
  3. 31 10月, 2007 1 次提交
    • P
      sh: Clean up SR.RB Kconfig mess. · c81134b5
      Paul Mundt 提交于
      CPU_HAS_SR_RB is selected by both CPU_SH3 and CPU_SH4, so having a
      dependency and default y on those additionally doesn't make much sense.
      The select also has to be special cased for CPUs that don't support
      this.
      
      This is also something that has been abused too much as a result
      of being user-visible, hence the addition of the select in the first
      place. So just kill the user-visibility entirely while we're at it.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      c81134b5
  4. 30 10月, 2007 1 次提交
  5. 20 10月, 2007 1 次提交
  6. 28 9月, 2007 1 次提交
    • P
      sh: Conditionalize gUSA support. · 83662461
      Paul Mundt 提交于
      This conditionalizes gUSA support. gUSA is not supported on
      SMP configurations, and it's not necessary there anyways due
      to having other atomicity options (ie, movli.l/movco.l).
      
      Anything implementing the LL/SC semantics (all SH-4A CPUs)
      can switch to userspace atomicity implementations without
      requiring gUSA. This is left default-enabled on all UP so
      that glibc doesn't break.
      
      Those that know what they are doing can disable this explicitly.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      83662461
  7. 27 9月, 2007 1 次提交
  8. 21 9月, 2007 8 次提交
  9. 26 7月, 2007 3 次提交
  10. 25 7月, 2007 2 次提交
  11. 20 7月, 2007 5 次提交
    • M
      sh: intc - add support for SH7750 and its variants · 56386f64
      Magnus Damm 提交于
      This patch converts the cpu specific 7750 setup code to use the
      new intc controller. Many new vectors are added and multiple
      processor variants including 7091, 7750, 7750s, 7750r, 7751 and
      7751r should all have the correct vectors hooked up.
      
      IRLM interrupts can be enabled using ipr_irq_enable_irlm() which
      now is marked as __init.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      56386f64
    • P
      sh: cpufreq: clock framework support. · cb5ec75b
      Paul Mundt 提交于
      This gets the SH cpufreq working again. We follow the changes
      in the AVR32 implementation for wrapping in to the clock framework.
      CPUs that wish to use this are required to define rate rounding
      primitives in order to satisfy clk_round_rate().
      
      This works well enough for the common case, though we should
      look at unifying this driver across all of the platforms that
      implement clock framework support in one capacity or another.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      cb5ec75b
    • M
      sh: intc - add support for 7780 · 39c7aa9e
      Magnus Damm 提交于
      This patch converts the cpu specific 7780 setup code to use the
      new intc controller. Many new vectors are added and also support for
      external interrupt sense configuration. So with this patch it is now
      possible to configure external interrupt pins as edge or level
      triggered using set_irq_type().
      
      No external interrupts are registered by default.
      Use plat_irq_setup_pins() to select between IRQ or IRL mode.
      
      This patch also fixes the Alarm IRQ for the RTC.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      39c7aa9e
    • P
      sh: cpufreq: Fix driver dependencies and flag as broken. · 792e947a
      Paul Mundt 提交于
      This is only supported on SH-4, so don't expose it for the other
      CPUs. Additionally, it's suffered some bitrot, so add a BROKEN
      dependency as well until we fix it up.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      792e947a
    • M
      sh: intc - shared IPR and INTC2 controller · 02ab3f70
      Magnus Damm 提交于
      This is the second version of the shared interrupt controller patch
      for the sh architecture, fixing up handling of intc_reg_fns[].
      
      The three main advantages with this controller over the existing
      ones are:
      
      	- Both priority (ipr) and bitmap (intc2) registers are
      	  supported
      	- External pin sense configuration is supported, ie edge
      	  vs level triggered
      	- CPU/Board specific code maps 1:1 with datasheet for
      	  easy verification
      
      This controller can easily coexist with the current IPR and INTC2
      controllers, but the idea is that CPUs/Boards should be moved over
      to this controller over time so we have a single code base to
      maintain.
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      02ab3f70
  12. 20 6月, 2007 2 次提交
  13. 11 6月, 2007 1 次提交
  14. 08 6月, 2007 3 次提交
    • P
      sh: Fix SH-4 CPU selects. · 05627486
      Paul Mundt 提交于
      Now that select no longer works for selecting the "closest" CPU,
      we have to explicitly reference the precise sub-type in the few
      places where it actually matters (presently only setup code and
      some legacy sh-sci cruft).
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      05627486
    • P
      sh: Rip out special unknown machvec. · fd8f20e8
      Paul Mundt 提交于
      This kills off the BareCPU board as a "special" machvec, rather,
      we leave this as a default for when no other vector is available,
      or when we want to use it in combination with other vectors for
      testing with generic ops. As sh_mv is copied out anyways (or
      overloaded when an alternate vector is explicitly selected), this
      doesn't consume any additional memory.
      
      The generic machvec can be forcibly selected with sh_mv=generic,
      or by not having any other boards enabled.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      fd8f20e8
    • P
      sh: Rework CPU/board dependencies. · f3d22298
      Paul Mundt 提交于
      This was a big mess, rework the logic a bit so that we constrain
      to a particular subtype and figure out the board support based
      on that. This makes building subtype specific kernels supporting
      multiple boards possible again.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      f3d22298
  15. 09 5月, 2007 1 次提交
    • P
      sh: clockevent/clocksource/hrtimers/nohz TMU support. · 57be2b48
      Paul Mundt 提交于
      This adds basic support for clockevents and clocksources,
      presently only implemented for TMU-based systems (which
      are the majority of SH-3 and SH-4 systems).
      
      The old NO_IDLE_HZ implementation is also dropped completely,
      the only users of this were on TMU-based systems anyways.
      
      More work needs to be done to generalize the TMU handling,
      in that the current implementation is rather tied to the
      notion of TMU0 and TMU1 utilization.
      
      Additionally, as more SH timers switch over to this scheme,
      we'll be able to gut most of the remaining system timer
      infrastructure that existed before.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      57be2b48
  16. 07 5月, 2007 3 次提交