This results in smaller/faster/simpler code and allows future optimizations.
Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}.

v2:
* updated for scc_pata
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

* add ide_use_fast_pio() helper for use by host drivers

* add DMA capability and hwif->autodma checks to ide_use_dma()

  - au1xxx-ide/it8213/it821x drivers didn't check for (id->capability & 1)

    [ for the IT8211/2 in SMART mode this check shouldn't be made but since
      in it821x_fixups() we set DMA bit explicitly:

               if(strstr(id->model, "Integrated Technology Express")) {
                       /* In raid mode the ident block is slightly buggy
                          We need to set the bits so that the IDE layer knows
                          LBA28. LBA48 and DMA ar valid */
                       id->capability |= 3;            /* LBA28, DMA */

       we are better off using generic helper if we can ]

  - ide-cris driver didn't set ->autodma

    [ before the patch hwif->autodma was only checked in the chipset specific
      hwif->ide_dma_check implementations, for ide-cris it is cris_dma_check()
      function so there no behavior change here ]

v2:
* updated patch description (thanks to Alan Cox for the feedback)

v3:
* updated for scc_pata driver
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

In cmd64x, siimage and scc_pata drivers:
* don't set drive->init_speed as it should be already
  set by successful execution of ide_set_xfer_rate()
* use hwif->speedproc functions directly

Above changes allows removal of EXPORT_SYMBOL_GPL(ide_set_xfer_rate).

v2:
* updated for scc_pata driver
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

* remove bogus comment for sis5513_config_xfer_rate()
* there is no need to call config_drive_art_rwp() because
  it is called by config_art_rwp_pio()
* remove needless wrapper
* remove stale "TODO" comment
  (IDE core should provide generic tuning code)
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

* disable DMA masks if no_piix_dma is set and remove now
  not needed no_piix_dma_check from piix_config_drive_for_dma()
* there is no need to read register 0x55 in init_hwif_piix()
* move cable detection code to piix_cable_detect()
* remove unreachable 82371MX code from init_hwif_piix()
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

* remove redundant svwks_ide_dma_end() [ __ide_dma_end() is used by default ]
* remove init_dma_svwks() so the default ide_setup_dma() function is used
  [ init_setup_csb6() takes care of not initializing disabled channels ]
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

* BUG() on unknown DMA mode in cs5530_config_dma()
* there is no need to call hwif->ide_dma_host_{off,on}() in
  cs5530_config_dma() because hwif->ide_dma_host_{off,on}()
  is called by hwif->ide_dma_off_{quietly,on}()
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

->init_dma() cannot be called with dmabase == 0
(see drivers/ide/setup-pci.c)
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

In drivers/ide/Kconfig BLK_DEV_TRM290 depends on
BLK_DEV_IDEDMA_PCI (on which is BLK_DEV_IDEDMA dependant on).
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

CONFIG_PDC202XX_MASTER config option doesn't exist
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Fix a number of issues with the DMA support code:

- driver claims support for all SW/MW DMA modes while supporting only MWDMA2;

- ide_dma_check() method tries to enable DMA on the "known good" drives which
  don't support MWDMA2;

- ide_dma_on() method upon failure to set drive to MWDMA2 re-tunes already
  tuned PIO mode and calls ide_dma_off() method instead of returning error;

- ide_dma_off() method sets drive->current_speed while it doesn't actually
  change (only the PIO timings are re-loaded into the chip's registers);

- init_hwif() method forcibly sets/resets both "drive DMA capable" bits while
  this is properly handled by ide_dma_{on,off}() methods being called later...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Fix the driver's tuneproc() method to always set the PIO mode requested and not
pick the best possible one, rename it to pdc202xx_tune_drive(), and change the
calls to it accordingly; remove the preceding comment which has nothing to do
with the code.

Sergei Shtylyov wrote:
>     The tuneproc() method should take arg 255 for auto-selecting the best PIO
> mode, not 5 as it did here + this driver's method always auto-selected instead
> of setting the mode it's been told to -- issue typical to drivers/ide/...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Fix two typos found by SiI680A documentation check.  They caused the taskfile
transfer overclocking:

- in PIO mode 1 as 0x2283 must be used for both data and taskfile transfers;

- in PIO mode 2 as data and taskfile timings are swapped when writing to the
  MMIO regs.

Fix coding style and trailing whitespace in enclosing statements while at it...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

 drivers/ide/pci/siimage.c |   59 ++++++++++++++++++++++------------------------
 1 file changed, 29 insertions(+), 30 deletions(-)

patch 2/2:
  Remove clearing bmdma status from cdrom_decode_status() since ATA devices
  might need it as well.

  (http://lkml.org/lkml/2006/12/4/201 and http://lkml.org/lkml/2006/11/15/94)
Signed-off-by: NAlbert Lee <albertcc@tw.ibm.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: "Adam W. Hawks" <awhawks@us.ibm.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

patch 1/2 (revised):
- Fix drive->waiting_for_dma to work with CDB-intr devices.
- Do the dma status clearing in ide_intr() and add a new
  hwif->ide_dma_clear_irq for Intel ICHx controllers.

Revised per Alan, Sergei and Bart's advice.

Patch against 2.6.20-rc6. Tested ok on my ICH4 and pdc20275 adapters.
Please review/apply, thanks.
Signed-off-by: NAlbert Lee <albertcc@tw.ibm.com>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: "Adam W. Hawks" <awhawks@us.ibm.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

* atiixp: if DMA can't be used atiixp_config_drive_for_dma() should return 0,
  atiixp_dma_check() will tune the correct PIO mode anyway

* jmicron: if DMA can't be used config_chipset_for_dma() should return 0,
  micron_config_drive_for_dma() will tune the correct PIO mode anyway

  config_jmicron_chipset_for_pio(drive, !speed) doesn't program
  device transfer mode for speed != 0 (only wastes some CPU cycles
  on ide_get_best_pio_mode() call) so remove it

* triflex: if DMA can't be used triflex_config_drive_for_dma() should return 0,
  triflex_config_drive_xfer_rate() will tune correct PIO mode anyway

Above changes also fix (theoretical) issue when ->speedproc fails to set
device transfer mode (i.e. when ide_config_drive_speed() fails to program it)
but one of DMA transfer modes is already enabled on the device by the BIOS.
In such scenario ide_dma_enable() will incorrectly return true statement
and ->ide_dma_check will try to enable DMA on the device.
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

* remember to clear reg2 bits for the current device before setting mode
* remove no longer needed hpt34x_clear_chipset()
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

On Thursday 11 January 2007 23:17, Bartlomiej Zolnierkiewicz wrote:
> 
> My working IDE tree (against Linus' tree) now resides here:
> 
> 	http://kernel.org/pub/linux/kernel/people/bart/pata-2.6/patches/

Bart, here's a driver I've been keeping out-of-tree for the past couple
of years.  This is for the Delking/Lexar/ASKA/etc.. 32-bit cardbus IDE
CompactFlash adapter card.

It's probably way out of sync with the latest driver model (??), but it
still builds/works.  I'm not interested in doing much of a rewrite, other
than for libata someday, as I no longer use the card myself.

But lots of other people do seem to use it, so it might be nice to see it
"in-tree".
Signed-off-by: NMark Lord <mlord@pobox.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

* set ATAPI/IORDY/TIME bits correctly in it8213_tuneproc()
* fix UDMA/MWDMA/SWDMA masks in it8213_init_hwif()
* in it8213_tune_chipset() SWDMA2 mode should be used instead of MWDMA0
* backport various fixes from piix/slc90e66 drivers:
  - in it8213_tuneproc() the highest possible PIO mode is PIO4 (not PIO5)
  - clear ATAPI/IORDY/TIME bits before setting them also for slave device
  - use ->speedproc in it8213_config_drive_for_dma()
  - don't try to tune PIO in config_chipset_for_pio()
  - simplify is_slave calculation in it8213_tuneproc()
  - misc cleanups
* fix it8213_ratemask() and it8213_tuneproc() comments
* simplify it8213_init_hwif()
* remove init_chipset_it8213()
* add missing Copyrights and update MODULE_AUTHOR()
* CodingStyle cleanups
* remove dead code

v2:
* PCI_DEVICE_ID_ITE_8213 is only defined in -mm kernels,
  so just use PCI Device ID (0x8213) directly
* fix ->ultra_mask incorrectly changed to 0x3f in v1 version of the patch
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

From: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Signed-off-by: NAndrew Morton <akpm@osdl.org>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Adrian Bunk <bunk@stusta.de>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Signed-off-by: NAdrian Bunk <bunk@stusta.de>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

This is the driver for the Toshiba TC86C001 GOKU-S PCI IDE controller,
completely reworked from the original brain-damaged Toshiba's 2.4 version.

This single channel UltraDMA/66 controller is very simple in programming,
yet Toshiba managed to plant many interesting bugs in it.  The particularly
nasty "limitation 5" (as they call the errata) caused me to abuse the IDE
core in a possibly most interesting way so far.  However, this is still
better than the #ifdef mess in drivers/ide/ide-io.c that the original
version included (well, it had much more mess)...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: NAlan Cox <alan@redhat.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Fold check_in_drive_lists() into quirkproc() handler in both PDC202xx
drivers-- this function was never called with a list other than
pdc_quirk_drives and was a bad example of code overall...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Remove the following useless fragments from the driver:

- the ide_dma_lostirq() and ide_dma_timeout() handlers which boil down to just
  printing the incoherent reset message and calling their default counterparts;

- check for non-NULL drive->id in the ide_dma_check() handler -- this is assumed
  to be true by all other handlers (also, get rid of unnecessary nesting of the
  conditional statements there);

- the comment before pdcnew_tune_drive() which has nothing to do with the code.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Synchronize with version 0.46 of the Intel PIIX/ICH driver:

- carry over Alan's and my own fixes in the tuneproc() method and my cleanups
  both there and in the ratemask() method;

- SLC90E66 only supports MW DMA modes 1/2 and SW DMA mode 2 (just like Intel
  chips), so don't claim support for other MW/SW DMA modes;

- don't check dor non-NULL drive->id in the ide_dma_check() method -- this is
  assumed to be true in all other drivers;

- do some coding/formatting cleanups while at it...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Fix/cleanup the driver's tuneproc() and ratemask() methods:

- PPE, IE, and TIME bits need to be cleared beforehand for the slave drive as
  well as master (Alan probably just forgot about it);

- this driver only supports PIO modes up to 4, so must pass the correct limit
  to ide_get_best_pio_mode();

- use min_t() macro instead of min();

- simplify slave vs master drive evaluation;

- do come coding and formatting cleanups...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

According to the datasheet, Intel 82371MX (MPIIX) actually has only a
single IDE channel mapped to the primary or secondary ports depending on
the value of the bit 14 of the IDETIM register at PCI config.  offset 0x6C
(the register at 0x6F which the driver refers to.  doesn't exist).  So,
disguise the controller as dual channel and set enablebits masks/values
such that only either primary or secondary channel is detected enabled. 
Also, preclude the IDE probing code from reading PCI BARs, this controller
just doesn't have them (it's not the separate PCI function like the other
PCI controllers), it only decodes the legacy addresses.

[ Alan sayeth " MPIIX does not work with or without the change.  It needs its
  own different driver and not to use setup-pci.  Huge job and since it works
  well with libata who cares.  Ditto the early PIIX chip." ]
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Fix minor coding mistake in the HPT36x PCI clock detection code noticed by
Bartlomiej Zolnierkiewicz -- it always reported 33 MHz due to the missing
'break' statements.  This, however, most probably never mattered -- in fact, I
was thinking of removing the 25/40 MHz cases completely since HPT36x BIOSes
didn't seem to set any other value than 7 into the 'cmd_high_time' field, i.e.
 supported only 33 MHz PCI.

Note that in the original driver there was another bug: 25 and 40 MHz cases
were interchanged.  Since the 'cmd_high_time' field is in units of PCI clocks,
a lower clock count just *cannot* correspond to a higher frequency, i.  e.  it
should be 5 for 25 MHz PCI and 9 for 40 MHz PCI, not the other way around.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Finally, rework the driver init.  code to correctly handle all the chip
variants HighPoint has created so far.  This should cure the rest of the
timing issues in the driver (especially, on 66 MHz PCI) caused by the
HighPoint's habit of switching the base DPLL clock with every new revision
of the chips...

  - switch to using the enumeration type to differ between the numerous chip
    variants, matching PCI device/revision ID with the chip type early, at the
    init_setup stage;

  - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
    stop duplicating it for each channel by storing the pointer in the pci_dev
    structure: first, at the init_setup stage, point it to a static "template"
    with only the chip type and its specific base DPLL frequency, the highest
    supported DMA mode, and the chip settings table pointer filled, then, at
    the init_chipset stage, allocate per-chip instance  and fill it with the
    rest of the necessary information;

  - get rid of the constant thresholds in the HPT37x PCI clock detection code,
    switch  to calculating  PCI clock frequency based on the chip's base DPLL
    frequency;

  - switch to using the DPLL clock and enable UltraATA/133 mode by default on
    anything newer than HPT370/A;

  - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
    unify the HPT36x/37x setup code and the speedproc handlers by joining the
    register setting lists into the table indexed by the clock selected;

  - add enablebits for all the chips to avoid touching disabled channels
    (though the HighPoint BIOS seem to only disable the primary one on
    HPT371/N);

  - separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
    when setting an UltraDMA mode in hpt37x_tune_chipset().

This version has been tested on HPT370/302/371N.

Thanks to Alan for the inspiration. Hopefully, his libata driver will also
benefit from the work done on this "obsolete" driver...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Clean up DMA timeout handling for HPT370:

- hpt370_lostirq_timeout() cleared the DMA status which made __ide_dma_end()
   called afterwards return the incorrect result, and the DMA engine was reset
   both before and after stopping DMA while the HighPoint drivers only do it
   after (which seems logical) -- fix this and also rename the function;

- get rid of the needless mutual recursion in hpt370_ide_dma_end() and
   hpt370_ide_dma_timeout();

- get rid of hpt370_lostirq_timeout() since hwif->ide_dma_end() called from
   the driver's interrupt handler later does all its work.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Continue with the driver rewrite:

- move the interrupt twiddling code from the speedproc handlers into the
    init_hwif_hpt366 which allows to merge the two HPT37x speedproc handlers
    into one;

- get rid of in init_hpt366 which solely consists of the duplicate code, then
    fold init_hpt37x() into init_chipset_hpt366();

- fix hpt3xx_tune_drive() to always set the PIO mode requested, not the best
    possible one, change hpt366_config_drive_xfer_rate() accordingly, simplify
    it a bit;

- group all the DMA related code together init_hwif_hpt366(), and generally
    clean up and beautify it.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Begin the real driver redesign. For the starters:

- cache the offset of the IDE channel's MISC. control registers which are used
   throughout the driver in hwif->select_data;

- only touch the relevant MCR when detecting the cable type on HPT374's
   function 1;

- make HPT36x's speedproc handler look the same way as HPT37x ones; fix the
   PIO timing register mask for HPT37x.

- rename all the HPT3xx register related variables consistently; clean up the
   whitespace.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Switch to using pci_get_slot() to get to the function 1 of HPT36x/374 chips --
there's no need for the driver itself to walk the list of the PCI devices, and
it also forgets to check the bus number of the device found.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

- Rework the driver setup code so that it prefixes the driver startup
  messages with the real chip name.

- Print the measured f_CNT value and the DPLL setting for non-HPT3xx
  chips as well.

- Claim the extra 240 bytes of I/O space for all chips, not only for
  those having PCI device ID of 0x0004.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

- Rework hpt3xx_ratemask() and hpt3xx_ratefilter() so that the former
  returns the max.  mode computed at the load time and doesn't have to do
  bad Ultra33 drive list lookups anymore; remove the duplicate code from
  the latter function.  Move the quirky drive list lookup into
  hpt3xx_quirkproc() where it should have been from the start...

- Disable UltraATA/100 for HPT370 by default as the 33 MHz ATA clock
  being used does not allow for it, and this *greatly* increases the
  transfer speed.

- Save some space by using byte-wide fields in struct hpt_info; switch to
  reading the 8-bit PCI revision ID reg.  only, not the whole 32-bit reg.

- Start incrementing the driver version number with each patch (should
  have been done from the first one posted).
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>