1. 06 10月, 2014 1 次提交
    • D
      sparc64: Fix physical memory management regressions with large max_phys_bits. · 0dd5b7b0
      David S. Miller 提交于
      If max_phys_bits needs to be > 43 (f.e. for T4 chips), things like
      DEBUG_PAGEALLOC stop working because the 3-level page tables only
      can cover up to 43 bits.
      
      Another problem is that when we increased MAX_PHYS_ADDRESS_BITS up to
      47, several statically allocated tables became enormous.
      
      Compounding this is that we will need to support up to 49 bits of
      physical addressing for M7 chips.
      
      The two tables in question are sparc64_valid_addr_bitmap and
      kpte_linear_bitmap.
      
      The first holds a bitmap, with 1 bit for each 4MB chunk of physical
      memory, indicating whether that chunk actually exists in the machine
      and is valid.
      
      The second table is a set of 2-bit values which tell how large of a
      mapping (4MB, 256MB, 2GB, 16GB, respectively) we can use at each 256MB
      chunk of ram in the system.
      
      These tables are huge and take up an enormous amount of the BSS
      section of the sparc64 kernel image.  Specifically, the
      sparc64_valid_addr_bitmap is 4MB, and the kpte_linear_bitmap is 128K.
      
      So let's solve the space wastage and the DEBUG_PAGEALLOC problem
      at the same time, by using the kernel page tables (as designed) to
      manage this information.
      
      We have to keep using large mappings when DEBUG_PAGEALLOC is disabled,
      and we do this by encoding huge PMDs and PUDs.
      
      On a T4-2 with 256GB of ram the kernel page table takes up 16K with
      DEBUG_PAGEALLOC disabled and 256MB with it enabled.  Furthermore, this
      memory is dynamically allocated at run time rather than coded
      statically into the kernel image.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Acked-by: NBob Picco <bob.picco@oracle.com>
      0dd5b7b0
  2. 04 5月, 2014 1 次提交
  3. 13 11月, 2013 2 次提交
    • D
      sparc64: Make PAGE_OFFSET variable. · b2d43834
      David S. Miller 提交于
      Choose PAGE_OFFSET dynamically based upon cpu type.
      
      Original UltraSPARC-I (spitfire) chips only supported a 44-bit
      virtual address space.
      
      Newer chips (T4 and later) support 52-bit virtual addresses
      and up to 47-bits of physical memory space.
      
      Therefore we have to adjust PAGE_SIZE dynamically based upon
      the capabilities of the chip.
      
      Note that this change alone does not allow us to support > 43-bit
      physical memory, to do that we need to re-arrange our page table
      support.  The current encodings of the pmd_t and pgd_t pointers
      restricts us to "32 + 11" == 43 bits.
      
      This change can waste quite a bit of memory for the various tables.
      In particular, a future change should work to size and allocate
      kern_linear_bitmap[] and sparc64_valid_addr_bitmap[] dynamically.
      This isn't easy as we really cannot take a TLB miss when accessing
      kern_linear_bitmap[].  We'd have to lock it into the TLB or similar.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Acked-by: NBob Picco <bob.picco@oracle.com>
      b2d43834
    • D
      sparc64: Document the shift counts used to validate linear kernel addresses. · bb7b4353
      David S. Miller 提交于
      This way we can see exactly what they are derived from, and in particular
      how they would change if we were to use a different PAGE_OFFSET value.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Acked-by: NBob Picco <bob.picco@oracle.com>
      bb7b4353
  4. 03 8月, 2013 1 次提交
  5. 07 9月, 2012 1 次提交
    • D
      sparc64: Support 2GB and 16GB page sizes for kernel linear mappings. · 4f93d21d
      David S. Miller 提交于
      SPARC-T4 supports 2GB pages.
      
      So convert kpte_linear_bitmap into an array of 2-bit values which
      index into kern_linear_pte_xor.
      
      Now kern_linear_pte_xor is used for 4 page size aligned regions,
      4MB, 256MB, 2GB, and 16GB respectively.
      
      Enabling 2GB pages is currently hardcoded using a check against
      sun4v_chip_type.  In the future this will be done more cleanly
      by interrogating the machine description which is the correct
      way to determine this kind of thing.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4f93d21d
  6. 05 8月, 2011 1 次提交
  7. 29 9月, 2009 1 次提交
  8. 26 8月, 2009 1 次提交
    • D
      sparc64: Validate linear D-TLB misses. · d8ed1d43
      David S. Miller 提交于
      When page alloc debugging is not enabled, we essentially accept any
      virtual address for linear kernel TLB misses.  But with kgdb, kernel
      address probing, and other facilities we can try to access arbitrary
      crap.
      
      So, make sure the address we miss on will translate to physical memory
      that actually exists.
      
      In order to make this work we have to embed the valid address bitmap
      into the kernel image.  And in order to make that less expensive we
      make an adjustment, in that the max physical memory address is
      decreased to "1 << 41", even on the chips that support a 42-bit
      physical address space.  We can do this because bit 41 indicates
      "I/O space" and thus covers non-memory ranges.
      
      The result of this is that:
      
      1) kpte_linear_bitmap shrinks from 2K to 1K in size
      
      2) we need 64K more for the valid address bitmap
      
      We can't let the valid address bitmap be dynamically allocated
      once we start using it to validate TLB misses, otherwise we have
      crazy issues to deal with wrt. recursive TLB misses and such.
      
      If we're in a TLB miss it could be the deepest trap level that's legal
      inside of the cpu.  So if we TLB miss referencing the bitmap, the cpu
      will be out of trap levels and enter RED state.
      
      To guard against out-of-range accesses to the bitmap, we have to check
      to make sure no bits in the physical address above bit 40 are set.  We
      could export and use last_valid_pfn for this check, but that's just an
      unnecessary extra memory reference.
      
      On the plus side of all this, since we load all of these translations
      into the special 4MB mapping TSB, and we check the TSB first for TLB
      misses, there should be absolutely no real cost for these new checks
      in the TLB miss path.
      
      Reported-by: heyongli@gmail.com
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d8ed1d43
  9. 05 12月, 2008 1 次提交
    • S
      sparc,sparc64: unify kernel/ · a88b5ba8
      Sam Ravnborg 提交于
      o Move all files from sparc64/kernel/ to sparc/kernel
        - rename as appropriate
      o Update sparc/Makefile to the changes
      o Update sparc/kernel/Makefile to include the sparc64 files
      
      NOTE: This commit changes link order on sparc64!
      
      Link order had to change for either of sparc32 and sparc64.
      And assuming sparc64 see more testing than sparc32 change link
      order on sparc64 where issues will be caught faster.
      Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a88b5ba8
  10. 13 1月, 2008 1 次提交
  11. 17 10月, 2007 1 次提交
  12. 17 3月, 2007 1 次提交
    • D
      [SPARC64]: Get DEBUG_PAGEALLOC working again. · d1acb421
      David S. Miller 提交于
      We have to make sure to use base-pagesize TLB entries even during the
      early transition period where we need TLB miss handling but don't have
      the kernel page tables setup yet for the linear region.
      
      Also, it is necessary therefore to not use the 4MB TSB for these
      translations, and instead use the normal kernel TSB.  This allows us
      to also get rid of the 4MB tsb for debug builds which shrinks the
      kernel a little bit.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d1acb421
  13. 01 7月, 2006 1 次提交
  14. 20 3月, 2006 12 次提交
  15. 13 10月, 2005 1 次提交
    • D
      [SPARC64]: Fix boot failures on SunBlade-150 · c9c10830
      David S. Miller 提交于
      The sequence to move over to the Linux trap tables from
      the firmware ones needs to be more air tight.  It turns
      out that to be %100 safe we do need to be able to translate
      OBP mappings in our TLB miss handlers early.
      
      In order not to eat up a lot of kernel image memory with
      static page tables, just use the translations array in
      the OBP TLB miss handlers.  That solves the bulk of the
      problem.
      
      Furthermore, to make sure the OBP TLB miss path will work
      even before the fixed MMU globals are loaded, explicitly
      load %g1 to TLB_SFSR at the beginning of the i-TLB and
      d-TLB miss handlers.
      
      To ease the OBP TLB miss walking of the prom_trans[] array,
      we sort it then delete all of the non-OBP entries in there
      (for example, there are entries for the kernel image itself
      which we're not interested in at all).
      
      We also save about 32K of kernel image size with this change.
      Not a bad side effect :-)
      
      There are still some reasons why trampoline.S can't use the
      setup_trap_table() yet.  The most noteworthy are:
      
      1) OBP boots secondary processors with non-bias'd stack for
         some reason.  This is easily fixed by using a small bootup
         stack in the kernel image explicitly for this purpose.
      
      2) Doing a firmware call via the normal C call prom_set_trap_table()
         goes through the whole OBP enter/exit sequence that saves and
         restores OBP and Linux kernel state in the MMUs.  This path
         unfortunately does a "flush %g6" while loading up the OBP locked
         TLB entries for the firmware call.
      
         If we setup the %g6 in the trampoline.S code properly, that
         is in the PAGE_OFFSET linear mapping, but we're not on the
         kernel trap table yet so those addresses won't translate properly.
      
         One idea is to do a by-hand firmware call like we do in the
         early bootup code and elsewhere here in trampoline.S  But this
         fails as well, as aparently the secondary processors are not
         booted with OBP's special locked TLB entries loaded.  These
         are necessary for the firwmare to processes TLB misses correctly
         up until the point where we take over the trap table.
      
      This does need to be resolved at some point.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c9c10830
  16. 26 9月, 2005 1 次提交
    • D
      [SPARC64]: Add CONFIG_DEBUG_PAGEALLOC support. · 56425306
      David S. Miller 提交于
      The trick is that we do the kernel linear mapping TLB miss starting
      with an instruction sequence like this:
      
      	ba,pt		%xcc, kvmap_load
      	 xor		%g2, %g4, %g5
      
      succeeded by an instruction sequence which performs a full page table
      walk starting at swapper_pg_dir.
      
      We first take over the trap table from the firmware.  Then, using this
      constant PTE generation for the linear mapping area above, we build
      the kernel page tables for the linear mapping.
      
      After this is setup, we patch that branch above into a "nop", which
      will cause TLB misses to fall through to the full page table walk.
      
      With this, the page unmapping for CONFIG_DEBUG_PAGEALLOC is trivial.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      56425306
  17. 22 9月, 2005 2 次提交