- 11 6月, 2013 2 次提交
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由 Tushar Behera 提交于
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 24 4月, 2013 1 次提交
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由 Tushar Behera 提交于
commit 688f7d8c ("clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3} to fix the wrong clock value. Though this fixed issue with Arndale, it created regressions for other boards like Snow. On Exynos5250, sclk_mmc<n> is generated like below (as per the clock names in drivers/clk/samsung/clk-exynos5250.c) mout_group1_p ==> mout_mmc<n> ==> div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n> Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence div_mmc_pre<n> was not getting referred in kernel code and depending on its value set during preboot, sclk_mmc<n> value was different for various boards. Setting the correct clock generation path should fix the issues reported in above referenced commit. The changes committed during the earlier patch has also been reverted here. Reported-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Tested-by: NDoug Anderson <dianders@chromium.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 20 4月, 2013 1 次提交
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由 Arnd Bergmann 提交于
The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
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- 08 4月, 2013 1 次提交
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由 Tushar Behera 提交于
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by: NTushar Behera <tushar.behera@linaro.org> CC: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 04 4月, 2013 2 次提交
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由 Leela Krishna Amudala 提交于
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Tomasz Figa 提交于
This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 25 3月, 2013 1 次提交
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由 Thomas Abraham 提交于
The Exynos5250 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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