1. 21 10月, 2013 1 次提交
    • R
      ARM: dts: omap: Add reset/idle on init bindings for OMAP · f12ecbe2
      Rajendra Nayak 提交于
      On OMAP we have co-processor IPs, memory controllers,
      GPIOs which control regulators and power switches to
      PMIC, and SoC internal Bus IPs, some or most of which
      should either not be reset or idled or both at init.
      (In some cases there are erratas which prevent an IP
      from being reset)
      Have a way to pass this information from DT.
      
      Update the am33xx/omap4 and omap5 dtsi files with the
      new bindings for modules which either should not be
      idled. reset or both. A later patch would cleanup the
      same information that exists today as part of the hwmod
      data files.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
      f12ecbe2
  2. 12 10月, 2013 2 次提交
  3. 08 10月, 2013 1 次提交
  4. 19 6月, 2013 5 次提交
  5. 23 5月, 2013 1 次提交
  6. 09 4月, 2013 10 次提交
  7. 03 4月, 2013 1 次提交
  8. 02 11月, 2012 1 次提交
    • J
      ARM: dts: OMAP4: Update timer addresses · d03a93bb
      Jon Hunter 提交于
      For OMAP4 devices, timers 5-8 have both a L3 bus address and a Cortex-A9
      private bus address. Currently the device-tree source only contains the
      L3 bus address for these timers. Update these timers to include the
      Cortex-A9 private address and make the default address the Cortex-A9
      private bus address to match the current HWMOD implementation.
      Signed-off-by: NJon Hunter <jon-hunter@ti.com>
      Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
      d03a93bb
  9. 29 10月, 2012 4 次提交
  10. 11 9月, 2012 1 次提交
  11. 08 9月, 2012 8 次提交
  12. 22 8月, 2012 1 次提交
  13. 09 7月, 2012 3 次提交
  14. 15 3月, 2012 1 次提交