- 21 10月, 2013 1 次提交
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由 Rajendra Nayak 提交于
On OMAP we have co-processor IPs, memory controllers, GPIOs which control regulators and power switches to PMIC, and SoC internal Bus IPs, some or most of which should either not be reset or idled or both at init. (In some cases there are erratas which prevent an IP from being reset) Have a way to pass this information from DT. Update the am33xx/omap4 and omap5 dtsi files with the new bindings for modules which either should not be idled. reset or both. A later patch would cleanup the same information that exists today as part of the hwmod data files. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
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- 12 10月, 2013 2 次提交
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由 Joel Fernandes 提交于
OMAP4 has an DES3DES module that uses the omap-des crypto driver. Add DT entries for the same. Signed-off-by: NJoel Fernandes <joelf@ti.com> Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
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由 Joel Fernandes 提交于
OMAP4 has an AES module that uses the omap-aes crypto driver. Add DT entries for the same. Signed-off-by: NJoel Fernandes <joelf@ti.com> Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
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- 08 10月, 2013 1 次提交
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由 Lee Jones 提交于
Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
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- 19 6月, 2013 5 次提交
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由 Florian Vaussard 提交于
Using constants for pinctrl allows a better readability, and removes redundancy with comments. Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Florian Vaussard 提交于
Use the constants defined in include/dt-bindings/interrupt-controller/ to enhance readability. Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Florian Vaussard 提交于
Use standard GPIO constants to enhance the readability of DT GPIOs. Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Florian Vaussard 提交于
Replace /include/ by #include for OMAP2+ DT, in order to use the C pre-processor, making use of #define features possible. Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Suman Anna 提交于
The carveouts that have been reserved for multimedia usecases are not being used currently by any driver and so have been cleaned up. Memory will be allocated runtime through CMA for enabling the multimedia usecases. Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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- 23 5月, 2013 1 次提交
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由 Lorenzo Pieralisi 提交于
This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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- 09 4月, 2013 10 次提交
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由 Jon Hunter 提交于
Add the "ti,gpio-always-on" property to the appropriate GPIO banks to indicate which banks are always powered and will never lose logic state. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Jon Hunter 提交于
Update the DMTIMER compatibility property to reflect the register level compatibilty between devices and update the various OMAP/AM timer bindings with the appropriate compatibility string. By doing this we can add platform specific data applicable to specific timer versions to the driver. For example, errata flags can be populated for the timer versions that are impacted. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Santosh Shilimkar 提交于
Add l3-noc node for OMAP4 and OMAP5 devices. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> [jon-hunter@ti.com: Fix the problem caused by adding 32 to the interrupt number for the L3 interrupts to account for per processor interrupts (PPI) and software generated interrupts (SGI) which typically are mapped to the first 32 interrupts in the ARM GIC. This is not necessary because the first parameter of the ARM GIC interrupt property specifies the GIC interrupt type (ie. SGI, PPI, etc). Hence, fix the interrupt number for the L3 interrupts by substracting 32] Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Sebastien Guiriec 提交于
Populate DMA client information for McBSP DMIC and McPDM periperhal on OMAP2+ devices. Signed-off-by: NSebastien Guiriec <s-guiriec@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Jon Hunter 提交于
The OMAP gpio binding documention [1] states that the #interrupts-cells property for gpio controllers should be 2. Currently, for OMAP3+ devices the #interrupt-cells is set to 1. By setting this property to 2, it allows clients to pass a 2nd parameter indicating the sensitivity (level or edge) and polarity (high or low) of the interrupt. The OMAP gpio controllers support these options and so update the #interrupt-cells property for OMAP3+ devices to 2. [1] Documentation/devicetree/bindings/gpio/gpio-omap.txt Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Jon Hunter 提交于
Add the device-tree node for GPMC on OMAP2, OMAP4 and OMAP5 devices. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Jon Hunter 提交于
Add SDMA controller binding for OMAP2+ devices and populate DMA client information for SPI and MMC peripheral on OMAP3+ devices. Please note that OMAP24xx devices do not have SPI and MMC bindings available yet and so DMA client information is not populated. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Reviewed-by: NFelipe Balbi <balbi@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Kishon Vijay Abraham I 提交于
Add usb otg data node in omap4/omap3 device tree file. Also update the node with board specific setting in omapx-<board>.dts file. The dt data specifies among others the interface type (ULPI or UTMI), mode which is mostly OTG, power that specifies the amount of power this can supply when in host mode. The information about usb otg node is available @ Documentation/devicetree/bindings/usb/omap-usb.txt Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Acked-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Kishon Vijay Abraham I 提交于
Add omap-usb2 data node in omap4 device tree file. Since omap-usb2 is connected to ocp2scp, omap-usb2 dt data is added as a child node of ocp2scp. The information about this data node is availabe @ Documentation/devicetree/bindings/usb/usb-phy.txt Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Acked-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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由 Kishon Vijay Abraham I 提交于
Add omap control usb data in omap4 device tree file. This will have the register address of registers to power on the PHY and to write to mailbox. The information about this data node is available @ Documentation/devicetree/bindings/usb/omap-usb.txt Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>
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- 03 4月, 2013 1 次提交
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由 Roger Quadros 提交于
Adds device nodes for HS USB Host module, TLL module, OHCI and EHCI controllers. CC: Benoît Cousson <b-cousson@ti.com> Signed-off-by: NRoger Quadros <rogerq@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 02 11月, 2012 1 次提交
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由 Jon Hunter 提交于
For OMAP4 devices, timers 5-8 have both a L3 bus address and a Cortex-A9 private bus address. Currently the device-tree source only contains the L3 bus address for these timers. Update these timers to include the Cortex-A9 private address and make the default address the Cortex-A9 private bus address to match the current HWMOD implementation. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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- 29 10月, 2012 4 次提交
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由 Jon Hunter 提交于
Adds the counter-32k timers nodes present in OMAP2/3/4 devices and device-tree binding documentation for OMAP counter-32k. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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由 Jon Hunter 提交于
Add the 12 GP timers nodes present in OMAP2. Add the 12 GP timers nodes present in OMAP3. Add the 11 GP timers nodes present in OMAP4. Add the 7 GP timers nodes present in AM33xx. Add documentation for timer properties specific to OMAP. Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified Vaibhav's original nodes adding information on which timers support a PWM output. V5 changes: - Updated timer register sizes for OMAP2/3/4. - Modified AM335x timer register size to be 1KB instead of 4KB to align with HWMOD. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Acked-Reviewed-&-Tested-By: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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由 Benoit Cousson 提交于
The interrupt-parent attribute does not have to be added in each node since the fmwk will check for the parent as well to get it. Create an interrupt-parent for OMAP2, OMAP3, AM33xx and remove the attributes from every nodes that were using it. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Sebastien Guiriec <s-guiriec@ti.com>
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由 Kishon Vijay Abraham I 提交于
*reg* property for ocp2scp was previously obtained from ti,hwmods property. But that is now explicitly added to the dt node. Also updated the documentation with *reg* info. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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- 11 9月, 2012 1 次提交
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由 Tony Lindgren 提交于
Add pinctrl driver entries for omap2+. These all use the generic pinctrl-single driver for the padconf registers. Cc: devicetree-discuss@lists.ozlabs.org Acked-by: NLinus Walleij <linus.walleij@linaro.org> [tony@atomide.com: updated to drop omap2420.dtsi rename changes] Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 08 9月, 2012 8 次提交
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由 Benoit Cousson 提交于
Thanks to Vaibhav <hvaibhav@ti.com> omap_device fix (ARM: OMAP: omap_device: Fix up resource names when booted with devicetre), we can now specify reg and interrupts using standard device tree attributes. Update the OMAP4 dtsi file with missing reg and interrupts attributes. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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由 Peter Ujfalusi 提交于
In order to get the memory areas by name when booted with DT. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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由 Peter Ujfalusi 提交于
Create the sections describing the McBSP ports to be able to use them via DT. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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由 Benoit Cousson 提交于
Remove some useless comment and move GIC controller outside of the OCP node since it does use the MPU internal bus and not the OCP. This will not change the functionality but will reflect the reality more accurately. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
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由 Santosh Shilimkar 提交于
Add cortex-a9 local timer support for all OMAP4 based SOCs using DT. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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由 Santosh Shilimkar 提交于
Provide PL310 Level 2 Cache Controller Device Tree support for OMAP4 based devices. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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由 Aneesh V 提交于
Device tree data for the EMIF sdram controllers in OMAP4 and LPDDR2 memory devices attached to OMAP4 boards. Reviewed-by: NGrant Likely <grant.likely@secretlab.ca> Tested-by: NLokesh Vutla <lokeshvutla@ti.com> Signed-off-by: NAneesh V <aneesh@ti.com> [santosh.shilimkar@ti.com: Rebased against 3.6-rc] Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> [b-cousson@ti.com: Use label in board to access EMIF nodes] Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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由 Sourav Poddar 提交于
Add keypad data node in omap4 device tree file. Also fill the device tree binding parameters with the required value in "omap4-sdp" dts file. Signed-off-by: NSourav Poddar <sourav.poddar@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com> [b-cousson@ti.com: Re-align the entries and the comments]
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- 22 8月, 2012 1 次提交
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由 Kishon Vijay Abraham I 提交于
Add ocp2scp data node in omap4 device tree file. Acked-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 09 7月, 2012 3 次提交
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由 Peter Ujfalusi 提交于
DMIC IP is used to connect up to 6 digital microphones directly to OMAP. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
McPDM is used on OMAP4 based boards to communicate with an external audio codec (twl6040). Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Xiao Jiang 提交于
Add wdt node to support dt. Signed-off-by: NXiao Jiang <jgq516@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 15 3月, 2012 1 次提交
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由 Rajendra Nayak 提交于
Add OMAP mmc related device tree data for OMAP4. Currenly limited to only omap4-panda and omap4-sdp boards. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
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