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  1. 28 4月, 2007 1 次提交
  3. 13 3月, 2007 2 次提交
    • E
      [PATCH] pci: Repair pci_save/restore_state so we can restore one save many times. · 9f35575d
      由 Eric W. Biederman 提交于 
      Because we do not reserve space for the pci-x and pci-e state in struct
pci dev we need to dynamically allocate it.  However because we need
to support restore being called multiple times after a single save
it is never safe to free the buffers we have allocated to hold the
state.

So this patch modifies the save routines to first check to see
if we have already allocated a state buffer before allocating
a new one.  Then the restore routines are modified to not free
the state after restoring it.  Simple and it fixes some subtle
error path handling bugs, that are hard to test for.
Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
Acked-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      9f35575d
    • E
      [PATCH] msi: Safer state caching. · 392ee1e6
      由 Eric W. Biederman 提交于 
      There are two ways pci_save_state and pci_restore_state are used.  As
helper functions during suspend/resume, and as helper functions around
a hardware reset event.  When used as helper functions around a hardware
reset event there is no reason to believe the calls will be paired, nor
is there a good reason to believe that if we restore the msi state from
before the reset that it will match the current msi state.  Since arch
code may change the msi message without going through the driver, drivers
currently do not have enough information to even know when to call
pci_save_state to ensure they will have msi state in sync with the other
kernel irq reception data structures.

It turns out the solution is straight forward, cache the state in the
existing msi data structures (not the magic pci saved things) and
have the msi code update the cached state each time we write to the hardware.
This means we never need to read the hardware to figure out what the hardware
state should be.

By modifying the caching in this manner we get to remove our save_state
routines and only need to provide restore_state routines.

The only fields that were at all tricky to regenerate were the msi and msi-x
control registers and the way we regenerate them currently is a bit dependent
upon assumptions on how we use the allow msi registers to be configured and used
making the code a little bit brittle.  If we ever change what cases we allow
or how we configure the msi bits we can address the fragility then.
Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
Acked-by: NAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      392ee1e6
  5. 10 3月, 2007 1 次提交
  7. 05 3月, 2007 1 次提交
    • E
      [PATCH] msi: sanely support hardware level msi disabling · f5f2b131
      由 Eric W. Biederman 提交于 
      In some cases when we are not using msi we need a way to ensure that the
hardware does not have an msi capability enabled.  Currently the code has been
calling disable_msi_mode to try and achieve that.  However disable_msi_mode
has several other side effects and is only available when msi support is
compiled in so it isn't really appropriate.

Instead this patch implements pci_msi_off which disables all msi and msix
capabilities unconditionally with no additional side effects.

pci_disable_device was redundantly clearing the bus master enable flag and
clearing the msi enable bit.  A device that is not allowed to perform bus
mastering operations cannot generate intx or msi interrupt messages as those
are essentially a special case of dma, and require bus mastering.  So the call
in pci_disable_device to disable msi capabilities was redundant.

quirk_pcie_pxh also called disable_msi_mode and is updated to use pci_msi_off.
Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
Cc: Michael Ellerman <michael@ellerman.id.au>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      f5f2b131
  9. 17 2月, 2007 2 次提交
  11. 10 2月, 2007 1 次提交
    • T
      devres: device resource management · 9ac7849e
      由 Tejun Heo 提交于 
      Implement device resource management, in short, devres.  A device
driver can allocate arbirary size of devres data which is associated
with a release function.  On driver detach, release function is
invoked on the devres data, then, devres data is freed.

devreses are typed by associated release functions.  Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function.  Both usages are
supported.

devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).

This patch adds devres core including documentation and the following
managed interfaces.

* alloc/free	: devm_kzalloc(), devm_kzfree()
* IO region	: devm_request_region(), devm_release_region()
* IRQ		: devm_request_irq(), devm_free_irq()
* DMA		: dmam_alloc_coherent(), dmam_free_coherent(),
		  dmam_declare_coherent_memory(), dmam_pool_create(),
		  dmam_pool_destroy()
* PCI		: pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap		: devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
		  devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
		  pcim_iomap(), pcim_iounmap()
Signed-off-by: NTejun Heo <htejun@gmail.com>
Signed-off-by: NJeff Garzik <jeff@garzik.org>
      9ac7849e
  13. 08 2月, 2007 8 次提交
  15. 12 1月, 2007 1 次提交
    • B
      [PATCH] increment pos before looking for the next cap in __pci_find_next_ht_cap · 47a4d5be
      由 Brice Goglin 提交于 
      While testing 2.6.20-rc3 on a machine with some CK804 chipsets, we noticed
that quirk_nvidia_ck804_msi_ht_cap() was not detecting HT MSI capabilities
anymore.  It is actually caused by the MSI mapping on the root chipset
being the 2nd HT capability in the chain.  pci_find_ht_capability() does
not seem to find anything but the first HT cap correctly, because it
forgets to increment the position before looking for the next cap.  The
following patch seems to fix it.

At least, this proves that having a ttl is good idea since the machine
would have been stucked in an infinite loop if we didn't have a ttl :)

We have to pass pos + PCI_CAP_LIST_NEXT to __pci_find_next_cap_ttl to
get the next HT cap instead of the same one again.
Signed-off-by: NBrice Goglin <brice@myri.com>
Signed-off-by: NAndrew J. Gallatin <gallatin@myri.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      47a4d5be
  17. 21 12月, 2006 2 次提交
  19. 02 12月, 2006 4 次提交
    • I
      PCI: switch pci_{enable,disable}_device() to be nestable · bae94d02
      由 Inaky Perez-Gonzalez 提交于 
      Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().

The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm]. 

In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers. 

However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:

1. driverA     starts     pci_enable_device()
2. driverB     starts     pci_enable_device()
3. driverA     shutdown   pci_disable_device()
4. driverB     shutdown   pci_disable_device()

between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.

By using this modification, the device won't be disabled until all the
callers to enable() have called disable().

This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.

We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: NInaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      bae94d02
    • M
      PCI: Replace HAVE_ARCH_PCI_MWI with PCI_DISABLE_MWI · edb2d97e
      由 Matthew Wilcox 提交于 
      pSeries is the only architecture left using HAVE_ARCH_PCI_MWI and it's
really inappropriate for its needs.  It really wants to disable MWI
altogether.  So here are a pair of stub implementations for pci_set_mwi
and pci_clear_mwi.

Also rename pci_generic_prep_mwi to pci_set_cacheline_size since that
better reflects what it does.
Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
Cc: Paul Mackerras <paulus@samba.org>
Acked-by: NJeff Garzik <jeff@garzik.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      edb2d97e
    • M
      PCI: Use pci_generic_prep_mwi on sparc64 · ebf5a248
      由 Matthew Wilcox 提交于 
      The setting of the CACHE_LINE_SIZE register in sparc64's pci
initialisation code isn't quite adequate as the device may have
incompatible requirements.  The generic code tests for this, so switch
sparc64 over to using it.

Since sparc64 has different L1 cache line size and PCI cache line size,
it would need to override the generic code like i386 and ia64 do.  We
know what the cache line size is at compile time though, so introduce a
new optional constant PCI_CACHE_LINE_BYTES.
Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
Signed-off-by: NDavid Miller <davem@davemloft.net>
Acked-by: NJeff Garzik <jeff@garzik.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      ebf5a248
    • S
      PCI: save/restore PCI-X state · cc692a5f
      由 Stephen Hemminger 提交于 
      Shouldn't PCI-X state be saved/restored?  No device really needs this
right now. qla24xx (fc HBA) and mthca (infiniband) don't do suspend, 
and sky2 resets its tweaks when links are brought up.
Signed-off-by: NStephen Hemminger <shemminger@osdl.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      cc692a5f
  21. 27 9月, 2006 1 次提交
  23. 26 9月, 2006 2 次提交
  25. 13 7月, 2006 1 次提交
    • K
      [PATCH] PCI: PCIE power management quirk · ffadcc2f
      由 Kristen Carlson Accardi 提交于 
      When changing power states from D0->DX and then from DX->D0, some
Intel PCIE chipsets will cause a device reset to occur.  This will
cause problems for any D State other than D3, since any state
information that the driver will expect to be present coming from
a D1 or D2 state will have been cleared.  This patch addes a
flag to the pci_dev structure to indicate that devices should
not use states D1 or D2, and will set that flag for the affected
chipsets.  This patch also modifies pci_set_power_state() so that
when a device driver tries to set the power state on
a device that is downstream from an affected chipset, or on one
of the affected devices it only allows state changes to or
from D0 & D3.  In addition, this patch allows the delay time
between D3->D0 to be changed via a quirk.  These chipsets also
need additional time to change states beyond the normal 10ms.
Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      ffadcc2f
  27. 28 6月, 2006 1 次提交
  29. 27 6月, 2006 1 次提交
  31. 22 6月, 2006 2 次提交
  33. 12 6月, 2006 2 次提交
  35. 24 5月, 2006 1 次提交
  37. 15 4月, 2006 2 次提交
  39. 24 3月, 2006 4 次提交