提交 4946aa9f 编写于 作者: W wangyuan46 提交者: Yang Yingliang

rde: fixup some problems from codereview

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

In this patch, we do some changes as below:
1.add bme/pm/sriov flr disable config
2.optimize print format
3.add fault proc of task error
Signed-off-by: Nwangyuan46 <wangyuan46@huawei.com>
Reviewed-by: Nlingmingqiang <lingmingqiang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 9a93c260
......@@ -45,12 +45,6 @@ struct hisi_rde {
#define RDE_MEM_SAVE_SHIFT 2
#define RDE_BUF_TYPE_SHIFT 3
#define SGL_DATA_OFFSET_SHIFT 8
#define RDE_COEF_GF_SHIFT 32
#define RDE_LBA_BLK 8
#define RDE_LBA_DWORD_CNT 5
#define DIF_CHK_GRD_CTRL_SHIFT 4
#define DIF_CHK_REF_CTRL_SHIFT 32
#define DIF_LBA_SHIFT 32
#define DIF_GEN_PAD_CTRL_SHIFT 32
#define DIF_GEN_REF_CTRL_SHIFT 35
#define DIF_GEN_APP_CTRL_SHIFT 38
......@@ -76,18 +70,26 @@ struct hisi_rde {
#define RDE_DONE_SHIFT 7
#define RDE_PER_SRC_COEF_SIZE 32
#define RDE_PER_SRC_COEF_TIMES 4
#define RDE_UPD_GN_FLAG 0x80
#define RDE_UPD_PARITY_SHIFT 7
#define RDE_TASK_TMOUT_MS 10000
#define RDE_GN_WITH_MODE(column, mode, parity) \
((u8)column + ((ACC_OPT_UPD ^ mode) ? 0 : (0x80 & (parity << 7))))
#define RDE_GN_CNT(i) (((i + 1) % 2 == 0) ? ((i + 1) >> 1) : ((i + 2) >> 1))
#define RDE_GN_FLAG(i) (((i + 1) % 2 == 0) ? 2 : 1)
#define RDE_GN_SHIFT(x) (RDE_COEF_GF_SHIFT * (x == 1 ? 1 : 0))
#define RDE_CLR_CNT(i) (((i - 1) / RDE_LBA_BLK + 1) * RDE_LBA_DWORD_CNT)
#define RDE_LBA_INFO_CNT(i) ((i % 2 == 0) ? (i >> 1) : ((i - 1) >> 1))
#define RDE_LBA_SHIFT_MSK(i) ((i % 2 == 0) ? 1 : 0)
#define RDE_GN_SHIFT(i) (32 * (i == 1 ? 1 : 0))
#define RDE_CHK_CTRL_CNT(i) ((i / 8) * 5)
#define RDE_LBA_CNT(i) ((i / 8 + 1) + \
((i % 2 == 0) ? (i >> 1) : ((i - 1) >> 1)))
#define RDE_CHK_CTRL_VALUE(grd, ref, i) \
((u64)(grd << 4 | ref) << (8 * (i % 8)))
#define RDE_LBA_SHIFT(i) (32 * ((i % 2) ^ 1))
struct hisi_rde_hw_error {
u8 status;
u32 int_msk;
const char *msg;
};
/* src data addr table, should be 64byte aligned */
struct rde_src_tbl {
......@@ -125,6 +127,7 @@ struct hisi_rde_msg {
struct raid_ec_ctrl *udata;
struct completion completion;
u32 req_id;
int result;
};
/* rde ctx structure, acc_init api can alloc and init this structure */
......@@ -148,6 +151,40 @@ struct rde_type {
u8 alg_type;
};
/* RDE hardware error status */
enum {
RDE_STATUS_NULL = 0,
RDE_BD_ADDR_NO_ALIGN = 0x2,
RDE_BD_RD_BUS_ERR = 0x3,
RDE_IO_ABORT = 0x4,
RDE_BD_ERR = 0x5,
RDE_ECC_ERR = 0x6,
RDE_SGL_ADDR_ERR = 0x7,
RDE_SGL_PARA_ERR = 0x8,
RDE_DATA_RD_BUS_ERR = 0x1c,
RDE_DATA_WR_BUS_ERR = 0x1d,
RDE_CRC_CHK_ERR = 0x1e,
RDE_REF_CHK_ERR = 0x1f,
RDE_DISK0_VERIFY = 0x20,
RDE_DISK1_VERIFY = 0x21,
RDE_DISK2_VERIFY = 0x22,
RDE_DISK3_VERIFY = 0x23,
RDE_DISK4_VERIFY = 0x24,
RDE_DISK5_VERIFY = 0x25,
RDE_DISK6_VERIFY = 0x26,
RDE_DISK7_VERIFY = 0x27,
RDE_DISK8_VERIFY = 0x28,
RDE_DISK9_VERIFY = 0x29,
RDE_DISK10_VERIFY = 0x2a,
RDE_DISK11_VERIFY = 0x2b,
RDE_DISK12_VERIFY = 0x2c,
RDE_DISK13_VERIFY = 0x2d,
RDE_DISK14_VERIFY = 0x2e,
RDE_DISK15_VERIFY = 0x2f,
RDE_DISK16_VERIFY = 0x30,
RDE_CHAN_TMOUT = 0x31,
};
/* RDE algorithm types */
enum {
MPCC = 0x00, /* EC */
......@@ -262,15 +299,27 @@ static inline void rde_table_dump(const struct hisi_rde_msg *req)
for (i = 0; i < SRC_ADDR_TABLE_NUM; i++) {
if (req->src_addr->content[i])
pr_info("src addr info[%d] content is 0x%llx\n",
pr_info("Table0 info[%d] is 0x%llx.\n",
i, req->src_addr->content[i]);
}
for (i = 0; i < SRC_DIF_TABLE_NUM; i++) {
if (req->src_tag_addr->content[i])
pr_info("Table1 info[%d] is 0x%llx.\n",
i, req->src_tag_addr->content[i]);
}
for (i = 0; i < DST_ADDR_TABLE_NUM; i++) {
if (req->dst_addr->content[i])
pr_info("dst addr info[%d] content is 0x%llx\n",
pr_info("Table2 info[%d] is 0x%llx.\n",
i, req->dst_addr->content[i]);
}
for (i = 0; i < DST_DIF_TABLE_NUM; i++) {
if (req->dst_tag_addr->content[i])
pr_info("Table3 info[%d] is 0x%llx.\n",
i, req->dst_tag_addr->content[i]);
}
}
struct hisi_rde *find_rde_device(int node);
......
......@@ -308,7 +308,7 @@ struct acc_dif {
* @input_block: number of sector
* @data_len: data len of per disk, block_size (with dif)* input_block
* @buf_type: denoted by ACC_BUF_TYPE_E
* @src_dif��dif information of source disks
* @src_dif£»dif information of source disks
* @dst_dif: dif information of dest disks
* @cm_load: coe_matrix reload control, 0: do not load, 1: load
* @cm_len: length of loaded coe_matrix, equal to src_num
......@@ -361,42 +361,14 @@ struct acc_ctx {
};
/**
*
* @brief set T10 CRC seed.
*
* @param [in] seed T10 CRC seed.
* @retval 0 is success, else is a negative number that is error code.
*
* @note
*
* @brief return value.
*/
int acc_set_pi_crc_seed(uint16_t seed);
/**
*
* @brief set the PRP page size.
*
* @param [in] page_size typical values: 4096 bytes, 8192 bytes.
* @retval 0 is success, else is a negative number that is error code.
*
* @note
* Not supported yet
*
*/
int acc_set_prp_mem_page_size(uint32_t page_size_byte);
/**
*
* @brief set the offset of SGE related to SGL.
*
* @param [in] offset typical values: 32 bytes, 64 bytes.
* @retval 0 is success, else is a negative number that is error code.
*
* @note
* Not supported yet
*
*/
int acc_set_sge_offset_from_sgl(uint32_t offset_byte);
enum ACC_STATUS_E {
ACC_SUCCESS = 0,
ACC_INVALID_PARAM = (-103), /*!< parameter error */
ACC_RDE_DIF_ERR = (-113), /*!< Input or Output dif check error */
ACC_RDE_DISK_VERIFY_ERR = (-114) /*!< Output data verify error */
};
/**
*
......
......@@ -23,7 +23,7 @@ static inline u32 sgl_addr_cnt(struct sgl_hw *sgl)
struct sgl_hw *cur_sgl = sgl;
if (!sgl) {
pr_err("[%s] sgl address is NULL", __func__);
pr_err("[%s] Sgl address is NULL.\n", __func__);
return 0;
}
......@@ -45,22 +45,22 @@ int acc_sgl_dump(struct sgl_hw *data)
struct sgl_entry_hw *entry;
if (unlikely(!data->entry_sum_in_sgl)) {
pr_err("error! The entrysum of sgl is zero.\n");
pr_err("Error! The entrysum of sgl is zero.\n");
return -EINVAL;
}
cnt_entries = sgl_addr_cnt(data);
pr_info("sgl entries:%d\n", cnt_entries);
pr_info("Sgl entries:%d.\n", cnt_entries);
for (cur_sgl = data; cur_sgl; ) {
pr_info("sgl addr: 0x%pK\n", cur_sgl);
pr_info("nextSgl: 0x%pK\n", cur_sgl->next);
pr_info("entrySumInChain: %u\n", cur_sgl->entry_sum_in_chain);
pr_info("entrySumInSgl: %u\n", cur_sgl->entry_sum_in_sgl);
pr_info("Sgl addr: 0x%pK.\n", cur_sgl);
pr_info("NextSgl: 0x%pK.\n", cur_sgl->next);
pr_info("EntrySumInChain: %u.\n", cur_sgl->entry_sum_in_chain);
pr_info("EntrySumInSgl: %u.\n", cur_sgl->entry_sum_in_sgl);
entry = cur_sgl->entries;
for (i = 0; (i < cur_sgl->entry_sum_in_sgl &&
entry->buf); i++) {
pr_info("entries[%d]:addr = 0x%pK\n", i, entry->buf);
pr_info("Entries[%d]:addr = 0x%pK.\n", i, entry->buf);
entry++;
}
if (cur_sgl->next)
......@@ -121,20 +121,20 @@ int acc_sgl_virt_to_phys(struct pci_dev *pdev, struct sgl_hw *data,
struct scatterlist *sglist;
if (!data) {
pr_err("[%s] para sgl_s is NULL.\n", __func__);
pr_err("[%s] Para sgl_s is NULL.\n", __func__);
return -EINVAL;
}
if (unlikely(!data->entry_sum_in_sgl) ||
data->entry_sum_in_sgl > data->entry_num_in_sgl) {
pr_err("[%s] para sge num is wrong.\n", __func__);
pr_err("[%s] Para sge num is wrong.\n", __func__);
return -EINVAL;
}
addr_cnt = sgl_addr_cnt(data);
sglist = kcalloc(addr_cnt, sizeof(*sglist), GFP_KERNEL);
if (unlikely(!sglist)) {
pr_err("[%s] malloc sglist fail.\n", __func__);
pr_err("[%s] Malloc sglist fail.\n", __func__);
return -ENOMEM;
}
......@@ -162,7 +162,7 @@ int acc_sgl_phys_to_virt(struct pci_dev *pdev, void *sglist_head,
int ret = -EFAULT;
if (!sglist_head) {
pr_err("[%s] para sglist_head is NULL.\n", __func__);
pr_err("[%s] Para sglist_head is NULL.\n", __func__);
return -EINVAL;
}
......@@ -177,7 +177,7 @@ int acc_sgl_phys_to_virt(struct pci_dev *pdev, void *sglist_head,
entry->buf); i++) {
sg = sg_next(sg);
if (unlikely(!sg)) {
pr_err("[%s][%d]scatterlist happens to be NULL.\n",
pr_err("[%s][%d]Scatterlist happens to be NULL.\n",
__func__, __LINE__);
goto FAIL;
}
......@@ -190,7 +190,7 @@ int acc_sgl_phys_to_virt(struct pci_dev *pdev, void *sglist_head,
if (cur_sgl->next) {
sg = sg_next(sg);
if (unlikely(!sg)) {
pr_err("[%s][%d]scatterlist happens to be NULL.\n",
pr_err("[%s][%d]Scatterlist happens to be NULL.\n",
__func__, __LINE__);
goto FAIL;
}
......
......@@ -108,30 +108,25 @@ struct hisi_rde_resource {
struct list_head list;
};
struct hisi_rde_hw_error {
u32 int_msk;
const char *msg;
};
static const struct hisi_rde_hw_error rde_hw_error[] = {
{.int_msk = BIT(0), .msg = "rde_ecc_1bitt_err"},
{.int_msk = BIT(1), .msg = "rde_ecc_2bit_err"},
{.int_msk = BIT(2), .msg = "rde_stat_mgmt_state_timeout_err"},
{.int_msk = BIT(3), .msg = "rde_data_wr_state_timeout_err"},
{.int_msk = BIT(4), .msg = "rde_alg_state_timeout_err"},
{.int_msk = BIT(5), .msg = "rde_data_ar_state_timeout_err"},
{.int_msk = BIT(6), .msg = "rde_bd_mgmt_state_timeout_err"},
{.int_msk = BIT(7), .msg = "rde_list_parse_ar_state_timeout_err"},
{.int_msk = BIT(8), .msg = "rde_bd_prefetch_state_timeout_err"},
{.int_msk = BIT(9), .msg = "rde_dst_buf_parse_state_timeout_err"},
{.int_msk = BIT(10), .msg = "rde_src_buf_parse_state_timeout_err"},
{.int_msk = BIT(11), .msg = "rde_chn_timeout_err"},
{.int_msk = BIT(12), .msg = "rde_bd_bresp_err"},
{.int_msk = BIT(13), .msg = "rde_data_bresp_err"},
{.int_msk = BIT(14), .msg = "rde_data_rresp_err"},
{.int_msk = BIT(15), .msg = "rde_sgl_rresp_err"},
{.int_msk = BIT(16), .msg = "rde_list_rresp_err"},
{.int_msk = BIT(17), .msg = "rde_bd_rresp_err"},
{.int_msk = BIT(0), .msg = "Rde_ecc_1bitt_err"},
{.int_msk = BIT(1), .msg = "Rde_ecc_2bit_err"},
{.int_msk = BIT(2), .msg = "Rde_stat_mgmt_state_timeout_err"},
{.int_msk = BIT(3), .msg = "Rde_data_wr_state_timeout_err"},
{.int_msk = BIT(4), .msg = "Rde_alg_state_timeout_err"},
{.int_msk = BIT(5), .msg = "Rde_data_ar_state_timeout_err"},
{.int_msk = BIT(6), .msg = "Rde_bd_mgmt_state_timeout_err"},
{.int_msk = BIT(7), .msg = "Rde_list_parse_ar_state_timeout_err"},
{.int_msk = BIT(8), .msg = "Rde_bd_prefetch_state_timeout_err"},
{.int_msk = BIT(9), .msg = "Rde_dst_buf_parse_state_timeout_err"},
{.int_msk = BIT(10), .msg = "Rde_src_buf_parse_state_timeout_err"},
{.int_msk = BIT(11), .msg = "Rde_chn_timeout_err"},
{.int_msk = BIT(12), .msg = "Rde_bd_bresp_err"},
{.int_msk = BIT(13), .msg = "Rde_data_bresp_err"},
{.int_msk = BIT(14), .msg = "Rde_data_rresp_err"},
{.int_msk = BIT(15), .msg = "Rde_sgl_rresp_err"},
{.int_msk = BIT(16), .msg = "Rde_list_rresp_err"},
{.int_msk = BIT(17), .msg = "Rde_bd_rresp_err"},
{ /* sentinel */ }
};
......@@ -217,7 +212,7 @@ static int pf_q_num_set(const char *val, const struct kernel_param *kp)
if (unlikely(!pdev)) {
q_num = min_t(u32, HRDE_QUEUE_NUM_V1, HRDE_QUEUE_NUM_V2);
pr_info
("No device found currently, suppose queue number is %d\n",
("No device found currently, suppose queue number is %d.\n",
q_num);
} else {
rev_id = pdev->revision;
......@@ -378,7 +373,7 @@ static int current_qm_write(struct ctrl_debug_file *file, u32 val)
u32 tmp;
if (val > 0) {
pr_err("function id should be smaller than 0.\n");
pr_err("Function id should be smaller than 0.\n");
return -EINVAL;
}
......@@ -409,7 +404,7 @@ static int current_bd_write(struct ctrl_debug_file *file, u32 val)
u32 tmp = 0;
if (val >= (HRDE_SQE_SIZE / sizeof(u32))) {
pr_err("width index should be smaller than 16.\n");
pr_err("Width index should be smaller than 16.\n");
return -EINVAL;
}
......@@ -640,6 +635,9 @@ static void hisi_rde_set_user_domain_and_cache(struct hisi_rde *hisi_rde)
/* qm cache */
writel(AXI_M_CFG, hisi_rde->qm.io_base + QM_AXI_M_CFG);
writel(AXI_M_CFG_ENABLE, hisi_rde->qm.io_base + QM_AXI_M_CFG_ENABLE);
/* disable BME/PM/SRIOV FLR*/
writel(PEH_AXUSER_CFG, hisi_rde->qm.io_base + QM_PEH_AXUSER_CFG);
writel(PEH_AXUSER_CFG_ENABLE, hisi_rde->qm.io_base +
QM_PEH_AXUSER_CFG_ENABLE);
......@@ -727,7 +725,7 @@ static int hisi_rde_qm_pre_init(struct hisi_qm *qm, struct pci_dev *pdev)
qm->sqe_size = HRDE_SQE_SIZE;
qm->dev_name = hisi_rde_name;
qm->fun_type = QM_HW_PF;
qm->algs = "rde\n";
qm->algs = "ec\n";
switch (uacce_mode) {
case UACCE_MODE_NOUACCE:
......@@ -791,31 +789,31 @@ static int hisi_rde_probe(struct pci_dev *pdev, const struct pci_device_id *id)
qm = &hisi_rde->qm;
ret = hisi_rde_qm_pre_init(qm, pdev);
if (ret) {
dev_err(&pdev->dev, "Failed to pre init qm!\n");
dev_err(&pdev->dev, "Pre init qm failed!\n");
return ret;
}
ret = hisi_qm_init(qm);
if (ret) {
dev_err(&pdev->dev, "Failed to init qm!\n");
dev_err(&pdev->dev, "Init qm failed!\n");
return ret;
}
ret = hisi_rde_pf_probe_init(hisi_rde);
if (ret) {
dev_err(&pdev->dev, "Failed to init pf!\n");
dev_err(&pdev->dev, "Init pf failed!\n");
goto err_qm_uninit;
}
ret = hisi_qm_start(qm);
if (ret) {
dev_err(&pdev->dev, "Failed to start qm!\n");
dev_err(&pdev->dev, "Start qm failed!\n");
goto err_qm_uninit;
}
ret = hisi_rde_debugfs_init(hisi_rde);
if (ret)
dev_warn(&pdev->dev, "Failed to init debugfs!\n");
dev_warn(&pdev->dev, "Init debugfs failed!\n");
hisi_rde_add_to_list(hisi_rde);
hisi_rde->rde_list_lock = &hisi_rde_list_lock;
......@@ -851,25 +849,29 @@ static void hisi_rde_hw_error_log(struct hisi_rde *hisi_rde, u32 err_sts)
while (err->msg) {
if (err->int_msk & err_sts)
dev_err(dev, "%s [error status=0x%x] found\n",
err->msg, err->int_msk);
dev_err_ratelimited(dev,
"[%s] [Error status=0x%x] found.\n",
err->msg, err->int_msk);
err++;
}
if (HRDE_ECC_2BIT_ERR & err_sts) {
err_val = (readl(hisi_rde->qm.io_base + HRDE_ERR_CNT)
& HRDE_ECC_2BIT_CNT_MSK);
dev_err(dev, "rde ecc 2bit sram num=0x%x\n", err_val);
dev_err_ratelimited(dev,
"Rde ecc 2bit sram num=0x%x.\n", err_val);
}
if (HRDE_STATE_INT_ERR & err_sts) {
for (i = 0; i < HRDE_DFX_NUM; i++) {
dev_err(dev, "%s=0x%x\n", hrde_dfx_regs[i].name,
dev_err_ratelimited(dev, "%s=0x%x\n",
hrde_dfx_regs[i].name,
readl(hisi_rde->qm.io_base +
hrde_dfx_regs[i].offset));
}
for (i = 0; i < HRDE_OOO_DFX_NUM; i++) {
dev_err(dev, "%s=0x%x\n", hrde_ooo_dfx_regs[i].name,
dev_err_ratelimited(dev, "%s=0x%x\n",
hrde_ooo_dfx_regs[i].name,
readl(hisi_rde->qm.io_base +
hrde_ooo_dfx_regs[i].offset));
}
......@@ -900,7 +902,7 @@ static pci_ers_result_t hisi_rde_hw_error_process(struct pci_dev *pdev)
pci_ers_result_t qm_ret, rde_ret, ret;
if (!hisi_rde) {
dev_err(dev, "Can't recover rde-error at dev init\n");
dev_err(dev, "Can't recover rde-error at dev init.\n");
return PCI_ERS_RESULT_NONE;
}
......@@ -943,7 +945,7 @@ static int hisi_rde_controller_reset_prepare(struct hisi_rde *hisi_rde)
ret = hisi_qm_stop(qm, QM_SOFT_RESET);
if (ret) {
dev_err(&pdev->dev, "Fails to stop QM!\n");
dev_err(&pdev->dev, "Stop QM failed!\n");
return ret;
}
......@@ -951,7 +953,7 @@ static int hisi_rde_controller_reset_prepare(struct hisi_rde *hisi_rde)
if (qm->use_uacce) {
ret = uacce_hw_err_isolate(&qm->uacce);
if (ret) {
dev_err(&pdev->dev, "Fails to isolate hw err!\n");
dev_err(&pdev->dev, "Isolate hw err failed!\n");
return ret;
}
}
......@@ -976,7 +978,7 @@ static int hisi_rde_soft_reset(struct hisi_rde *hisi_rde)
/* Disable PEH MSI */
ret = hisi_qm_set_msi(qm, HRDE_DISABLE);
if (ret) {
dev_err(dev, "Fails to disable peh msi bit.\n");
dev_err(dev, "Disable peh msi bit failed.\n");
return ret;
}
......@@ -997,7 +999,7 @@ static int hisi_rde_soft_reset(struct hisi_rde *hisi_rde)
/* Disable PF MSE bit */
ret = hisi_qm_set_pf_mse(qm, HRDE_DISABLE);
if (ret) {
dev_err(dev, "Fails to disable pf mse bit.\n");
dev_err(dev, "Disable pf mse bit failed.\n");
return ret;
}
......@@ -1033,14 +1035,14 @@ static int hisi_rde_controller_reset_done(struct hisi_rde *hisi_rde)
/* Enable PEH MSI */
ret = hisi_qm_set_msi(qm, HRDE_ENABLE);
if (ret) {
dev_err(&pdev->dev, "Fails to enable peh msi bit!\n");
dev_err(&pdev->dev, "Enable peh msi bit failed!\n");
return ret;
}
/* Enable PF MSE bit */
ret = hisi_qm_set_pf_mse(qm, HRDE_ENABLE);
if (ret) {
dev_err(&pdev->dev, "Fails to enable pf mse bit!\n");
dev_err(&pdev->dev, "Enable pf mse bit failed!\n");
return ret;
}
......@@ -1049,7 +1051,7 @@ static int hisi_rde_controller_reset_done(struct hisi_rde *hisi_rde)
ret = hisi_qm_restart(qm);
if (ret) {
dev_err(&pdev->dev, "Failed to start QM!\n");
dev_err(&pdev->dev, "Start QM failed!\n");
return -EPERM;
}
......@@ -1061,7 +1063,7 @@ static int hisi_rde_controller_reset(struct hisi_rde *hisi_rde)
struct device *dev = &hisi_rde->qm.pdev->dev;
int ret;
dev_info(dev, "Controller resetting...\n");
dev_info_ratelimited(dev, "Controller resetting...\n");
ret = hisi_rde_controller_reset_prepare(hisi_rde);
if (ret)
......@@ -1069,7 +1071,7 @@ static int hisi_rde_controller_reset(struct hisi_rde *hisi_rde)
ret = hisi_rde_soft_reset(hisi_rde);
if (ret) {
dev_err(dev, "Controller reset failed (%d)\n", ret);
dev_err(dev, "Controller reset failed (%d).\n", ret);
return ret;
}
......@@ -1078,7 +1080,7 @@ static int hisi_rde_controller_reset(struct hisi_rde *hisi_rde)
return ret;
clear_bit(HISI_RDE_RESET, &hisi_rde->status);
dev_info(dev, "Controller reset complete\n");
dev_info_ratelimited(dev, "Controller reset complete.\n");
return 0;
}
......@@ -1097,7 +1099,7 @@ static void hisi_rde_ras_proc(struct work_struct *work)
ret = hisi_rde_hw_error_process(pdev);
if (ret == PCI_ERS_RESULT_NEED_RESET)
if (hisi_rde_controller_reset(hisi_rde))
dev_err(&pdev->dev, "hisi_rde reset fail.\n");
dev_err(&pdev->dev, "Hisi_rde reset fail.\n");
}
......@@ -1115,7 +1117,7 @@ int hisi_rde_abnormal_fix(struct hisi_qm *qm)
hisi_rde = pci_get_drvdata(pdev);
if (!hisi_rde) {
dev_err(&pdev->dev, "hisi_rde is NULL.\n");
dev_err(&pdev->dev, "Hisi_rde is NULL.\n");
return -EINVAL;
}
......@@ -1168,7 +1170,7 @@ static void hisi_rde_reset_prepare(struct pci_dev *pdev)
ret = hisi_qm_stop(qm, QM_FLR);
if (ret) {
dev_err(&pdev->dev, "Fails to stop QM!\n");
dev_err(&pdev->dev, "Stop QM failed!\n");
return;
}
......@@ -1197,7 +1199,7 @@ static void hisi_rde_reset_done(struct pci_dev *pdev)
ret = hisi_qm_restart(qm);
if (ret) {
dev_err(&pdev->dev, "Failed to start QM!\n");
dev_err(&pdev->dev, "Start QM failed!\n");
goto flr_done;
}
......@@ -1244,12 +1246,12 @@ static int __init hisi_rde_init(void)
ret = pci_register_driver(&hisi_rde_pci_driver);
if (ret < 0) {
pr_err("Failed to register pci driver.\n");
pr_err("Register pci driver failed.\n");
goto err_pci;
}
if (list_empty(&hisi_rde_list)) {
pr_err("no rde device.\n");
pr_err("No rde device.\n");
ret = -ENODEV;
goto err_probe_device;
}
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册