net: hns3: code optimizaition of hclge_handle_hw_ras_error()

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

This patch syncronizes some difference from kernel-dev branch,
which optimizes hclge_handle_hw_ras_error() to make the code logic
clearer.
1. If there was no NIC or Roce RAS when we read
HCLGE_RAS_PF_OTHER_INT_STS_REG, we return directly.
2. Because NIC and Roce RAS may occurs at the same time, so we should
check value of revision at first before we handle Roce RAS instead
of only checking it in branch of no NIC RAS is detected.
3. Check HCLGE_STATE_RST_HANDLING each time before we want to return
PCI_ERS_RESULT_NEED_RESET.
4. Remove checking of HCLGE_RAS_REG_NFE_MASK and
HCLGE_RAS_REG_ROCEE_ERR_MASK because if hw_err_reset_req is not
zero, it proves that we have set it in handling of NIC or Roce RAS.
5. Remove override_pci_need_reset, because hw_err_reset_req can be
used to record reset level that we need to recover from a RAS error.

Feature or Bugfix:Bugfix
Signed-off-by: NWeihang Li <liweihang@hisilicon.com>
Signed-off-by: NYufeng Mo <moyufeng@huawei.com>
Reviewed-by: Ntanhuazhong <tanhuazhong@huawei.com>
Reviewed-by: Nlipeng <lipeng321@huawei.com>
Reviewed-by: NYunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/net/ethernet/hisilicon/hns3/hnae3.h

@@ -230,8 +230,6 @@ struct hnae3_ae_dev {
 	const struct hnae3_ae_ops *ops;
 	struct list_head node;
 	u32 flag;
-	/* workaround to stop multiple reset happening */
-	u8 override_pci_need_reset;
 	unsigned long hw_err_reset_req;
 	enum hnae3_reset_type reset_type;
 	void *priv;

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

@@ -2215,7 +2215,7 @@ static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
 	/* request the reset */
 	if (ops->reset_event && ops->get_reset_level &&
 	    ops->set_default_reset_request) {
-		if (!ae_dev->override_pci_need_reset) {
+		if (ae_dev->hw_err_reset_req) {
 			reset_type = ops->get_reset_level(ae_dev,
 						&ae_dev->hw_err_reset_req);
 			ops->set_default_reset_request(ae_dev, reset_type);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

@@ -1677,6 +1677,8 @@ pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev)
 	if (status & HCLGE_RAS_REG_NFE_MASK ||
 	    status & HCLGE_RAS_REG_ROCEE_ERR_MASK)
 		ae_dev->hw_err_reset_req = 0;
+	else
+		goto out;
 
 	/* Handling Non-fatal HNS RAS errors */
 	if (status & HCLGE_RAS_REG_NFE_MASK) {
@@ -1689,27 +1691,19 @@ pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev)
 			if (ret)
 				return PCI_ERS_RESULT_RECOVERED;
 		}
-	} else {
-		if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
-		    hdev->pdev->revision < 0x21) {
-			ae_dev->override_pci_need_reset = 1;
-			return PCI_ERS_RESULT_RECOVERED;
-		}
 	}
 
-	if (status & HCLGE_RAS_REG_ROCEE_ERR_MASK) {
-		dev_err(dev, "ROCEE uncorrected RAS error identified\n");
+	/* Handling Non-fatal Rocee RAS errors */
+	if (hdev->pdev->revision >= 0x21 &&
+	    status & HCLGE_RAS_REG_ROCEE_ERR_MASK) {
+		dev_err(dev, "ROCEE Non-Fatal RAS error identified\n");
 		hclge_handle_rocee_ras_error(ae_dev);
 	}
 
-	if ((status & HCLGE_RAS_REG_NFE_MASK ||
-	     status & HCLGE_RAS_REG_ROCEE_ERR_MASK) &&
-	     ae_dev->hw_err_reset_req) {
-		ae_dev->override_pci_need_reset = 0;
+	if (ae_dev->hw_err_reset_req)
 		return PCI_ERS_RESULT_NEED_RESET;
-	}
-	ae_dev->override_pci_need_reset = 1;
 
+out:
 	return PCI_ERS_RESULT_RECOVERED;
 }