net: hns3: fix VF interrupt clearing error for revision 0x20

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

For revision 0x21, interrupt clear register is writing 0 clear
register, it means write 0 will clear the bit, write 1 make no
sence. So should just write 0 to the interrupt bit, other bits
keep 1.

For revision 0x20, this interrupt clear register is a read & write
register, for the bit has not interrupt, can not write 1, otherwise
it will be 1.

So this patch adds a compatible handler for revision 0x20.

Fixes: a8a77dda7665 ("net: hns3: fix interrupt clearing error for VF")
Feature or Bugfix:Bugfix
Signed-off-by: NHuazhong Tan <tanhuazhong@huawei.com>
Reviewed-by: Nlipeng <lipeng321@huawei.com>
Reviewed-by: NYunsheng Lin <linyunsheng@huawei.com>
Reviewed-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

@@ -1896,7 +1896,19 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
 
 	/* check for vector0 mailbox(=CMDQ RX) event source */
 	if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
-		*clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
+		/* for revision 0x21, clearing interrupt is writing bit 0
+		 * to the clear register, writing bit 1 means to keep the
+		 * old value.
+		 * for revision 0x20, the clear register is a read & write
+		 * register, so we should just write 0 to the bit we are
+		 * handling, and keep other bits as cmdq_stat_reg.
+		 */
+		if (hdev->pdev->revision >= 0x21)
+			*clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
+		else
+			*clearval = cmdq_stat_reg &
+				    ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
+
 		return HCLGEVF_VECTOR0_EVENT_MBX;
 	}