The A31 SoC uses the same musb controller as found in earlier SoCs, but it
is hooked up slightly different. Its SRAM is private and no longer controlled
through the SRAM controller, and its reset is controlled via a separate
reset controller. This commit adds support for this setup.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>