pinctrl-nomadik.c 56.8 KB
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/*
 * Generic GPIO driver for logic cells found in the Nomadik SoC
 *
 * Copyright (C) 2008,2009 STMicroelectronics
 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
 *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
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 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
#include <linux/err.h>
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#include <linux/gpio.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/slab.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
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#include <linux/platform_data/pinctrl-nomadik.h>
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#include <asm/mach/irq.h>
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#include "pinctrl-nomadik.h"
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#include "core.h"
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/*
 * The GPIO module in the Nomadik family of Systems-on-Chip is an
 * AMBA device, managing 32 pins and alternate functions.  The logic block
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 * is currently used in the Nomadik and ux500.
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 *
 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
 */

struct nmk_gpio_chip {
	struct gpio_chip chip;
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	struct irq_domain *domain;
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	void __iomem *addr;
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	struct clk *clk;
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	unsigned int bank;
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	unsigned int parent_irq;
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	int secondary_parent_irq;
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	u32 (*get_secondary_status)(unsigned int bank);
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	void (*set_ioforce)(bool enable);
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	spinlock_t lock;
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	bool sleepmode;
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	/* Keep track of configured edges */
	u32 edge_rising;
	u32 edge_falling;
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	u32 real_wake;
	u32 rwimsc;
	u32 fwimsc;
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	u32 rimsc;
	u32 fimsc;
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	u32 pull_up;
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	u32 lowemi;
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};

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/**
 * struct nmk_pinctrl - state container for the Nomadik pin controller
 * @dev: containing device pointer
 * @pctl: corresponding pin controller device
 * @soc: SoC data for this specific chip
 * @prcm_base: PRCM register range virtual base
 */
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struct nmk_pinctrl {
	struct device *dev;
	struct pinctrl_dev *pctl;
	const struct nmk_pinctrl_soc_data *soc;
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	void __iomem *prcm_base;
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};

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static struct nmk_gpio_chip *
nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];

static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);

#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)

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static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
				unsigned offset, int gpio_mode)
{
	u32 bit = 1 << offset;
	u32 afunc, bfunc;

	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
	if (gpio_mode & NMK_GPIO_ALT_A)
		afunc |= bit;
	if (gpio_mode & NMK_GPIO_ALT_B)
		bfunc |= bit;
	writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
	writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
}

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static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
				unsigned offset, enum nmk_gpio_slpm mode)
{
	u32 bit = 1 << offset;
	u32 slpm;

	slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
	if (mode == NMK_GPIO_SLPM_NOCHANGE)
		slpm |= bit;
	else
		slpm &= ~bit;
	writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
}

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static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
				unsigned offset, enum nmk_gpio_pull pull)
{
	u32 bit = 1 << offset;
	u32 pdis;

	pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
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	if (pull == NMK_GPIO_PULL_NONE) {
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		pdis |= bit;
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		nmk_chip->pull_up &= ~bit;
	} else {
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		pdis &= ~bit;
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	}

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	writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);

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	if (pull == NMK_GPIO_PULL_UP) {
		nmk_chip->pull_up |= bit;
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		writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
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	} else if (pull == NMK_GPIO_PULL_DOWN) {
		nmk_chip->pull_up &= ~bit;
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		writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
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	}
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}

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static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
				  unsigned offset, bool lowemi)
{
	u32 bit = BIT(offset);
	bool enabled = nmk_chip->lowemi & bit;

	if (lowemi == enabled)
		return;

	if (lowemi)
		nmk_chip->lowemi |= bit;
	else
		nmk_chip->lowemi &= ~bit;

	writel_relaxed(nmk_chip->lowemi,
		       nmk_chip->addr + NMK_GPIO_LOWEMI);
}

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static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
				  unsigned offset)
{
	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
}

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static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
				  unsigned offset, int val)
{
	if (val)
		writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
	else
		writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
}

static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
				  unsigned offset, int val)
{
	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
	__nmk_gpio_set_output(nmk_chip, offset, val);
}

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static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
				     unsigned offset, int gpio_mode,
				     bool glitch)
{
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	u32 rwimsc = nmk_chip->rwimsc;
	u32 fwimsc = nmk_chip->fwimsc;
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	if (glitch && nmk_chip->set_ioforce) {
		u32 bit = BIT(offset);

		/* Prevent spurious wakeups */
		writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
		writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);

		nmk_chip->set_ioforce(true);
	}

	__nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);

	if (glitch && nmk_chip->set_ioforce) {
		nmk_chip->set_ioforce(false);

		writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
		writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
	}
}

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static void
nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
{
	u32 falling = nmk_chip->fimsc & BIT(offset);
	u32 rising = nmk_chip->rimsc & BIT(offset);
	int gpio = nmk_chip->chip.base + offset;
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	int irq = irq_find_mapping(nmk_chip->domain, offset);
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	struct irq_data *d = irq_get_irq_data(irq);

	if (!rising && !falling)
		return;

	if (!d || !irqd_irq_disabled(d))
		return;

	if (rising) {
		nmk_chip->rimsc &= ~BIT(offset);
		writel_relaxed(nmk_chip->rimsc,
			       nmk_chip->addr + NMK_GPIO_RIMSC);
	}

	if (falling) {
		nmk_chip->fimsc &= ~BIT(offset);
		writel_relaxed(nmk_chip->fimsc,
			       nmk_chip->addr + NMK_GPIO_FIMSC);
	}

	dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
}

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static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
{
	u32 val;

	val = readl(reg);
	val = ((val & ~mask) | (value & mask));
	writel(val, reg);
}

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static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
	unsigned offset, unsigned alt_num)
{
	int i;
	u16 reg;
	u8 bit;
	u8 alt_index;
	const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
	const u16 *gpiocr_regs;

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	if (!npct->prcm_base)
		return;

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	if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
		dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
			alt_num);
		return;
	}

	for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
		if (npct->soc->altcx_pins[i].pin == offset)
			break;
	}
	if (i == npct->soc->npins_altcx) {
		dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
			offset);
		return;
	}

	pin_desc = npct->soc->altcx_pins + i;
	gpiocr_regs = npct->soc->prcm_gpiocr_registers;

	/*
	 * If alt_num is NULL, just clear current ALTCx selection
	 * to make sure we come back to a pure ALTC selection
	 */
	if (!alt_num) {
		for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
			if (pin_desc->altcx[i].used == true) {
				reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
				bit = pin_desc->altcx[i].control_bit;
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				if (readl(npct->prcm_base + reg) & BIT(bit)) {
					nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
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					dev_dbg(npct->dev,
						"PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
						offset, i+1);
				}
			}
		}
		return;
	}

	alt_index = alt_num - 1;
	if (pin_desc->altcx[alt_index].used == false) {
		dev_warn(npct->dev,
			"PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
			offset, alt_num);
		return;
	}

	/*
	 * Check if any other ALTCx functions are activated on this pin
	 * and disable it first.
	 */
	for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
		if (i == alt_index)
			continue;
		if (pin_desc->altcx[i].used == true) {
			reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
			bit = pin_desc->altcx[i].control_bit;
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			if (readl(npct->prcm_base + reg) & BIT(bit)) {
				nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
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				dev_dbg(npct->dev,
					"PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
					offset, i+1);
			}
		}
	}

	reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
	bit = pin_desc->altcx[alt_index].control_bit;
	dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
		offset, alt_index+1);
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	nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
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}

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static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
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			     pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
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{
	static const char *afnames[] = {
		[NMK_GPIO_ALT_GPIO]	= "GPIO",
		[NMK_GPIO_ALT_A]	= "A",
		[NMK_GPIO_ALT_B]	= "B",
		[NMK_GPIO_ALT_C]	= "C"
	};
	static const char *pullnames[] = {
		[NMK_GPIO_PULL_NONE]	= "none",
		[NMK_GPIO_PULL_UP]	= "up",
		[NMK_GPIO_PULL_DOWN]	= "down",
		[3] /* illegal */	= "??"
	};
	static const char *slpmnames[] = {
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		[NMK_GPIO_SLPM_INPUT]		= "input/wakeup",
		[NMK_GPIO_SLPM_NOCHANGE]	= "no-change/no-wakeup",
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	};

	int pin = PIN_NUM(cfg);
	int pull = PIN_PULL(cfg);
	int af = PIN_ALT(cfg);
	int slpm = PIN_SLPM(cfg);
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	int output = PIN_DIR(cfg);
	int val = PIN_VAL(cfg);
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	bool glitch = af == NMK_GPIO_ALT_C;
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	dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
		pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
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		output ? "output " : "input",
		output ? (val ? "high" : "low") : "");

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	if (sleep) {
		int slpm_pull = PIN_SLPM_PULL(cfg);
		int slpm_output = PIN_SLPM_DIR(cfg);
		int slpm_val = PIN_SLPM_VAL(cfg);

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		af = NMK_GPIO_ALT_GPIO;

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		/*
		 * The SLPM_* values are normal values + 1 to allow zero to
		 * mean "same as normal".
		 */
		if (slpm_pull)
			pull = slpm_pull - 1;
		if (slpm_output)
			output = slpm_output - 1;
		if (slpm_val)
			val = slpm_val - 1;

		dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
			pin,
			slpm_pull ? pullnames[pull] : "same",
			slpm_output ? (output ? "output" : "input") : "same",
			slpm_val ? (val ? "high" : "low") : "same");
	}

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	if (output)
		__nmk_gpio_make_output(nmk_chip, offset, val);
	else {
		__nmk_gpio_make_input(nmk_chip, offset);
		__nmk_gpio_set_pull(nmk_chip, offset, pull);
	}
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	__nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));

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	/*
	 * If the pin is switching to altfunc, and there was an interrupt
	 * installed on it which has been lazy disabled, actually mask the
	 * interrupt to prevent spurious interrupts that would occur while the
	 * pin is under control of the peripheral.  Only SKE does this.
	 */
	if (af != NMK_GPIO_ALT_GPIO)
		nmk_gpio_disable_lazy_irq(nmk_chip, offset);

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	/*
	 * If we've backed up the SLPM registers (glitch workaround), modify
	 * the backups since they will be restored.
	 */
	if (slpmregs) {
		if (slpm == NMK_GPIO_SLPM_NOCHANGE)
			slpmregs[nmk_chip->bank] |= BIT(offset);
		else
			slpmregs[nmk_chip->bank] &= ~BIT(offset);
	} else
		__nmk_gpio_set_slpm(nmk_chip, offset, slpm);

	__nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
}

/*
 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
 *  - Save SLPM registers
 *  - Set SLPM=0 for the IOs you want to switch and others to 1
 *  - Configure the GPIO registers for the IOs that are being switched
 *  - Set IOFORCE=1
 *  - Modify the AFLSA/B registers for the IOs that are being switched
 *  - Set IOFORCE=0
 *  - Restore SLPM registers
 *  - Any spurious wake up event during switch sequence to be ignored and
 *    cleared
 */
static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
		unsigned int temp = slpm[i];

		if (!chip)
			break;

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		clk_enable(chip->clk);

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		slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
		writel(temp, chip->addr + NMK_GPIO_SLPC);
	}
}

static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			break;

		writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
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		clk_disable(chip->clk);
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	}
}

static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
{
	static unsigned int slpm[NUM_BANKS];
	unsigned long flags;
	bool glitch = false;
	int ret = 0;
	int i;

	for (i = 0; i < num; i++) {
		if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
			glitch = true;
			break;
		}
	}

	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);

	if (glitch) {
		memset(slpm, 0xff, sizeof(slpm));

		for (i = 0; i < num; i++) {
			int pin = PIN_NUM(cfgs[i]);
			int offset = pin % NMK_GPIO_PER_CHIP;

			if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
				slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
		}

		nmk_gpio_glitch_slpm_init(slpm);
	}

	for (i = 0; i < num; i++) {
		struct nmk_gpio_chip *nmk_chip;
		int pin = PIN_NUM(cfgs[i]);

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		nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
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		if (!nmk_chip) {
			ret = -EINVAL;
			break;
		}

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		clk_enable(nmk_chip->clk);
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		spin_lock(&nmk_chip->lock);
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		__nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
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				 cfgs[i], sleep, glitch ? slpm : NULL);
		spin_unlock(&nmk_chip->lock);
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		clk_disable(nmk_chip->clk);
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	}

	if (glitch)
		nmk_gpio_glitch_slpm_restore(slpm);

	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);

	return ret;
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}

/**
 * nmk_config_pin - configure a pin's mux attributes
 * @cfg: pin confguration
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 * @sleep: Non-zero to apply the sleep mode configuration
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 * Configures a pin's mode (alternate function or GPIO), its pull up status,
 * and its sleep mode based on the specified configuration.  The @cfg is
 * usually one of the SoC specific macros defined in mach/<soc>-pins.h.  These
 * are constructed using, and can be further enhanced with, the macros in
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 * <linux/platform_data/pinctrl-nomadik.h>
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 *
 * If a pin's mode is set to GPIO, it is configured as an input to avoid
 * side-effects.  The gpio can be manipulated later using standard GPIO API
 * calls.
 */
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int nmk_config_pin(pin_cfg_t cfg, bool sleep)
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{
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	return __nmk_config_pins(&cfg, 1, sleep);
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}
EXPORT_SYMBOL(nmk_config_pin);

/**
 * nmk_config_pins - configure several pins at once
 * @cfgs: array of pin configurations
 * @num: number of elments in the array
 *
 * Configures several pins using nmk_config_pin().  Refer to that function for
 * further information.
 */
int nmk_config_pins(pin_cfg_t *cfgs, int num)
{
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	return __nmk_config_pins(cfgs, num, false);
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}
EXPORT_SYMBOL(nmk_config_pins);

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int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
{
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	return __nmk_config_pins(cfgs, num, true);
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}
EXPORT_SYMBOL(nmk_config_pins_sleep);

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/**
 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
 * @gpio: pin number
 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
 *
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 * This register is actually in the pinmux layer, not the GPIO block itself.
 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
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 *
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 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
 * entered) regardless of the altfunction selected. Also wake-up detection is
 * ENABLED.
 *
 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
 * (for altfunction GPIO) or respective on-chip peripherals (for other
 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
 *
 * Note that enable_irq_wake() will automatically enable wakeup detection.
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 */
int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
{
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;

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	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
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	if (!nmk_chip)
		return -EINVAL;

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	clk_enable(nmk_chip->clk);
608 609 610
	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
	spin_lock(&nmk_chip->lock);

611
	__nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
612 613 614

	spin_unlock(&nmk_chip->lock);
	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
615
	clk_disable(nmk_chip->clk);
616 617 618 619

	return 0;
}

620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637
/**
 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
 * @gpio: pin number
 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
 *
 * Enables/disables pull up/down on a specified pin.  This only takes effect if
 * the pin is configured as an input (either explicitly or by the alternate
 * function).
 *
 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
 * configured as an input.  Otherwise, due to the way the controller registers
 * work, this function will change the value output on the pin.
 */
int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
{
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;

638
	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
639 640 641
	if (!nmk_chip)
		return -EINVAL;

642
	clk_enable(nmk_chip->clk);
643
	spin_lock_irqsave(&nmk_chip->lock, flags);
644
	__nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
645
	spin_unlock_irqrestore(&nmk_chip->lock, flags);
646
	clk_disable(nmk_chip->clk);
647 648 649 650

	return 0;
}

651
/* Mode functions */
652 653 654 655 656 657 658 659 660
/**
 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
 * @gpio: pin number
 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
 *	       NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
 *
 * Sets the mode of the specified pin to one of the alternate functions or
 * plain GPIO.
 */
661 662 663 664 665
int nmk_gpio_set_mode(int gpio, int gpio_mode)
{
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;

666
	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
667 668 669
	if (!nmk_chip)
		return -EINVAL;

670
	clk_enable(nmk_chip->clk);
671
	spin_lock_irqsave(&nmk_chip->lock, flags);
672
	__nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
673
	spin_unlock_irqrestore(&nmk_chip->lock, flags);
674
	clk_disable(nmk_chip->clk);
675 676 677 678 679

	return 0;
}
EXPORT_SYMBOL(nmk_gpio_set_mode);

680 681 682 683 684 685 686 687 688
static int nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
{
	int i;
	u16 reg;
	u8 bit;
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
	const u16 *gpiocr_regs;

689 690 691
	if (!npct->prcm_base)
		return NMK_GPIO_ALT_C;

692 693 694 695 696 697 698 699 700 701 702 703 704
	for (i = 0; i < npct->soc->npins_altcx; i++) {
		if (npct->soc->altcx_pins[i].pin == gpio)
			break;
	}
	if (i == npct->soc->npins_altcx)
		return NMK_GPIO_ALT_C;

	pin_desc = npct->soc->altcx_pins + i;
	gpiocr_regs = npct->soc->prcm_gpiocr_registers;
	for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
		if (pin_desc->altcx[i].used == true) {
			reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
			bit = pin_desc->altcx[i].control_bit;
705
			if (readl(npct->prcm_base + reg) & BIT(bit))
706 707 708 709 710 711
				return NMK_GPIO_ALT_C+i+1;
		}
	}
	return NMK_GPIO_ALT_C;
}

712 713 714 715 716
int nmk_gpio_get_mode(int gpio)
{
	struct nmk_gpio_chip *nmk_chip;
	u32 afunc, bfunc, bit;

717
	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
718 719 720
	if (!nmk_chip)
		return -EINVAL;

721
	bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
722

723 724
	clk_enable(nmk_chip->clk);

725 726 727
	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;

728 729
	clk_disable(nmk_chip->clk);

730 731 732 733 734 735 736 737
	return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
}
EXPORT_SYMBOL(nmk_gpio_get_mode);


/* IRQ functions */
static inline int nmk_gpio_get_bitmask(int gpio)
{
738
	return 1 << (gpio % NMK_GPIO_PER_CHIP);
739 740
}

741
static void nmk_gpio_irq_ack(struct irq_data *d)
742 743 744
{
	struct nmk_gpio_chip *nmk_chip;

745
	nmk_chip = irq_data_get_irq_chip_data(d);
746 747
	if (!nmk_chip)
		return;
748 749

	clk_enable(nmk_chip->clk);
750
	writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
751
	clk_disable(nmk_chip->clk);
752 753
}

754 755 756 757 758
enum nmk_gpio_irq_type {
	NORMAL,
	WAKE,
};

759
static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
760 761
				  int gpio, enum nmk_gpio_irq_type which,
				  bool enable)
762
{
763
	u32 bitmask = nmk_gpio_get_bitmask(gpio);
R
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764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779
	u32 *rimscval;
	u32 *fimscval;
	u32 rimscreg;
	u32 fimscreg;

	if (which == NORMAL) {
		rimscreg = NMK_GPIO_RIMSC;
		fimscreg = NMK_GPIO_FIMSC;
		rimscval = &nmk_chip->rimsc;
		fimscval = &nmk_chip->fimsc;
	} else  {
		rimscreg = NMK_GPIO_RWIMSC;
		fimscreg = NMK_GPIO_FWIMSC;
		rimscval = &nmk_chip->rwimsc;
		fimscval = &nmk_chip->fwimsc;
	}
780

781
	/* we must individually set/clear the two edges */
782
	if (nmk_chip->edge_rising & bitmask) {
783
		if (enable)
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784
			*rimscval |= bitmask;
785
		else
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786 787
			*rimscval &= ~bitmask;
		writel(*rimscval, nmk_chip->addr + rimscreg);
788 789
	}
	if (nmk_chip->edge_falling & bitmask) {
790
		if (enable)
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791
			*fimscval |= bitmask;
792
		else
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793 794
			*fimscval &= ~bitmask;
		writel(*fimscval, nmk_chip->addr + fimscreg);
795
	}
796
}
797

798 799 800
static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
				int gpio, bool on)
{
801 802 803 804 805 806
	/*
	 * Ensure WAKEUP_ENABLE is on.  No need to disable it if wakeup is
	 * disabled, since setting SLPM to 1 increases power consumption, and
	 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
	 */
	if (nmk_chip->sleepmode && on) {
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807
		__nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
808
				    NMK_GPIO_SLPM_WAKEUP_ENABLE);
809 810
	}

811 812 813 814
	__nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
}

static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
815 816 817
{
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;
818
	u32 bitmask;
819

820
	nmk_chip = irq_data_get_irq_chip_data(d);
821
	bitmask = nmk_gpio_get_bitmask(d->hwirq);
822
	if (!nmk_chip)
823
		return -EINVAL;
824

825
	clk_enable(nmk_chip->clk);
826 827 828
	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
	spin_lock(&nmk_chip->lock);

829
	__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
830 831

	if (!(nmk_chip->real_wake & bitmask))
832
		__nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
833 834 835

	spin_unlock(&nmk_chip->lock);
	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
836
	clk_disable(nmk_chip->clk);
837 838

	return 0;
839 840
}

841
static void nmk_gpio_irq_mask(struct irq_data *d)
842
{
843
	nmk_gpio_irq_maskunmask(d, false);
844
}
845

846
static void nmk_gpio_irq_unmask(struct irq_data *d)
847
{
848
	nmk_gpio_irq_maskunmask(d, true);
849 850
}

851
static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
852
{
853 854
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;
855
	u32 bitmask;
856

857
	nmk_chip = irq_data_get_irq_chip_data(d);
858 859
	if (!nmk_chip)
		return -EINVAL;
860
	bitmask = nmk_gpio_get_bitmask(d->hwirq);
861

862
	clk_enable(nmk_chip->clk);
863 864 865
	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
	spin_lock(&nmk_chip->lock);

866
	if (irqd_irq_disabled(d))
867
		__nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
868 869 870 871 872

	if (on)
		nmk_chip->real_wake |= bitmask;
	else
		nmk_chip->real_wake &= ~bitmask;
873 874 875

	spin_unlock(&nmk_chip->lock);
	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
876
	clk_disable(nmk_chip->clk);
877 878

	return 0;
879 880
}

881
static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
882
{
883
	bool enabled = !irqd_irq_disabled(d);
884
	bool wake = irqd_is_wakeup_set(d);
885 886 887 888
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;
	u32 bitmask;

889
	nmk_chip = irq_data_get_irq_chip_data(d);
890
	bitmask = nmk_gpio_get_bitmask(d->hwirq);
891 892 893 894 895 896 897
	if (!nmk_chip)
		return -EINVAL;
	if (type & IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;
	if (type & IRQ_TYPE_LEVEL_LOW)
		return -EINVAL;

898
	clk_enable(nmk_chip->clk);
899 900
	spin_lock_irqsave(&nmk_chip->lock, flags);

901
	if (enabled)
902
		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
903

904
	if (enabled || wake)
905
		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
906

907 908 909 910 911 912 913 914
	nmk_chip->edge_rising &= ~bitmask;
	if (type & IRQ_TYPE_EDGE_RISING)
		nmk_chip->edge_rising |= bitmask;

	nmk_chip->edge_falling &= ~bitmask;
	if (type & IRQ_TYPE_EDGE_FALLING)
		nmk_chip->edge_falling |= bitmask;

915
	if (enabled)
916
		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
917

918
	if (enabled || wake)
919
		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
920

921
	spin_unlock_irqrestore(&nmk_chip->lock, flags);
922
	clk_disable(nmk_chip->clk);
923 924 925 926

	return 0;
}

927 928 929
static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
{
	struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
930

931 932
	clk_enable(nmk_chip->clk);
	nmk_gpio_irq_unmask(d);
933 934 935
	return 0;
}

936 937 938 939 940 941 942 943
static void nmk_gpio_irq_shutdown(struct irq_data *d)
{
	struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);

	nmk_gpio_irq_mask(d);
	clk_disable(nmk_chip->clk);
}

944 945
static struct irq_chip nmk_gpio_irq_chip = {
	.name		= "Nomadik-GPIO",
946 947 948 949 950
	.irq_ack	= nmk_gpio_irq_ack,
	.irq_mask	= nmk_gpio_irq_mask,
	.irq_unmask	= nmk_gpio_irq_unmask,
	.irq_set_type	= nmk_gpio_irq_set_type,
	.irq_set_wake	= nmk_gpio_irq_set_wake,
951 952
	.irq_startup	= nmk_gpio_irq_startup,
	.irq_shutdown	= nmk_gpio_irq_shutdown,
953
	.flags		= IRQCHIP_MASK_ON_SUSPEND,
954 955
};

956 957
static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
				   u32 status)
958 959
{
	struct nmk_gpio_chip *nmk_chip;
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960
	struct irq_chip *host_chip = irq_get_chip(irq);
961

962
	chained_irq_enter(host_chip, desc);
963

T
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964
	nmk_chip = irq_get_handler_data(irq);
965 966 967
	while (status) {
		int bit = __ffs(status);

968
		generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
969
		status &= ~BIT(bit);
970
	}
971

972
	chained_irq_exit(host_chip, desc);
973 974
}

975 976
static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
T
Thomas Gleixner 已提交
977
	struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
978 979 980 981 982
	u32 status;

	clk_enable(nmk_chip->clk);
	status = readl(nmk_chip->addr + NMK_GPIO_IS);
	clk_disable(nmk_chip->clk);
983 984 985 986 987 988 989

	__nmk_gpio_irq_handler(irq, desc, status);
}

static void nmk_gpio_secondary_irq_handler(unsigned int irq,
					   struct irq_desc *desc)
{
T
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990
	struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
991 992 993 994 995
	u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);

	__nmk_gpio_irq_handler(irq, desc, status);
}

996 997
static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
{
T
Thomas Gleixner 已提交
998 999
	irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
	irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
1000 1001

	if (nmk_chip->secondary_parent_irq >= 0) {
T
Thomas Gleixner 已提交
1002
		irq_set_chained_handler(nmk_chip->secondary_parent_irq,
1003
					nmk_gpio_secondary_irq_handler);
T
Thomas Gleixner 已提交
1004
		irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
1005 1006
	}

1007 1008 1009 1010
	return 0;
}

/* I/O Functions */
1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029

static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	/*
	 * Map back to global GPIO space and request muxing, the direction
	 * parameter does not matter for this controller.
	 */
	int gpio = chip->base + offset;

	return pinctrl_request_gpio(gpio);
}

static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	int gpio = chip->base + offset;

	pinctrl_free_gpio(gpio);
}

1030 1031 1032 1033 1034
static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);

1035 1036
	clk_enable(nmk_chip->clk);

1037
	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
1038 1039 1040

	clk_disable(nmk_chip->clk);

1041 1042 1043 1044 1045 1046 1047 1048
	return 0;
}

static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);
	u32 bit = 1 << offset;
1049 1050 1051
	int value;

	clk_enable(nmk_chip->clk);
1052

1053
	value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
1054

1055 1056 1057
	clk_disable(nmk_chip->clk);

	return value;
1058 1059 1060 1061 1062 1063 1064 1065
}

static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
				int val)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);

1066 1067
	clk_enable(nmk_chip->clk);

1068
	__nmk_gpio_set_output(nmk_chip, offset, val);
1069 1070

	clk_disable(nmk_chip->clk);
1071 1072
}

1073 1074 1075 1076 1077 1078
static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
				int val)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);

1079 1080
	clk_enable(nmk_chip->clk);

1081
	__nmk_gpio_make_output(nmk_chip, offset, val);
1082

1083 1084
	clk_disable(nmk_chip->clk);

1085 1086 1087
	return 0;
}

1088 1089 1090 1091 1092
static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);

1093
	return irq_create_mapping(nmk_chip->domain, offset);
1094 1095
}

1096 1097 1098 1099
#ifdef CONFIG_DEBUG_FS

#include <linux/seq_file.h>

1100 1101 1102
static void nmk_gpio_dbg_show_one(struct seq_file *s,
	struct pinctrl_dev *pctldev, struct gpio_chip *chip,
	unsigned offset, unsigned gpio)
1103
{
1104
	const char *label = gpiochip_is_requested(chip, offset);
1105 1106
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);
1107 1108 1109 1110
	int mode;
	bool is_out;
	bool pull;
	u32 bit = 1 << offset;
1111 1112 1113 1114 1115
	const char *modes[] = {
		[NMK_GPIO_ALT_GPIO]	= "gpio",
		[NMK_GPIO_ALT_A]	= "altA",
		[NMK_GPIO_ALT_B]	= "altB",
		[NMK_GPIO_ALT_C]	= "altC",
1116 1117 1118 1119
		[NMK_GPIO_ALT_C+1]	= "altC1",
		[NMK_GPIO_ALT_C+2]	= "altC2",
		[NMK_GPIO_ALT_C+3]	= "altC3",
		[NMK_GPIO_ALT_C+4]	= "altC4",
1120 1121
	};

1122
	clk_enable(nmk_chip->clk);
1123 1124 1125
	is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
	pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
	mode = nmk_gpio_get_mode(gpio);
1126 1127
	if ((mode == NMK_GPIO_ALT_C) && pctldev)
		mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159

	seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
		   gpio, label ?: "(none)",
		   is_out ? "out" : "in ",
		   chip->get
		   ? (chip->get(chip, offset) ? "hi" : "lo")
		   : "?  ",
		   (mode < 0) ? "unknown" : modes[mode],
		   pull ? "pull" : "none");

	if (label && !is_out) {
		int		irq = gpio_to_irq(gpio);
		struct irq_desc	*desc = irq_to_desc(irq);

		/* This races with request_irq(), set_irq_type(),
		 * and set_irq_wake() ... but those are "rare".
		 */
		if (irq >= 0 && desc->action) {
			char *trigger;
			u32 bitmask = nmk_gpio_get_bitmask(gpio);

			if (nmk_chip->edge_rising & bitmask)
				trigger = "edge-rising";
			else if (nmk_chip->edge_falling & bitmask)
				trigger = "edge-falling";
			else
				trigger = "edge-undefined";

			seq_printf(s, " irq-%d %s%s",
				   irq, trigger,
				   irqd_is_wakeup_set(&desc->irq_data)
				   ? " wakeup" : "");
1160
		}
1161 1162 1163 1164 1165 1166 1167 1168
	}
	clk_disable(nmk_chip->clk);
}

static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	unsigned		i;
	unsigned		gpio = chip->base;
1169

1170
	for (i = 0; i < chip->ngpio; i++, gpio++) {
1171
		nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1172 1173 1174 1175 1176
		seq_printf(s, "\n");
	}
}

#else
1177
static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1178
					 struct pinctrl_dev *pctldev,
1179 1180 1181 1182
					 struct gpio_chip *chip,
					 unsigned offset, unsigned gpio)
{
}
1183 1184 1185
#define nmk_gpio_dbg_show	NULL
#endif

1186 1187
/* This structure is replicated for each GPIO block allocated at probe time */
static struct gpio_chip nmk_gpio_template = {
1188 1189
	.request		= nmk_gpio_request,
	.free			= nmk_gpio_free,
1190 1191 1192 1193
	.direction_input	= nmk_gpio_make_input,
	.get			= nmk_gpio_get_input,
	.direction_output	= nmk_gpio_make_output,
	.set			= nmk_gpio_set_output,
1194
	.to_irq			= nmk_gpio_to_irq,
1195
	.dbg_show		= nmk_gpio_dbg_show,
1196 1197 1198
	.can_sleep		= 0,
};

1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226
void nmk_gpio_clocks_enable(void)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			continue;

		clk_enable(chip->clk);
	}
}

void nmk_gpio_clocks_disable(void)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			continue;

		clk_disable(chip->clk);
	}
}

1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245
/*
 * Called from the suspend/resume path to only keep the real wakeup interrupts
 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
 * and not the rest of the interrupts which we needed to have as wakeups for
 * cpuidle.
 *
 * PM ops are not used since this needs to be done at the end, after all the
 * other drivers are done with their suspend callbacks.
 */
void nmk_gpio_wakeups_suspend(void)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			break;

1246 1247
		clk_enable(chip->clk);

1248 1249 1250 1251 1252
		writel(chip->rwimsc & chip->real_wake,
		       chip->addr + NMK_GPIO_RWIMSC);
		writel(chip->fwimsc & chip->real_wake,
		       chip->addr + NMK_GPIO_FWIMSC);

1253
		clk_disable(chip->clk);
1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266
	}
}

void nmk_gpio_wakeups_resume(void)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			break;

1267 1268
		clk_enable(chip->clk);

1269 1270 1271
		writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
		writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);

1272
		clk_disable(chip->clk);
1273 1274 1275
	}
}

1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294
/*
 * Read the pull up/pull down status.
 * A bit set in 'pull_up' means that pull up
 * is selected if pull is enabled in PDIS register.
 * Note: only pull up/down set via this driver can
 * be detected due to HW limitations.
 */
void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
{
	if (gpio_bank < NUM_BANKS) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];

		if (!chip)
			return;

		*pull_up = chip->pull_up;
	}
}

1295 1296
static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
			    irq_hw_number_t hwirq)
1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315
{
	struct nmk_gpio_chip *nmk_chip = d->host_data;

	if (!nmk_chip)
		return -EINVAL;

	irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID);
	irq_set_chip_data(irq, nmk_chip);
	irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);

	return 0;
}

const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
	.map = nmk_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

1316
static int nmk_gpio_probe(struct platform_device *dev)
1317
{
1318
	struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1319
	struct device_node *np = dev->dev.of_node;
1320 1321
	struct nmk_gpio_chip *nmk_chip;
	struct gpio_chip *chip;
1322
	struct resource *res;
1323
	struct clk *clk;
1324
	int secondary_irq;
1325
	void __iomem *base;
1326
	int irq_start = 0;
1327
	int irq;
1328 1329
	int ret;

1330 1331
	if (!pdata && !np) {
		dev_err(&dev->dev, "No platform data or device tree found\n");
1332
		return -ENODEV;
1333 1334 1335
	}

	if (np) {
1336
		pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1337 1338 1339
		if (!pdata)
			return -ENOMEM;

1340
		if (of_get_property(np, "st,supports-sleepmode", NULL))
1341 1342 1343 1344
			pdata->supports_sleepmode = true;

		if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
			dev_err(&dev->dev, "gpio-bank property not found\n");
1345
			return -EINVAL;
1346 1347 1348 1349 1350
		}

		pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
		pdata->num_gpio   = NMK_GPIO_PER_CHIP;
	}
1351 1352

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1353 1354
	if (!res)
		return -ENOENT;
1355 1356

	irq = platform_get_irq(dev, 0);
1357 1358
	if (irq < 0)
		return irq;
1359

1360
	secondary_irq = platform_get_irq(dev, 1);
1361 1362
	if (secondary_irq >= 0 && !pdata->get_secondary_status)
		return -EINVAL;
1363

1364
	base = devm_request_and_ioremap(&dev->dev, res);
1365 1366
	if (!base)
		return -ENOMEM;
1367

1368
	clk = devm_clk_get(&dev->dev, NULL);
1369 1370
	if (IS_ERR(clk))
		return PTR_ERR(clk);
1371
	clk_prepare(clk);
1372

1373
	nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1374 1375
	if (!nmk_chip)
		return -ENOMEM;
1376

1377 1378 1379 1380
	/*
	 * The virt address in nmk_chip->addr is in the nomadik register space,
	 * so we can simply convert the resource address, without remapping
	 */
1381
	nmk_chip->bank = dev->id;
1382
	nmk_chip->clk = clk;
1383
	nmk_chip->addr = base;
1384
	nmk_chip->chip = nmk_gpio_template;
1385
	nmk_chip->parent_irq = irq;
1386 1387
	nmk_chip->secondary_parent_irq = secondary_irq;
	nmk_chip->get_secondary_status = pdata->get_secondary_status;
1388
	nmk_chip->set_ioforce = pdata->set_ioforce;
1389
	nmk_chip->sleepmode = pdata->supports_sleepmode;
1390
	spin_lock_init(&nmk_chip->lock);
1391 1392 1393

	chip = &nmk_chip->chip;
	chip->base = pdata->first_gpio;
1394
	chip->ngpio = pdata->num_gpio;
1395
	chip->label = pdata->name ?: dev_name(&dev->dev);
1396 1397 1398
	chip->dev = &dev->dev;
	chip->owner = THIS_MODULE;

1399 1400 1401 1402
	clk_enable(nmk_chip->clk);
	nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
	clk_disable(nmk_chip->clk);

1403
#ifdef CONFIG_OF_GPIO
1404
	chip->of_node = np;
1405
#endif
1406

1407 1408
	ret = gpiochip_add(&nmk_chip->chip);
	if (ret)
1409
		return ret;
1410

1411 1412 1413
	BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));

	nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1414

1415
	platform_set_drvdata(dev, nmk_chip);
1416

1417
	if (!np)
1418
		irq_start = pdata->first_irq;
1419
	nmk_chip->domain = irq_domain_add_simple(np,
1420 1421
				NMK_GPIO_PER_CHIP, irq_start,
				&nmk_gpio_irq_simple_ops, nmk_chip);
1422
	if (!nmk_chip->domain) {
1423
		dev_err(&dev->dev, "failed to create irqdomain\n");
1424 1425 1426
		/* Just do this, no matter if it fails */
		ret = gpiochip_remove(&nmk_chip->chip);
		return -ENOSYS;
1427 1428
	}

1429 1430
	nmk_gpio_init_irq(nmk_chip);

1431 1432
	dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);

1433 1434 1435
	return 0;
}

1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461
static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	return npct->soc->ngroups;
}

static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
				       unsigned selector)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	return npct->soc->groups[selector].name;
}

static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
			      const unsigned **pins,
			      unsigned *num_pins)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	*pins = npct->soc->groups[selector].pins;
	*num_pins = npct->soc->groups[selector].npins;
	return 0;
}

1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478
static struct pinctrl_gpio_range *
nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	int i;

	for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
		struct pinctrl_gpio_range *range;

		range = &npct->soc->gpio_ranges[i];
		if (offset >= range->pin_base &&
		    offset <= (range->pin_base + range->npins - 1))
			return range;
	}
	return NULL;
}

1479 1480 1481
static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
		   unsigned offset)
{
1482 1483 1484 1485 1486 1487 1488 1489 1490
	struct pinctrl_gpio_range *range;
	struct gpio_chip *chip;

	range = nmk_match_gpio_range(pctldev, offset);
	if (!range || !range->gc) {
		seq_printf(s, "invalid pin offset");
		return;
	}
	chip = range->gc;
1491
	nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1492 1493
}

1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765
static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
		struct pinctrl_map *map, unsigned num_maps)
{
	int i;

	for (i = 0; i < num_maps; i++)
		if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
			kfree(map[i].data.configs.configs);
	kfree(map);
}

static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
		unsigned *num_maps, unsigned reserve)
{
	unsigned old_num = *reserved_maps;
	unsigned new_num = *num_maps + reserve;
	struct pinctrl_map *new_map;

	if (old_num >= new_num)
		return 0;

	new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
	if (!new_map)
		return -ENOMEM;

	memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));

	*map = new_map;
	*reserved_maps = new_num;

	return 0;
}

static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
		unsigned *num_maps, const char *group,
		const char *function)
{
	if (*num_maps == *reserved_maps)
		return -ENOSPC;

	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
	(*map)[*num_maps].data.mux.group = group;
	(*map)[*num_maps].data.mux.function = function;
	(*num_maps)++;

	return 0;
}

static int nmk_dt_add_map_configs(struct pinctrl_map **map,
		unsigned *reserved_maps,
		unsigned *num_maps, const char *group,
		unsigned long *configs, unsigned num_configs)
{
	unsigned long *dup_configs;

	if (*num_maps == *reserved_maps)
		return -ENOSPC;

	dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
			      GFP_KERNEL);
	if (!dup_configs)
		return -ENOMEM;

	(*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;

	(*map)[*num_maps].data.configs.group_or_pin = group;
	(*map)[*num_maps].data.configs.configs = dup_configs;
	(*map)[*num_maps].data.configs.num_configs = num_configs;
	(*num_maps)++;

	return 0;
}

#define NMK_CONFIG_PIN(x,y) { .property = x, .config = y, }
#define NMK_CONFIG_PIN_ARRAY(x,y) { .property = x, .choice = y, \
	.size = ARRAY_SIZE(y), }

static const unsigned long nmk_pin_input_modes[] = {
	PIN_INPUT_NOPULL,
	PIN_INPUT_PULLUP,
	PIN_INPUT_PULLDOWN,
};

static const unsigned long nmk_pin_output_modes[] = {
	PIN_OUTPUT_LOW,
	PIN_OUTPUT_HIGH,
	PIN_DIR_OUTPUT,
};

static const unsigned long nmk_pin_sleep_modes[] = {
	PIN_SLEEPMODE_DISABLED,
	PIN_SLEEPMODE_ENABLED,
};

static const unsigned long nmk_pin_sleep_input_modes[] = {
	PIN_SLPM_INPUT_NOPULL,
	PIN_SLPM_INPUT_PULLUP,
	PIN_SLPM_INPUT_PULLDOWN,
	PIN_SLPM_DIR_INPUT,
};

static const unsigned long nmk_pin_sleep_output_modes[] = {
	PIN_SLPM_OUTPUT_LOW,
	PIN_SLPM_OUTPUT_HIGH,
	PIN_SLPM_DIR_OUTPUT,
};

static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
	PIN_SLPM_WAKEUP_DISABLE,
	PIN_SLPM_WAKEUP_ENABLE,
};

static const unsigned long nmk_pin_gpio_modes[] = {
	PIN_GPIOMODE_DISABLED,
	PIN_GPIOMODE_ENABLED,
};

static const unsigned long nmk_pin_sleep_pdis_modes[] = {
	PIN_SLPM_PDIS_DISABLED,
	PIN_SLPM_PDIS_ENABLED,
};

struct nmk_cfg_param {
	const char *property;
	unsigned long config;
	const unsigned long *choice;
	int size;
};

static const struct nmk_cfg_param nmk_cfg_params[] = {
	NMK_CONFIG_PIN_ARRAY("ste,input",		nmk_pin_input_modes),
	NMK_CONFIG_PIN_ARRAY("ste,output",		nmk_pin_output_modes),
	NMK_CONFIG_PIN_ARRAY("ste,sleep",		nmk_pin_sleep_modes),
	NMK_CONFIG_PIN_ARRAY("ste,sleep-input",		nmk_pin_sleep_input_modes),
	NMK_CONFIG_PIN_ARRAY("ste,sleep-output",	nmk_pin_sleep_output_modes),
	NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup",	nmk_pin_sleep_wakeup_modes),
	NMK_CONFIG_PIN_ARRAY("ste,gpio",		nmk_pin_gpio_modes),
	NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable",	nmk_pin_sleep_pdis_modes),
};

static int nmk_dt_pin_config(int index, int val, unsigned long *config)
{
	int ret = 0;

	if (nmk_cfg_params[index].choice == NULL)
		*config = nmk_cfg_params[index].config;
	else {
		/* test if out of range */
		if  (val < nmk_cfg_params[index].size) {
			*config = nmk_cfg_params[index].config |
				nmk_cfg_params[index].choice[val];
		}
	}
	return ret;
}

static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
{
	int i, pin_number;
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
		for (i = 0; i < npct->soc->npins; i++)
			if (npct->soc->pins[i].number == pin_number)
				return npct->soc->pins[i].name;
	return NULL;
}

static bool nmk_pinctrl_dt_get_config(struct device_node *np,
		unsigned long *configs)
{
	bool has_config = 0;
	unsigned long cfg = 0;
	int i, val, ret;

	for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
		ret = of_property_read_u32(np,
				nmk_cfg_params[i].property, &val);
		if (ret != -EINVAL) {
			if (nmk_dt_pin_config(i, val, &cfg) == 0) {
				*configs |= cfg;
				has_config = 1;
			}
		}
	}

	return has_config;
}

int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
		struct device_node *np,
		struct pinctrl_map **map,
		unsigned *reserved_maps,
		unsigned *num_maps)
{
	int ret;
	const char *function = NULL;
	unsigned long configs = 0;
	bool has_config = 0;
	unsigned reserve = 0;
	struct property *prop;
	const char *group, *gpio_name;
	struct device_node *np_config;

	ret = of_property_read_string(np, "ste,function", &function);
	if (ret >= 0)
		reserve = 1;

	has_config = nmk_pinctrl_dt_get_config(np, &configs);

	np_config = of_parse_phandle(np, "ste,config", 0);
	if (np_config)
		has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);

	ret = of_property_count_strings(np, "ste,pins");
	if (ret < 0)
		goto exit;

	if (has_config)
		reserve++;

	reserve *= ret;

	ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
	if (ret < 0)
		goto exit;

	of_property_for_each_string(np, "ste,pins", prop, group) {
		if (function) {
			ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
					  group, function);
			if (ret < 0)
				goto exit;
		}
		if (has_config) {
			gpio_name = nmk_find_pin_name(pctldev, group);

			ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
					      gpio_name, &configs, 1);
			if (ret < 0)
				goto exit;
		}

	}
exit:
	return ret;
}

int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
				 struct device_node *np_config,
				 struct pinctrl_map **map, unsigned *num_maps)
{
	unsigned reserved_maps;
	struct device_node *np;
	int ret;

	reserved_maps = 0;
	*map = NULL;
	*num_maps = 0;

	for_each_child_of_node(np_config, np) {
		ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
				&reserved_maps, num_maps);
		if (ret < 0) {
			nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
			return ret;
		}
	}

	return 0;
}

1766 1767 1768 1769 1770
static struct pinctrl_ops nmk_pinctrl_ops = {
	.get_groups_count = nmk_get_groups_cnt,
	.get_group_name = nmk_get_group_name,
	.get_group_pins = nmk_get_group_pins,
	.pin_dbg_show = nmk_pin_dbg_show,
1771 1772
	.dt_node_to_map = nmk_pinctrl_dt_node_to_map,
	.dt_free_map = nmk_pinctrl_dt_free_map,
1773 1774
};

1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820
static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	return npct->soc->nfunctions;
}

static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
					 unsigned function)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	return npct->soc->functions[function].name;
}

static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
				   unsigned function,
				   const char * const **groups,
				   unsigned * const num_groups)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	*groups = npct->soc->functions[function].groups;
	*num_groups = npct->soc->functions[function].ngroups;

	return 0;
}

static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
			  unsigned group)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	const struct nmk_pingroup *g;
	static unsigned int slpm[NUM_BANKS];
	unsigned long flags;
	bool glitch;
	int ret = -EINVAL;
	int i;

	g = &npct->soc->groups[group];

	if (g->altsetting < 0)
		return -EINVAL;

	dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);

1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841
	/*
	 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
	 * we may pass through an undesired state. In this case we take
	 * some extra care.
	 *
	 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
	 *  - Save SLPM registers (since we have a shadow register in the
	 *    nmk_chip we're using that as backup)
	 *  - Set SLPM=0 for the IOs you want to switch and others to 1
	 *  - Configure the GPIO registers for the IOs that are being switched
	 *  - Set IOFORCE=1
	 *  - Modify the AFLSA/B registers for the IOs that are being switched
	 *  - Set IOFORCE=0
	 *  - Restore SLPM registers
	 *  - Any spurious wake up event during switch sequence to be ignored
	 *    and cleared
	 *
	 * We REALLY need to save ALL slpm registers, because the external
	 * IOFORCE will switch *all* ports to their sleepmode setting to as
	 * to avoid glitches. (Not just one port!)
	 */
1842
	glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891

	if (glitch) {
		spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);

		/* Initially don't put any pins to sleep when switching */
		memset(slpm, 0xff, sizeof(slpm));

		/*
		 * Then mask the pins that need to be sleeping now when we're
		 * switching to the ALT C function.
		 */
		for (i = 0; i < g->npins; i++)
			slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
		nmk_gpio_glitch_slpm_init(slpm);
	}

	for (i = 0; i < g->npins; i++) {
		struct pinctrl_gpio_range *range;
		struct nmk_gpio_chip *nmk_chip;
		struct gpio_chip *chip;
		unsigned bit;

		range = nmk_match_gpio_range(pctldev, g->pins[i]);
		if (!range) {
			dev_err(npct->dev,
				"invalid pin offset %d in group %s at index %d\n",
				g->pins[i], g->name, i);
			goto out_glitch;
		}
		if (!range->gc) {
			dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
				g->pins[i], g->name, i);
			goto out_glitch;
		}
		chip = range->gc;
		nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
		dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);

		clk_enable(nmk_chip->clk);
		bit = g->pins[i] % NMK_GPIO_PER_CHIP;
		/*
		 * If the pin is switching to altfunc, and there was an
		 * interrupt installed on it which has been lazy disabled,
		 * actually mask the interrupt to prevent spurious interrupts
		 * that would occur while the pin is under control of the
		 * peripheral. Only SKE does this.
		 */
		nmk_gpio_disable_lazy_irq(nmk_chip, bit);

1892 1893
		__nmk_gpio_set_mode_safe(nmk_chip, bit,
			(g->altsetting & NMK_GPIO_ALT_C), glitch);
1894
		clk_disable(nmk_chip->clk);
1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906

		/*
		 * Call PRCM GPIOCR config function in case ALTC
		 * has been selected:
		 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
		 *   must be set.
		 * - If selection is pure ALTC and previous selection was ALTCx,
		 *   then some bits in PRCM GPIOCR registers must be cleared.
		 */
		if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
			nmk_prcm_altcx_set_mode(npct, g->pins[i],
				g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
	}

	/* When all pins are successfully reconfigured we get here */
	ret = 0;

out_glitch:
	if (glitch) {
		nmk_gpio_glitch_slpm_restore(slpm);
		spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
	}

	return ret;
}

static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
			    unsigned function, unsigned group)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	const struct nmk_pingroup *g;

	g = &npct->soc->groups[group];

	if (g->altsetting < 0)
		return;

	/* Poke out the mux, set the pin to some default state? */
	dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
}

1936 1937 1938
static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
				   struct pinctrl_gpio_range *range,
				   unsigned offset)
1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	struct nmk_gpio_chip *nmk_chip;
	struct gpio_chip *chip;
	unsigned bit;

	if (!range) {
		dev_err(npct->dev, "invalid range\n");
		return -EINVAL;
	}
	if (!range->gc) {
		dev_err(npct->dev, "missing GPIO chip in range\n");
		return -EINVAL;
	}
	chip = range->gc;
	nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);

	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);

	clk_enable(nmk_chip->clk);
	bit = offset % NMK_GPIO_PER_CHIP;
	/* There is no glitch when converting any pin to GPIO */
	__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
	clk_disable(nmk_chip->clk);

	return 0;
}

1967 1968 1969
static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
				  struct pinctrl_gpio_range *range,
				  unsigned offset)
1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
	/* Set the pin to some default state, GPIO is usually default */
}

static struct pinmux_ops nmk_pinmux_ops = {
	.get_functions_count = nmk_pmx_get_funcs_cnt,
	.get_function_name = nmk_pmx_get_func_name,
	.get_function_groups = nmk_pmx_get_func_groups,
	.enable = nmk_pmx_enable,
	.disable = nmk_pmx_disable,
	.gpio_request_enable = nmk_gpio_request_enable,
	.gpio_disable_free = nmk_gpio_disable_free,
};

1987 1988
static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
			      unsigned long *config)
1989 1990 1991 1992 1993
{
	/* Not implemented */
	return -EINVAL;
}

1994 1995
static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
			      unsigned long config)
1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
{
	static const char *pullnames[] = {
		[NMK_GPIO_PULL_NONE]	= "none",
		[NMK_GPIO_PULL_UP]	= "up",
		[NMK_GPIO_PULL_DOWN]	= "down",
		[3] /* illegal */	= "??"
	};
	static const char *slpmnames[] = {
		[NMK_GPIO_SLPM_INPUT]		= "input/wakeup",
		[NMK_GPIO_SLPM_NOCHANGE]	= "no-change/no-wakeup",
	};
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	struct nmk_gpio_chip *nmk_chip;
	struct pinctrl_gpio_range *range;
	struct gpio_chip *chip;
	unsigned bit;

	/*
	 * The pin config contains pin number and altfunction fields, here
	 * we just ignore that part. It's being handled by the framework and
	 * pinmux callback respectively.
	 */
	pin_cfg_t cfg = (pin_cfg_t) config;
	int pull = PIN_PULL(cfg);
	int slpm = PIN_SLPM(cfg);
	int output = PIN_DIR(cfg);
	int val = PIN_VAL(cfg);
	bool lowemi = PIN_LOWEMI(cfg);
	bool gpiomode = PIN_GPIOMODE(cfg);
	bool sleep = PIN_SLEEPMODE(cfg);

	range = nmk_match_gpio_range(pctldev, pin);
	if (!range) {
		dev_err(npct->dev, "invalid pin offset %d\n", pin);
		return -EINVAL;
	}
	if (!range->gc) {
		dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
			pin);
		return -EINVAL;
	}
	chip = range->gc;
	nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);

	if (sleep) {
		int slpm_pull = PIN_SLPM_PULL(cfg);
		int slpm_output = PIN_SLPM_DIR(cfg);
		int slpm_val = PIN_SLPM_VAL(cfg);

		/* All pins go into GPIO mode at sleep */
		gpiomode = true;

		/*
		 * The SLPM_* values are normal values + 1 to allow zero to
		 * mean "same as normal".
		 */
		if (slpm_pull)
			pull = slpm_pull - 1;
		if (slpm_output)
			output = slpm_output - 1;
		if (slpm_val)
			val = slpm_val - 1;

		dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
			pin,
			slpm_pull ? pullnames[pull] : "same",
			slpm_output ? (output ? "output" : "input") : "same",
			slpm_val ? (val ? "high" : "low") : "same");
	}

	dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
		pin, cfg, pullnames[pull], slpmnames[slpm],
		output ? "output " : "input",
		output ? (val ? "high" : "low") : "",
		lowemi ? "on" : "off" );

	clk_enable(nmk_chip->clk);
	bit = pin % NMK_GPIO_PER_CHIP;
	if (gpiomode)
		/* No glitch when going to GPIO mode */
		__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
	if (output)
		__nmk_gpio_make_output(nmk_chip, bit, val);
	else {
		__nmk_gpio_make_input(nmk_chip, bit);
		__nmk_gpio_set_pull(nmk_chip, bit, pull);
	}
	/* TODO: isn't this only applicable on output pins? */
	__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);

	__nmk_gpio_set_slpm(nmk_chip, bit, slpm);
	clk_disable(nmk_chip->clk);
	return 0;
}

static struct pinconf_ops nmk_pinconf_ops = {
	.pin_config_get = nmk_pin_config_get,
	.pin_config_set = nmk_pin_config_set,
};

2096 2097 2098
static struct pinctrl_desc nmk_pinctrl_desc = {
	.name = "pinctrl-nomadik",
	.pctlops = &nmk_pinctrl_ops,
2099
	.pmxops = &nmk_pinmux_ops,
2100
	.confops = &nmk_pinconf_ops,
2101 2102 2103
	.owner = THIS_MODULE,
};

2104 2105
static const struct of_device_id nmk_pinctrl_match[] = {
	{
2106
		.compatible = "stericsson,nmk-pinctrl",
2107 2108 2109 2110 2111
		.data = (void *)PINCTRL_NMK_DB8500,
	},
	{},
};

2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133
static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct nmk_pinctrl *npct;

	npct = platform_get_drvdata(pdev);
	if (!npct)
		return -EINVAL;

	return pinctrl_force_sleep(npct->pctl);
}

static int nmk_pinctrl_resume(struct platform_device *pdev)
{
	struct nmk_pinctrl *npct;

	npct = platform_get_drvdata(pdev);
	if (!npct)
		return -EINVAL;

	return pinctrl_force_default(npct->pctl);
}

2134
static int nmk_pinctrl_probe(struct platform_device *pdev)
2135 2136
{
	const struct platform_device_id *platid = platform_get_device_id(pdev);
2137
	struct device_node *np = pdev->dev.of_node;
2138
	struct nmk_pinctrl *npct;
2139
	struct resource *res;
2140
	unsigned int version = 0;
2141 2142 2143 2144 2145 2146
	int i;

	npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
	if (!npct)
		return -ENOMEM;

2147 2148
	if (platid)
		version = platid->driver_data;
2149 2150 2151 2152 2153 2154 2155 2156
	else if (np) {
		const struct of_device_id *match;

		match = of_match_device(nmk_pinctrl_match, &pdev->dev);
		if (!match)
			return -ENODEV;
		version = (unsigned int) match->data;
	}
2157

2158
	/* Poke in other ASIC variants here */
2159 2160
	if (version == PINCTRL_NMK_STN8815)
		nmk_pinctrl_stn8815_init(&npct->soc);
2161
	if (version == PINCTRL_NMK_DB8500)
2162
		nmk_pinctrl_db8500_init(&npct->soc);
2163 2164
	if (version == PINCTRL_NMK_DB8540)
		nmk_pinctrl_db8540_init(&npct->soc);
2165

2166 2167 2168 2169 2170 2171 2172 2173 2174
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res) {
		npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
					       resource_size(res));
		if (!npct->prcm_base) {
			dev_err(&pdev->dev,
				"failed to ioremap PRCM registers\n");
			return -ENOMEM;
		}
2175
	} else if (version == PINCTRL_NMK_STN8815) {
2176 2177
		dev_info(&pdev->dev,
			 "No PRCM base, assume no ALT-Cx control is available\n");
2178 2179 2180
	} else {
		dev_err(&pdev->dev, "missing PRCM base address\n");
		return -EINVAL;
2181 2182
	}

2183 2184 2185 2186 2187 2188
	/*
	 * We need all the GPIO drivers to probe FIRST, or we will not be able
	 * to obtain references to the struct gpio_chip * for them, and we
	 * need this to proceed.
	 */
	for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
2189
		if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
2190 2191 2192
			dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
			return -EPROBE_DEFER;
		}
2193
		npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
2194 2195 2196 2197 2198
	}

	nmk_pinctrl_desc.pins = npct->soc->pins;
	nmk_pinctrl_desc.npins = npct->soc->npins;
	npct->dev = &pdev->dev;
2199

2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215
	npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
	if (!npct->pctl) {
		dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
		return -EINVAL;
	}

	/* We will handle a range of GPIO pins */
	for (i = 0; i < npct->soc->gpio_num_ranges; i++)
		pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);

	platform_set_drvdata(pdev, npct);
	dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");

	return 0;
}

2216 2217 2218 2219 2220
static const struct of_device_id nmk_gpio_match[] = {
	{ .compatible = "st,nomadik-gpio", },
	{}
};

2221 2222
static struct platform_driver nmk_gpio_driver = {
	.driver = {
2223 2224
		.owner = THIS_MODULE,
		.name = "gpio",
2225
		.of_match_table = nmk_gpio_match,
2226
	},
2227 2228 2229
	.probe = nmk_gpio_probe,
};

2230 2231 2232
static const struct platform_device_id nmk_pinctrl_id[] = {
	{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
	{ "pinctrl-db8500", PINCTRL_NMK_DB8500 },
2233
	{ "pinctrl-db8540", PINCTRL_NMK_DB8540 },
2234
	{ }
2235 2236 2237 2238 2239 2240
};

static struct platform_driver nmk_pinctrl_driver = {
	.driver = {
		.owner = THIS_MODULE,
		.name = "pinctrl-nomadik",
2241
		.of_match_table = nmk_pinctrl_match,
2242 2243 2244
	},
	.probe = nmk_pinctrl_probe,
	.id_table = nmk_pinctrl_id,
2245 2246 2247 2248
#ifdef CONFIG_PM
	.suspend = nmk_pinctrl_suspend,
	.resume = nmk_pinctrl_resume,
#endif
2249 2250
};

2251 2252
static int __init nmk_gpio_init(void)
{
2253 2254 2255 2256 2257 2258
	int ret;

	ret = platform_driver_register(&nmk_gpio_driver);
	if (ret)
		return ret;
	return platform_driver_register(&nmk_pinctrl_driver);
2259 2260
}

2261
core_initcall(nmk_gpio_init);
2262 2263 2264 2265

MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
MODULE_DESCRIPTION("Nomadik GPIO Driver");
MODULE_LICENSE("GPL");