core.c 56.3 KB
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/*
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 * Performance events x86 architecture code
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 *
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 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
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 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
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 *
 *  For licencing details see kernel-base/COPYING
 */

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#include <linux/perf_event.h>
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#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
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#include <linux/module.h>
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#include <linux/kdebug.h>
#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/cpu.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <asm/apic.h>
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#include <asm/stacktrace.h>
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#include <asm/nmi.h>
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#include <asm/smp.h>
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#include <asm/alternative.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/timer.h>
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#include <asm/desc.h>
#include <asm/ldt.h>
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#include "perf_event.h"
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struct x86_pmu x86_pmu __read_mostly;
43

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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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	.enabled = 1,
};
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struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;

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u64 __read_mostly hw_cache_event_ids
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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u64 __read_mostly hw_cache_extra_regs
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
58

59
/*
60 61
 * Propagate event elapsed time into the generic event.
 * Can only be executed on the CPU where the event is active.
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 * Returns the delta events processed.
 */
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u64 x86_perf_event_update(struct perf_event *event)
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{
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	struct hw_perf_event *hwc = &event->hw;
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	int shift = 64 - x86_pmu.cntval_bits;
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	u64 prev_raw_count, new_raw_count;
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	int idx = hwc->idx;
70
	s64 delta;
71

72
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
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		return 0;

75
	/*
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	 * Careful: an NMI might modify the previous event value.
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	 *
	 * Our tactic to handle this is to first atomically read and
	 * exchange a new raw count - then add that new-prev delta
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	 * count to the generic event atomically:
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	 */
again:
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	prev_raw_count = local64_read(&hwc->prev_count);
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	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
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86
	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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					new_raw_count) != prev_raw_count)
		goto again;

	/*
	 * Now we have the new raw value and have updated the prev
	 * timestamp already. We can now calculate the elapsed delta
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	 * (event-)time and add that to the generic event.
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	 *
	 * Careful, not all hw sign-extends above the physical width
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	 * of the count.
97
	 */
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	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;
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	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
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	return new_raw_count;
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}

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/*
 * Find and validate any extra registers to set up.
 */
static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
{
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	struct hw_perf_event_extra *reg;
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	struct extra_reg *er;

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	reg = &event->hw.extra_reg;
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	if (!x86_pmu.extra_regs)
		return 0;

	for (er = x86_pmu.extra_regs; er->msr; er++) {
		if (er->event != (config & er->config_mask))
			continue;
		if (event->attr.config1 & ~er->valid_mask)
			return -EINVAL;
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		/* Check if the extra msrs can be safely accessed*/
		if (!er->extra_msr_access)
			return -ENXIO;
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		reg->idx = er->idx;
		reg->config = event->attr.config1;
		reg->reg = er->msr;
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		break;
	}
	return 0;
}

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static atomic_t active_events;
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static atomic_t pmc_refcount;
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static DEFINE_MUTEX(pmc_reserve_mutex);

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#ifdef CONFIG_X86_LOCAL_APIC

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static bool reserve_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
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			goto perfctr_fail;
	}

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
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			goto eventsel_fail;
	}

	return true;

eventsel_fail:
	for (i--; i >= 0; i--)
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		release_evntsel_nmi(x86_pmu_config_addr(i));
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	i = x86_pmu.num_counters;
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perfctr_fail:
	for (i--; i >= 0; i--)
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		release_perfctr_nmi(x86_pmu_event_addr(i));
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	return false;
}

static void release_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		release_perfctr_nmi(x86_pmu_event_addr(i));
		release_evntsel_nmi(x86_pmu_config_addr(i));
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	}
}

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#else

static bool reserve_pmc_hardware(void) { return true; }
static void release_pmc_hardware(void) {}

#endif

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static bool check_hw_exists(void)
{
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	u64 val, val_fail, val_new= ~0;
	int i, reg, reg_fail, ret = 0;
	int bios_fail = 0;
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	int reg_safe = -1;
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	/*
	 * Check to see if the BIOS enabled any of the counters, if so
	 * complain and bail.
	 */
	for (i = 0; i < x86_pmu.num_counters; i++) {
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		reg = x86_pmu_config_addr(i);
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		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
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		if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
			bios_fail = 1;
			val_fail = val;
			reg_fail = reg;
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		} else {
			reg_safe = i;
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		}
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	}

	if (x86_pmu.num_counters_fixed) {
		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
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			if (val & (0x03 << i*4)) {
				bios_fail = 1;
				val_fail = val;
				reg_fail = reg;
			}
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		}
	}

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	/*
	 * If all the counters are enabled, the below test will always
	 * fail.  The tools will also become useless in this scenario.
	 * Just fail and disable the hardware counters.
	 */

	if (reg_safe == -1) {
		reg = reg_safe;
		goto msr_fail;
	}

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	/*
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	 * Read the current value, change it and read it back to see if it
	 * matches, this is needed to detect certain hardware emulators
	 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
243
	 */
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	reg = x86_pmu_event_addr(reg_safe);
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	if (rdmsrl_safe(reg, &val))
		goto msr_fail;
	val ^= 0xffffUL;
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	ret = wrmsrl_safe(reg, val);
	ret |= rdmsrl_safe(reg, &val_new);
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	if (ret || val != val_new)
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		goto msr_fail;
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	/*
	 * We still allow the PMU driver to operate:
	 */
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	if (bios_fail) {
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		pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
		pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
			      reg_fail, val_fail);
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	}
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	return true;
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msr_fail:
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	pr_cont("Broken PMU hardware detected, using software events only.\n");
	pr_info("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
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		boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
		reg, val_new);
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	return false;
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}

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static void hw_perf_event_destroy(struct perf_event *event)
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{
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	x86_release_hardware();
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	atomic_dec(&active_events);
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}

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void hw_perf_lbr_event_destroy(struct perf_event *event)
{
	hw_perf_event_destroy(event);

	/* undo the lbr/bts event accounting */
	x86_del_exclusive(x86_lbr_exclusive_lbr);
}

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static inline int x86_pmu_initialized(void)
{
	return x86_pmu.handle_irq != NULL;
}

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static inline int
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set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
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{
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	struct perf_event_attr *attr = &event->attr;
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	unsigned int cache_type, cache_op, cache_result;
	u64 config, val;

	config = attr->config;

	cache_type = (config >>  0) & 0xff;
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;

	val = hw_cache_event_ids[cache_type][cache_op][cache_result];

	if (val == 0)
		return -ENOENT;

	if (val == -1)
		return -EINVAL;

	hwc->config |= val;
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	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
	return x86_pmu_extra_regs(val, event);
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}

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int x86_reserve_hardware(void)
{
	int err = 0;

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	if (!atomic_inc_not_zero(&pmc_refcount)) {
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		mutex_lock(&pmc_reserve_mutex);
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		if (atomic_read(&pmc_refcount) == 0) {
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			if (!reserve_pmc_hardware())
				err = -EBUSY;
			else
				reserve_ds_buffers();
		}
		if (!err)
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			atomic_inc(&pmc_refcount);
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		mutex_unlock(&pmc_reserve_mutex);
	}

	return err;
}

void x86_release_hardware(void)
{
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	if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
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		release_pmc_hardware();
		release_ds_buffers();
		mutex_unlock(&pmc_reserve_mutex);
	}
}

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/*
 * Check if we can create event of a certain type (that no conflicting events
 * are present).
 */
int x86_add_exclusive(unsigned int what)
{
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	int i;
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	if (x86_pmu.lbr_pt_coexist)
		return 0;

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	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
		mutex_lock(&pmc_reserve_mutex);
		for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
			if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
				goto fail_unlock;
		}
		atomic_inc(&x86_pmu.lbr_exclusive[what]);
		mutex_unlock(&pmc_reserve_mutex);
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	}
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	atomic_inc(&active_events);
	return 0;
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fail_unlock:
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	mutex_unlock(&pmc_reserve_mutex);
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	return -EBUSY;
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}

void x86_del_exclusive(unsigned int what)
{
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	if (x86_pmu.lbr_pt_coexist)
		return;

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	atomic_dec(&x86_pmu.lbr_exclusive[what]);
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	atomic_dec(&active_events);
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}

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int x86_setup_perfctr(struct perf_event *event)
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{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	u64 config;

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	if (!is_sampling_event(event)) {
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		hwc->sample_period = x86_pmu.max_period;
		hwc->last_period = hwc->sample_period;
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		local64_set(&hwc->period_left, hwc->sample_period);
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	}

	if (attr->type == PERF_TYPE_RAW)
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		return x86_pmu_extra_regs(event->attr.config, event);
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	if (attr->type == PERF_TYPE_HW_CACHE)
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		return set_ext_hw_attr(hwc, event);
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	if (attr->config >= x86_pmu.max_events)
		return -EINVAL;

	/*
	 * The generic map:
	 */
	config = x86_pmu.event_map(attr->config);

	if (config == 0)
		return -ENOENT;

	if (config == -1LL)
		return -EINVAL;

	/*
	 * Branch tracing:
	 */
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	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
	    !attr->freq && hwc->sample_period == 1) {
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		/* BTS is not supported by this architecture. */
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		if (!x86_pmu.bts_active)
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			return -EOPNOTSUPP;

		/* BTS is currently only allowed for user-mode. */
		if (!attr->exclude_kernel)
			return -EOPNOTSUPP;
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		/* disallow bts if conflicting events are present */
		if (x86_add_exclusive(x86_lbr_exclusive_lbr))
			return -EBUSY;

		event->destroy = hw_perf_lbr_event_destroy;
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	}

	hwc->config |= config;

	return 0;
}
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/*
 * check that branch_sample_type is compatible with
 * settings needed for precise_ip > 1 which implies
 * using the LBR to capture ALL taken branches at the
 * priv levels of the measurement
 */
static inline int precise_br_compat(struct perf_event *event)
{
	u64 m = event->attr.branch_sample_type;
	u64 b = 0;

	/* must capture all branches */
	if (!(m & PERF_SAMPLE_BRANCH_ANY))
		return 0;

	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_user)
		b |= PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_kernel)
		b |= PERF_SAMPLE_BRANCH_KERNEL;

	/*
	 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
	 */

	return m == b;
}

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int x86_pmu_hw_config(struct perf_event *event)
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{
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	if (event->attr.precise_ip) {
		int precise = 0;

		/* Support for constant skid */
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		if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
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			precise++;

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			/* Support for IP fixup */
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			if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
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				precise++;
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			if (x86_pmu.pebs_prec_dist)
				precise++;
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		}
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		if (event->attr.precise_ip > precise)
			return -EOPNOTSUPP;
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	}
	/*
	 * check that PEBS LBR correction does not conflict with
	 * whatever the user is asking with attr->branch_sample_type
	 */
	if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
		u64 *br_type = &event->attr.branch_sample_type;

		if (has_branch_stack(event)) {
			if (!precise_br_compat(event))
				return -EOPNOTSUPP;

			/* branch_sample_type is compatible */

		} else {
			/*
			 * user did not specify  branch_sample_type
			 *
			 * For PEBS fixups, we capture all
			 * the branches at the priv level of the
			 * event.
			 */
			*br_type = PERF_SAMPLE_BRANCH_ANY;

			if (!event->attr.exclude_user)
				*br_type |= PERF_SAMPLE_BRANCH_USER;

			if (!event->attr.exclude_kernel)
				*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
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		}
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	}

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	if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
		event->attach_state |= PERF_ATTACH_TASK_DATA;

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	/*
	 * Generate PMC IRQs:
	 * (keep 'enabled' bit clear for now)
	 */
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	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
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	/*
	 * Count user and OS events unless requested not to
	 */
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	if (!event->attr.exclude_user)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
	if (!event->attr.exclude_kernel)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
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	if (event->attr.type == PERF_TYPE_RAW)
		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
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	if (event->attr.sample_period && x86_pmu.limit_period) {
		if (x86_pmu.limit_period(event, event->attr.sample_period) >
				event->attr.sample_period)
			return -EINVAL;
	}

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	return x86_setup_perfctr(event);
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}

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/*
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 * Setup the hardware configuration for a given attr_type
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 */
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static int __x86_pmu_event_init(struct perf_event *event)
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{
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	int err;
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	if (!x86_pmu_initialized())
		return -ENODEV;
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	err = x86_reserve_hardware();
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	if (err)
		return err;

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	atomic_inc(&active_events);
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	event->destroy = hw_perf_event_destroy;
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	event->hw.idx = -1;
	event->hw.last_cpu = -1;
	event->hw.last_tag = ~0ULL;
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	/* mark unused */
	event->hw.extra_reg.idx = EXTRA_REG_NONE;
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	event->hw.branch_reg.idx = EXTRA_REG_NONE;

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	return x86_pmu.hw_config(event);
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}

588
void x86_pmu_disable_all(void)
589
{
590
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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	int idx;

593
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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		u64 val;

596
		if (!test_bit(idx, cpuc->active_mask))
597
			continue;
598
		rdmsrl(x86_pmu_config_addr(idx), val);
599
		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
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			continue;
601
		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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		wrmsrl(x86_pmu_config_addr(idx), val);
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	}
}

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/*
 * There may be PMI landing after enabled=0. The PMI hitting could be before or
 * after disable_all.
 *
 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
 * It will not be re-enabled in the NMI handler again, because enabled=0. After
 * handling the NMI, disable_all will be called, which will not change the
 * state either. If PMI hits after disable_all, the PMU is already disabled
 * before entering NMI handler. The NMI handler will not change the state
 * either.
 *
 * So either situation is harmless.
 */
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static void x86_pmu_disable(struct pmu *pmu)
620
{
621
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
622

623
	if (!x86_pmu_initialized())
624
		return;
625

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	if (!cpuc->enabled)
		return;

	cpuc->n_added = 0;
	cpuc->enabled = 0;
	barrier();
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	x86_pmu.disable_all();
634
}
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636
void x86_pmu_enable_all(int added)
637
{
638
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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	int idx;

641
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
642
		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
643

644
		if (!test_bit(idx, cpuc->active_mask))
645
			continue;
646

647
		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
648 649 650
	}
}

P
Peter Zijlstra 已提交
651
static struct pmu pmu;
652 653 654 655 656 657

static inline int is_x86_event(struct perf_event *event)
{
	return event->pmu == &pmu;
}

658 659 660 661 662 663 664 665 666 667 668 669
/*
 * Event scheduler state:
 *
 * Assign events iterating over all events and counters, beginning
 * with events with least weights first. Keep the current iterator
 * state in struct sched_state.
 */
struct sched_state {
	int	weight;
	int	event;		/* event index */
	int	counter;	/* counter index */
	int	unassigned;	/* number of events to be assigned left */
670
	int	nr_gp;		/* number of GP counters used */
671 672 673
	unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
};

674 675 676
/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
#define	SCHED_STATES_MAX	2

677 678 679
struct perf_sched {
	int			max_weight;
	int			max_events;
680 681
	int			max_gp;
	int			saved_states;
682
	struct event_constraint	**constraints;
683
	struct sched_state	state;
684
	struct sched_state	saved[SCHED_STATES_MAX];
685 686 687 688 689
};

/*
 * Initialize interator that runs through all events and counters.
 */
690
static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
691
			    int num, int wmin, int wmax, int gpmax)
692 693 694 695 696 697
{
	int idx;

	memset(sched, 0, sizeof(*sched));
	sched->max_events	= num;
	sched->max_weight	= wmax;
698
	sched->max_gp		= gpmax;
699
	sched->constraints	= constraints;
700 701

	for (idx = 0; idx < num; idx++) {
702
		if (constraints[idx]->weight == wmin)
703 704 705 706 707 708 709 710
			break;
	}

	sched->state.event	= idx;		/* start with min weight */
	sched->state.weight	= wmin;
	sched->state.unassigned	= num;
}

711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733
static void perf_sched_save_state(struct perf_sched *sched)
{
	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
		return;

	sched->saved[sched->saved_states] = sched->state;
	sched->saved_states++;
}

static bool perf_sched_restore_state(struct perf_sched *sched)
{
	if (!sched->saved_states)
		return false;

	sched->saved_states--;
	sched->state = sched->saved[sched->saved_states];

	/* continue with next counter: */
	clear_bit(sched->state.counter++, sched->state.used);

	return true;
}

734 735 736 737
/*
 * Select a counter for the current event to schedule. Return true on
 * success.
 */
738
static bool __perf_sched_find_counter(struct perf_sched *sched)
739 740 741 742 743 744 745 746 747 748
{
	struct event_constraint *c;
	int idx;

	if (!sched->state.unassigned)
		return false;

	if (sched->state.event >= sched->max_events)
		return false;

749
	c = sched->constraints[sched->state.event];
750
	/* Prefer fixed purpose counters */
751 752
	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
		idx = INTEL_PMC_IDX_FIXED;
753
		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
754 755 756 757
			if (!__test_and_set_bit(idx, sched->state.used))
				goto done;
		}
	}
758

759 760
	/* Grab the first unused counter starting with idx */
	idx = sched->state.counter;
761
	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
762 763 764 765
		if (!__test_and_set_bit(idx, sched->state.used)) {
			if (sched->state.nr_gp++ >= sched->max_gp)
				return false;

766
			goto done;
767
		}
768 769
	}

770 771 772 773
	return false;

done:
	sched->state.counter = idx;
774

775 776 777 778 779 780 781 782 783 784 785 786 787
	if (c->overlap)
		perf_sched_save_state(sched);

	return true;
}

static bool perf_sched_find_counter(struct perf_sched *sched)
{
	while (!__perf_sched_find_counter(sched)) {
		if (!perf_sched_restore_state(sched))
			return false;
	}

788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811
	return true;
}

/*
 * Go through all unassigned events and find the next one to schedule.
 * Take events with the least weight first. Return true on success.
 */
static bool perf_sched_next_event(struct perf_sched *sched)
{
	struct event_constraint *c;

	if (!sched->state.unassigned || !--sched->state.unassigned)
		return false;

	do {
		/* next event */
		sched->state.event++;
		if (sched->state.event >= sched->max_events) {
			/* next weight */
			sched->state.event = 0;
			sched->state.weight++;
			if (sched->state.weight > sched->max_weight)
				return false;
		}
812
		c = sched->constraints[sched->state.event];
813 814 815 816 817 818 819 820 821 822
	} while (c->weight != sched->state.weight);

	sched->state.counter = 0;	/* start with first counter */

	return true;
}

/*
 * Assign a counter for each event.
 */
823
int perf_assign_events(struct event_constraint **constraints, int n,
824
			int wmin, int wmax, int gpmax, int *assign)
825 826 827
{
	struct perf_sched sched;

828
	perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
829 830 831 832 833 834 835 836 837 838

	do {
		if (!perf_sched_find_counter(&sched))
			break;	/* failed */
		if (assign)
			assign[sched.state.event] = sched.state.counter;
	} while (perf_sched_next_event(&sched));

	return sched.state.unassigned;
}
839
EXPORT_SYMBOL_GPL(perf_assign_events);
840

841
int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
842
{
843
	struct event_constraint *c;
844
	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
845
	struct perf_event *e;
846
	int i, wmin, wmax, unsched = 0;
847 848 849 850
	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

851 852 853
	if (x86_pmu.start_scheduling)
		x86_pmu.start_scheduling(cpuc);

854
	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
855
		cpuc->event_constraint[i] = NULL;
856
		c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
857
		cpuc->event_constraint[i] = c;
858

859 860
		wmin = min(wmin, c->weight);
		wmax = max(wmax, c->weight);
861 862
	}

863 864 865
	/*
	 * fastpath, try to reuse previous register
	 */
866
	for (i = 0; i < n; i++) {
867
		hwc = &cpuc->event_list[i]->hw;
868
		c = cpuc->event_constraint[i];
869 870 871 872 873 874

		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
875
		if (!test_bit(hwc->idx, c->idxmsk))
876 877 878 879 880 881
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

P
Peter Zijlstra 已提交
882
		__set_bit(hwc->idx, used_mask);
883 884 885 886
		if (assign)
			assign[i] = hwc->idx;
	}

887
	/* slow path */
888
	if (i != n) {
889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904
		int gpmax = x86_pmu.num_counters;

		/*
		 * Do not allow scheduling of more than half the available
		 * generic counters.
		 *
		 * This helps avoid counter starvation of sibling thread by
		 * ensuring at most half the counters cannot be in exclusive
		 * mode. There is no designated counters for the limits. Any
		 * N/2 counters can be used. This helps with events with
		 * specific counter constraints.
		 */
		if (is_ht_workaround_enabled() && !cpuc->is_fake &&
		    READ_ONCE(cpuc->excl_cntrs->exclusive_present))
			gpmax /= 2;

905
		unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
906
					     wmax, gpmax, assign);
907
	}
908

909
	/*
910 911 912 913 914 915 916 917
	 * In case of success (unsched = 0), mark events as committed,
	 * so we do not put_constraint() in case new events are added
	 * and fail to be scheduled
	 *
	 * We invoke the lower level commit callback to lock the resource
	 *
	 * We do not need to do all of this in case we are called to
	 * validate an event group (assign == NULL)
918
	 */
919
	if (!unsched && assign) {
920 921 922
		for (i = 0; i < n; i++) {
			e = cpuc->event_list[i];
			e->hw.flags |= PERF_X86_EVENT_COMMITTED;
923
			if (x86_pmu.commit_scheduling)
924
				x86_pmu.commit_scheduling(cpuc, i, assign[i]);
925
		}
926
	} else {
927
		for (i = 0; i < n; i++) {
928 929 930 931 932 933 934 935
			e = cpuc->event_list[i];
			/*
			 * do not put_constraint() on comitted events,
			 * because they are good to go
			 */
			if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
				continue;

936 937 938
			/*
			 * release events that failed scheduling
			 */
939
			if (x86_pmu.put_event_constraints)
940
				x86_pmu.put_event_constraints(cpuc, e);
941 942
		}
	}
943 944 945 946

	if (x86_pmu.stop_scheduling)
		x86_pmu.stop_scheduling(cpuc);

947
	return unsched ? -EINVAL : 0;
948 949 950 951 952 953 954 955 956 957 958
}

/*
 * dogrp: true if must collect siblings events (group)
 * returns total number of events and error code
 */
static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
{
	struct perf_event *event;
	int n, max_count;

959
	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
960 961 962 963 964 965

	/* current number of events already accepted */
	n = cpuc->n_events;

	if (is_x86_event(leader)) {
		if (n >= max_count)
966
			return -EINVAL;
967 968 969 970 971 972 973 974
		cpuc->event_list[n] = leader;
		n++;
	}
	if (!dogrp)
		return n;

	list_for_each_entry(event, &leader->sibling_list, group_entry) {
		if (!is_x86_event(event) ||
975
		    event->state <= PERF_EVENT_STATE_OFF)
976 977 978
			continue;

		if (n >= max_count)
979
			return -EINVAL;
980 981 982 983 984 985 986 987

		cpuc->event_list[n] = event;
		n++;
	}
	return n;
}

static inline void x86_assign_hw_event(struct perf_event *event,
988
				struct cpu_hw_events *cpuc, int i)
989
{
990 991 992 993 994
	struct hw_perf_event *hwc = &event->hw;

	hwc->idx = cpuc->assign[i];
	hwc->last_cpu = smp_processor_id();
	hwc->last_tag = ++cpuc->tags[i];
995

996
	if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
997 998
		hwc->config_base = 0;
		hwc->event_base	= 0;
999
	} else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1000
		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1001 1002
		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
		hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1003
	} else {
1004 1005
		hwc->config_base = x86_pmu_config_addr(hwc->idx);
		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
1006
		hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1007 1008 1009
	}
}

1010 1011 1012 1013 1014 1015 1016 1017 1018
static inline int match_prev_assignment(struct hw_perf_event *hwc,
					struct cpu_hw_events *cpuc,
					int i)
{
	return hwc->idx == cpuc->assign[i] &&
		hwc->last_cpu == smp_processor_id() &&
		hwc->last_tag == cpuc->tags[i];
}

P
Peter Zijlstra 已提交
1019
static void x86_pmu_start(struct perf_event *event, int flags);
1020

P
Peter Zijlstra 已提交
1021
static void x86_pmu_enable(struct pmu *pmu)
1022
{
1023
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1024 1025
	struct perf_event *event;
	struct hw_perf_event *hwc;
1026
	int i, added = cpuc->n_added;
1027

1028
	if (!x86_pmu_initialized())
1029
		return;
1030 1031 1032 1033

	if (cpuc->enabled)
		return;

1034
	if (cpuc->n_added) {
1035
		int n_running = cpuc->n_events - cpuc->n_added;
1036 1037 1038 1039 1040 1041
		/*
		 * apply assignment obtained either from
		 * hw_perf_group_sched_in() or x86_pmu_enable()
		 *
		 * step1: save events moving to new counters
		 */
1042
		for (i = 0; i < n_running; i++) {
1043 1044 1045
			event = cpuc->event_list[i];
			hwc = &event->hw;

1046 1047 1048 1049 1050 1051 1052 1053
			/*
			 * we can avoid reprogramming counter if:
			 * - assigned same counter as last time
			 * - running on same CPU as last time
			 * - no other event has used the counter since
			 */
			if (hwc->idx == -1 ||
			    match_prev_assignment(hwc, cpuc, i))
1054 1055
				continue;

P
Peter Zijlstra 已提交
1056 1057 1058 1059 1060 1061 1062 1063
			/*
			 * Ensure we don't accidentally enable a stopped
			 * counter simply because we rescheduled.
			 */
			if (hwc->state & PERF_HES_STOPPED)
				hwc->state |= PERF_HES_ARCH;

			x86_pmu_stop(event, PERF_EF_UPDATE);
1064 1065
		}

1066 1067 1068
		/*
		 * step2: reprogram moved events into new counters
		 */
1069 1070 1071 1072
		for (i = 0; i < cpuc->n_events; i++) {
			event = cpuc->event_list[i];
			hwc = &event->hw;

1073
			if (!match_prev_assignment(hwc, cpuc, i))
1074
				x86_assign_hw_event(event, cpuc, i);
1075 1076
			else if (i < n_running)
				continue;
1077

P
Peter Zijlstra 已提交
1078 1079 1080 1081
			if (hwc->state & PERF_HES_ARCH)
				continue;

			x86_pmu_start(event, PERF_EF_RELOAD);
1082 1083 1084 1085
		}
		cpuc->n_added = 0;
		perf_events_lapic_init();
	}
1086 1087 1088 1089

	cpuc->enabled = 1;
	barrier();

1090
	x86_pmu.enable_all(added);
1091 1092
}

1093
static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
I
Ingo Molnar 已提交
1094

1095 1096
/*
 * Set the next IRQ period, based on the hwc->period_left value.
1097
 * To be called with the event disabled in hw:
1098
 */
1099
int x86_perf_event_set_period(struct perf_event *event)
I
Ingo Molnar 已提交
1100
{
1101
	struct hw_perf_event *hwc = &event->hw;
1102
	s64 left = local64_read(&hwc->period_left);
1103
	s64 period = hwc->sample_period;
1104
	int ret = 0, idx = hwc->idx;
1105

1106
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
1107 1108
		return 0;

1109
	/*
1110
	 * If we are way outside a reasonable range then just skip forward:
1111 1112 1113
	 */
	if (unlikely(left <= -period)) {
		left = period;
1114
		local64_set(&hwc->period_left, left);
1115
		hwc->last_period = period;
1116
		ret = 1;
1117 1118 1119 1120
	}

	if (unlikely(left <= 0)) {
		left += period;
1121
		local64_set(&hwc->period_left, left);
1122
		hwc->last_period = period;
1123
		ret = 1;
1124
	}
1125
	/*
1126
	 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1127 1128 1129
	 */
	if (unlikely(left < 2))
		left = 2;
I
Ingo Molnar 已提交
1130

1131 1132 1133
	if (left > x86_pmu.max_period)
		left = x86_pmu.max_period;

1134 1135 1136
	if (x86_pmu.limit_period)
		left = x86_pmu.limit_period(event, left);

1137
	per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1138

1139 1140 1141 1142 1143 1144 1145
	if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
	    local64_read(&hwc->prev_count) != (u64)-left) {
		/*
		 * The hw event starts counting from this event offset,
		 * mark it to be able to extra future deltas:
		 */
		local64_set(&hwc->prev_count, (u64)-left);
1146

1147 1148
		wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
	}
1149 1150 1151 1152 1153 1154 1155

	/*
	 * Due to erratum on certan cpu we need
	 * a second write to be sure the register
	 * is updated properly
	 */
	if (x86_pmu.perfctr_second_write) {
1156
		wrmsrl(hwc->event_base,
1157
			(u64)(-left) & x86_pmu.cntval_mask);
1158
	}
1159

1160
	perf_event_update_userpage(event);
1161

1162
	return ret;
1163 1164
}

1165
void x86_pmu_enable_event(struct perf_event *event)
1166
{
T
Tejun Heo 已提交
1167
	if (__this_cpu_read(cpu_hw_events.enabled))
1168 1169
		__x86_pmu_enable_event(&event->hw,
				       ARCH_PERFMON_EVENTSEL_ENABLE);
I
Ingo Molnar 已提交
1170 1171
}

1172
/*
P
Peter Zijlstra 已提交
1173
 * Add a single event to the PMU.
1174 1175 1176
 *
 * The event is added to the group of enabled events
 * but only if it can be scehduled with existing events.
1177
 */
P
Peter Zijlstra 已提交
1178
static int x86_pmu_add(struct perf_event *event, int flags)
1179
{
1180
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1181 1182 1183
	struct hw_perf_event *hwc;
	int assign[X86_PMC_IDX_MAX];
	int n, n0, ret;
1184

1185
	hwc = &event->hw;
1186

1187
	n0 = cpuc->n_events;
1188 1189 1190
	ret = n = collect_events(cpuc, event, false);
	if (ret < 0)
		goto out;
1191

P
Peter Zijlstra 已提交
1192 1193 1194 1195
	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
	if (!(flags & PERF_EF_START))
		hwc->state |= PERF_HES_ARCH;

1196 1197
	/*
	 * If group events scheduling transaction was started,
L
Lucas De Marchi 已提交
1198
	 * skip the schedulability test here, it will be performed
1199
	 * at commit time (->commit_txn) as a whole.
1200
	 */
1201
	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1202
		goto done_collect;
1203

1204
	ret = x86_pmu.schedule_events(cpuc, n, assign);
1205
	if (ret)
1206
		goto out;
1207 1208 1209 1210 1211
	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));
1212

1213
done_collect:
1214 1215 1216 1217
	/*
	 * Commit the collect_events() state. See x86_pmu_del() and
	 * x86_pmu_*_txn().
	 */
1218
	cpuc->n_events = n;
1219
	cpuc->n_added += n - n0;
1220
	cpuc->n_txn += n - n0;
1221

1222 1223 1224
	ret = 0;
out:
	return ret;
I
Ingo Molnar 已提交
1225 1226
}

P
Peter Zijlstra 已提交
1227
static void x86_pmu_start(struct perf_event *event, int flags)
1228
{
1229
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
P
Peter Zijlstra 已提交
1230 1231
	int idx = event->hw.idx;

P
Peter Zijlstra 已提交
1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(idx == -1))
		return;

	if (flags & PERF_EF_RELOAD) {
		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
		x86_perf_event_set_period(event);
	}

	event->hw.state = 0;
1244

P
Peter Zijlstra 已提交
1245 1246
	cpuc->events[idx] = event;
	__set_bit(idx, cpuc->active_mask);
1247
	__set_bit(idx, cpuc->running);
1248
	x86_pmu.enable(event);
P
Peter Zijlstra 已提交
1249
	perf_event_update_userpage(event);
1250 1251
}

1252
void perf_event_print_debug(void)
I
Ingo Molnar 已提交
1253
{
1254
	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
A
Andi Kleen 已提交
1255
	u64 pebs, debugctl;
1256
	struct cpu_hw_events *cpuc;
1257
	unsigned long flags;
1258 1259
	int cpu, idx;

1260
	if (!x86_pmu.num_counters)
1261
		return;
I
Ingo Molnar 已提交
1262

1263
	local_irq_save(flags);
I
Ingo Molnar 已提交
1264 1265

	cpu = smp_processor_id();
1266
	cpuc = &per_cpu(cpu_hw_events, cpu);
I
Ingo Molnar 已提交
1267

1268
	if (x86_pmu.version >= 2) {
1269 1270 1271 1272 1273 1274 1275 1276 1277 1278
		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);

		pr_info("\n");
		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
		pr_info("CPU#%d: status:     %016llx\n", cpu, status);
		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1279 1280 1281 1282
		if (x86_pmu.pebs_constraints) {
			rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
			pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
		}
A
Andi Kleen 已提交
1283 1284 1285 1286
		if (x86_pmu.lbr_nr) {
			rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
			pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
		}
1287
	}
1288
	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
I
Ingo Molnar 已提交
1289

1290
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1291 1292
		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
I
Ingo Molnar 已提交
1293

1294
		prev_left = per_cpu(pmc_prev_left[idx], cpu);
I
Ingo Molnar 已提交
1295

1296
		pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
I
Ingo Molnar 已提交
1297
			cpu, idx, pmc_ctrl);
1298
		pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
I
Ingo Molnar 已提交
1299
			cpu, idx, pmc_count);
1300
		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1301
			cpu, idx, prev_left);
I
Ingo Molnar 已提交
1302
	}
1303
	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1304 1305
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);

1306
		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1307 1308
			cpu, idx, pmc_count);
	}
1309
	local_irq_restore(flags);
I
Ingo Molnar 已提交
1310 1311
}

1312
void x86_pmu_stop(struct perf_event *event, int flags)
I
Ingo Molnar 已提交
1313
{
1314
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1315
	struct hw_perf_event *hwc = &event->hw;
I
Ingo Molnar 已提交
1316

P
Peter Zijlstra 已提交
1317 1318 1319 1320 1321 1322
	if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
		x86_pmu.disable(event);
		cpuc->events[hwc->idx] = NULL;
		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
		hwc->state |= PERF_HES_STOPPED;
	}
1323

P
Peter Zijlstra 已提交
1324 1325 1326 1327 1328 1329 1330 1331
	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		/*
		 * Drain the remaining delta count out of a event
		 * that we are disabling:
		 */
		x86_perf_event_update(event);
		hwc->state |= PERF_HES_UPTODATE;
	}
1332 1333
}

P
Peter Zijlstra 已提交
1334
static void x86_pmu_del(struct perf_event *event, int flags)
1335
{
1336
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1337 1338
	int i;

1339 1340 1341 1342 1343
	/*
	 * event is descheduled
	 */
	event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;

1344 1345 1346 1347
	/*
	 * If we're called during a txn, we don't need to do anything.
	 * The events never got scheduled and ->cancel_txn will truncate
	 * the event_list.
1348 1349 1350
	 *
	 * XXX assumes any ->del() called during a TXN will only be on
	 * an event added during that same TXN.
1351
	 */
1352
	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1353 1354
		return;

1355 1356 1357
	/*
	 * Not a TXN, therefore cleanup properly.
	 */
P
Peter Zijlstra 已提交
1358
	x86_pmu_stop(event, PERF_EF_UPDATE);
1359

1360
	for (i = 0; i < cpuc->n_events; i++) {
1361 1362 1363
		if (event == cpuc->event_list[i])
			break;
	}
1364

1365 1366
	if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
		return;
P
Peter Zijlstra 已提交
1367

1368 1369 1370
	/* If we have a newly added event; make sure to decrease n_added. */
	if (i >= cpuc->n_events - cpuc->n_added)
		--cpuc->n_added;
1371

1372 1373 1374 1375
	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(cpuc, event);

	/* Delete the array entry. */
1376
	while (++i < cpuc->n_events) {
1377
		cpuc->event_list[i-1] = cpuc->event_list[i];
1378 1379
		cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
	}
1380
	--cpuc->n_events;
1381

1382
	perf_event_update_userpage(event);
I
Ingo Molnar 已提交
1383 1384
}

1385
int x86_pmu_handle_irq(struct pt_regs *regs)
1386
{
1387
	struct perf_sample_data data;
1388 1389
	struct cpu_hw_events *cpuc;
	struct perf_event *event;
V
Vince Weaver 已提交
1390
	int idx, handled = 0;
1391 1392
	u64 val;

1393
	cpuc = this_cpu_ptr(&cpu_hw_events);
1394

1395 1396 1397 1398 1399 1400 1401 1402 1403 1404
	/*
	 * Some chipsets need to unmask the LVTPC in a particular spot
	 * inside the nmi handler.  As a result, the unmasking was pushed
	 * into all the nmi handlers.
	 *
	 * This generic handler doesn't seem to have any issues where the
	 * unmasking occurs so it was left at the top.
	 */
	apic_write(APIC_LVTPC, APIC_DM_NMI);

1405
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1406 1407 1408 1409 1410 1411 1412 1413
		if (!test_bit(idx, cpuc->active_mask)) {
			/*
			 * Though we deactivated the counter some cpus
			 * might still deliver spurious interrupts still
			 * in flight. Catch them:
			 */
			if (__test_and_clear_bit(idx, cpuc->running))
				handled++;
1414
			continue;
1415
		}
1416

1417
		event = cpuc->events[idx];
1418

1419
		val = x86_perf_event_update(event);
1420
		if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1421
			continue;
1422

1423
		/*
1424
		 * event overflow
1425
		 */
1426
		handled++;
1427
		perf_sample_data_init(&data, 0, event->hw.last_period);
1428

1429
		if (!x86_perf_event_set_period(event))
1430 1431
			continue;

1432
		if (perf_event_overflow(event, &data, regs))
P
Peter Zijlstra 已提交
1433
			x86_pmu_stop(event, 0);
1434
	}
1435

1436 1437 1438
	if (handled)
		inc_irq_stat(apic_perf_irqs);

1439 1440
	return handled;
}
1441

1442
void perf_events_lapic_init(void)
I
Ingo Molnar 已提交
1443
{
1444
	if (!x86_pmu.apic || !x86_pmu_initialized())
I
Ingo Molnar 已提交
1445
		return;
1446

I
Ingo Molnar 已提交
1447
	/*
1448
	 * Always use NMI for PMU
I
Ingo Molnar 已提交
1449
	 */
1450
	apic_write(APIC_LVTPC, APIC_DM_NMI);
I
Ingo Molnar 已提交
1451 1452
}

1453
static int
1454
perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
I
Ingo Molnar 已提交
1455
{
1456 1457
	u64 start_clock;
	u64 finish_clock;
P
Peter Zijlstra 已提交
1458
	int ret;
1459

1460 1461 1462 1463
	/*
	 * All PMUs/events that share this PMI handler should make sure to
	 * increment active_events for their events.
	 */
1464
	if (!atomic_read(&active_events))
1465
		return NMI_DONE;
1466

P
Peter Zijlstra 已提交
1467
	start_clock = sched_clock();
1468
	ret = x86_pmu.handle_irq(regs);
P
Peter Zijlstra 已提交
1469
	finish_clock = sched_clock();
1470 1471 1472 1473

	perf_sample_event_took(finish_clock - start_clock);

	return ret;
I
Ingo Molnar 已提交
1474
}
1475
NOKPROBE_SYMBOL(perf_event_nmi_handler);
I
Ingo Molnar 已提交
1476

1477 1478
struct event_constraint emptyconstraint;
struct event_constraint unconstrained;
1479

1480
static int
1481 1482 1483
x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
	unsigned int cpu = (long)hcpu;
1484
	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1485
	int i, ret = NOTIFY_OK;
1486 1487 1488

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_UP_PREPARE:
1489 1490
		for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
			cpuc->kfree_on_online[i] = NULL;
1491
		if (x86_pmu.cpu_prepare)
1492
			ret = x86_pmu.cpu_prepare(cpu);
1493 1494 1495 1496 1497 1498 1499
		break;

	case CPU_STARTING:
		if (x86_pmu.cpu_starting)
			x86_pmu.cpu_starting(cpu);
		break;

1500
	case CPU_ONLINE:
1501 1502 1503 1504
		for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
			kfree(cpuc->kfree_on_online[i]);
			cpuc->kfree_on_online[i] = NULL;
		}
1505 1506
		break;

1507 1508 1509 1510 1511
	case CPU_DYING:
		if (x86_pmu.cpu_dying)
			x86_pmu.cpu_dying(cpu);
		break;

1512
	case CPU_UP_CANCELED:
1513 1514 1515 1516 1517 1518 1519 1520 1521
	case CPU_DEAD:
		if (x86_pmu.cpu_dead)
			x86_pmu.cpu_dead(cpu);
		break;

	default:
		break;
	}

1522
	return ret;
1523 1524
}

1525 1526 1527 1528 1529 1530 1531 1532
static void __init pmu_check_apic(void)
{
	if (cpu_has_apic)
		return;

	x86_pmu.apic = 0;
	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
	pr_info("no hardware sampling interrupt available.\n");
1533 1534 1535 1536 1537 1538 1539 1540 1541

	/*
	 * If we have a PMU initialized but no APIC
	 * interrupts, we cannot sample hardware
	 * events (user-space has to fall back and
	 * sample via a hrtimer based software event):
	 */
	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;

1542 1543
}

1544 1545 1546 1547 1548
static struct attribute_group x86_pmu_format_group = {
	.name = "format",
	.attrs = NULL,
};

1549 1550 1551 1552 1553 1554
/*
 * Remove all undefined events (x86_pmu.event_map(id) == 0)
 * out of events_attr attributes.
 */
static void __init filter_events(struct attribute **attrs)
{
1555 1556
	struct device_attribute *d;
	struct perf_pmu_events_attr *pmu_attr;
1557
	int offset = 0;
1558 1559 1560
	int i, j;

	for (i = 0; attrs[i]; i++) {
1561 1562 1563 1564 1565
		d = (struct device_attribute *)attrs[i];
		pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
		/* str trumps id */
		if (pmu_attr->event_str)
			continue;
1566
		if (x86_pmu.event_map(i + offset))
1567 1568 1569 1570 1571 1572 1573
			continue;

		for (j = i; attrs[j]; j++)
			attrs[j] = attrs[j + 1];

		/* Check the shifted attr. */
		i--;
1574 1575 1576 1577 1578 1579 1580 1581

		/*
		 * event_map() is index based, the attrs array is organized
		 * by increasing event index. If we shift the events, then
		 * we need to compensate for the event_map(), otherwise
		 * we are looking up the wrong event in the map
		 */
		offset++;
1582 1583 1584
	}
}

1585
/* Merge two pointer arrays */
1586
__init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610
{
	struct attribute **new;
	int j, i;

	for (j = 0; a[j]; j++)
		;
	for (i = 0; b[i]; i++)
		j++;
	j++;

	new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
	if (!new)
		return NULL;

	j = 0;
	for (i = 0; a[i]; i++)
		new[j++] = a[i];
	for (i = 0; b[i]; i++)
		new[j++] = b[i];
	new[j] = NULL;

	return new;
}

1611
ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1612 1613 1614 1615 1616
{
	struct perf_pmu_events_attr *pmu_attr = \
		container_of(attr, struct perf_pmu_events_attr, attr);
	u64 config = x86_pmu.event_map(pmu_attr->id);

1617 1618 1619
	/* string trumps id */
	if (pmu_attr->event_str)
		return sprintf(page, "%s", pmu_attr->event_str);
1620

1621 1622
	return x86_pmu.events_sysfs_show(page, config);
}
1623
EXPORT_SYMBOL_GPL(events_sysfs_show);
1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637

EVENT_ATTR(cpu-cycles,			CPU_CYCLES		);
EVENT_ATTR(instructions,		INSTRUCTIONS		);
EVENT_ATTR(cache-references,		CACHE_REFERENCES	);
EVENT_ATTR(cache-misses, 		CACHE_MISSES		);
EVENT_ATTR(branch-instructions,		BRANCH_INSTRUCTIONS	);
EVENT_ATTR(branch-misses,		BRANCH_MISSES		);
EVENT_ATTR(bus-cycles,			BUS_CYCLES		);
EVENT_ATTR(stalled-cycles-frontend,	STALLED_CYCLES_FRONTEND	);
EVENT_ATTR(stalled-cycles-backend,	STALLED_CYCLES_BACKEND	);
EVENT_ATTR(ref-cycles,			REF_CPU_CYCLES		);

static struct attribute *empty_attrs;

P
Peter Huewe 已提交
1638
static struct attribute *events_attr[] = {
1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
	EVENT_PTR(CPU_CYCLES),
	EVENT_PTR(INSTRUCTIONS),
	EVENT_PTR(CACHE_REFERENCES),
	EVENT_PTR(CACHE_MISSES),
	EVENT_PTR(BRANCH_INSTRUCTIONS),
	EVENT_PTR(BRANCH_MISSES),
	EVENT_PTR(BUS_CYCLES),
	EVENT_PTR(STALLED_CYCLES_FRONTEND),
	EVENT_PTR(STALLED_CYCLES_BACKEND),
	EVENT_PTR(REF_CPU_CYCLES),
	NULL,
};

static struct attribute_group x86_pmu_events_group = {
	.name = "events",
	.attrs = events_attr,
};

1657
ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695
{
	u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
	u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
	bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
	bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
	bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
	bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
	ssize_t ret;

	/*
	* We have whole page size to spend and just little data
	* to write, so we can safely use sprintf.
	*/
	ret = sprintf(page, "event=0x%02llx", event);

	if (umask)
		ret += sprintf(page + ret, ",umask=0x%02llx", umask);

	if (edge)
		ret += sprintf(page + ret, ",edge");

	if (pc)
		ret += sprintf(page + ret, ",pc");

	if (any)
		ret += sprintf(page + ret, ",any");

	if (inv)
		ret += sprintf(page + ret, ",inv");

	if (cmask)
		ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);

	ret += sprintf(page + ret, "\n");

	return ret;
}

1696
static int __init init_hw_perf_events(void)
1697
{
1698
	struct x86_pmu_quirk *quirk;
1699 1700
	int err;

1701
	pr_info("Performance Events: ");
1702

1703 1704
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_INTEL:
1705
		err = intel_pmu_init();
1706
		break;
1707
	case X86_VENDOR_AMD:
1708
		err = amd_pmu_init();
1709
		break;
1710
	default:
1711
		err = -ENOTSUPP;
1712
	}
1713
	if (err != 0) {
1714
		pr_cont("no PMU driver, software events only.\n");
1715
		return 0;
1716
	}
1717

1718 1719
	pmu_check_apic();

1720
	/* sanity check that the hardware exists or is emulated */
1721
	if (!check_hw_exists())
1722
		return 0;
1723

1724
	pr_cont("%s PMU driver.\n", x86_pmu.name);
1725

1726 1727
	x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */

1728 1729
	for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
		quirk->func();
1730

1731 1732
	if (!x86_pmu.intel_ctrl)
		x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
I
Ingo Molnar 已提交
1733

1734
	perf_events_lapic_init();
1735
	register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1736

1737
	unconstrained = (struct event_constraint)
1738
		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1739
				   0, x86_pmu.num_counters, 0, 0);
1740

1741
	x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1742

1743 1744 1745
	if (x86_pmu.event_attrs)
		x86_pmu_events_group.attrs = x86_pmu.event_attrs;

1746 1747
	if (!x86_pmu.events_sysfs_show)
		x86_pmu_events_group.attrs = &empty_attrs;
1748 1749
	else
		filter_events(x86_pmu_events_group.attrs);
1750

1751 1752 1753 1754 1755 1756 1757 1758
	if (x86_pmu.cpu_events) {
		struct attribute **tmp;

		tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
		if (!WARN_ON(!tmp))
			x86_pmu_events_group.attrs = tmp;
	}

I
Ingo Molnar 已提交
1759
	pr_info("... version:                %d\n",     x86_pmu.version);
1760 1761 1762
	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
I
Ingo Molnar 已提交
1763
	pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1764
	pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1765
	pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1766

P
Peter Zijlstra 已提交
1767
	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1768
	perf_cpu_notifier(x86_pmu_notifier);
1769 1770

	return 0;
I
Ingo Molnar 已提交
1771
}
1772
early_initcall(init_hw_perf_events);
I
Ingo Molnar 已提交
1773

1774
static inline void x86_pmu_read(struct perf_event *event)
1775
{
1776
	x86_perf_event_update(event);
1777 1778
}

1779 1780 1781 1782
/*
 * Start group events scheduling transaction
 * Set the flag to make pmu::enable() not perform the
 * schedulability test, it will be performed at commit time
1783 1784 1785 1786
 *
 * We only support PERF_PMU_TXN_ADD transactions. Save the
 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
 * transactions.
1787
 */
1788
static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1789
{
1790 1791 1792 1793 1794 1795 1796 1797
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	WARN_ON_ONCE(cpuc->txn_flags);		/* txn already in flight */

	cpuc->txn_flags = txn_flags;
	if (txn_flags & ~PERF_PMU_TXN_ADD)
		return;

P
Peter Zijlstra 已提交
1798
	perf_pmu_disable(pmu);
T
Tejun Heo 已提交
1799
	__this_cpu_write(cpu_hw_events.n_txn, 0);
1800 1801 1802 1803 1804 1805 1806
}

/*
 * Stop group events scheduling transaction
 * Clear the flag and pmu::enable() will perform the
 * schedulability test.
 */
P
Peter Zijlstra 已提交
1807
static void x86_pmu_cancel_txn(struct pmu *pmu)
1808
{
1809 1810 1811 1812 1813 1814 1815 1816 1817 1818
	unsigned int txn_flags;
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	WARN_ON_ONCE(!cpuc->txn_flags);	/* no txn in flight */

	txn_flags = cpuc->txn_flags;
	cpuc->txn_flags = 0;
	if (txn_flags & ~PERF_PMU_TXN_ADD)
		return;

1819
	/*
1820 1821
	 * Truncate collected array by the number of events added in this
	 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1822
	 */
T
Tejun Heo 已提交
1823 1824
	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
P
Peter Zijlstra 已提交
1825
	perf_pmu_enable(pmu);
1826 1827 1828 1829 1830 1831
}

/*
 * Commit group events scheduling transaction
 * Perform the group schedulability test as a whole
 * Return 0 if success
1832 1833
 *
 * Does not cancel the transaction on failure; expects the caller to do this.
1834
 */
P
Peter Zijlstra 已提交
1835
static int x86_pmu_commit_txn(struct pmu *pmu)
1836
{
1837
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1838 1839 1840
	int assign[X86_PMC_IDX_MAX];
	int n, ret;

1841 1842 1843 1844 1845 1846 1847
	WARN_ON_ONCE(!cpuc->txn_flags);	/* no txn in flight */

	if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
		cpuc->txn_flags = 0;
		return 0;
	}

1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862
	n = cpuc->n_events;

	if (!x86_pmu_initialized())
		return -EAGAIN;

	ret = x86_pmu.schedule_events(cpuc, n, assign);
	if (ret)
		return ret;

	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));

1863
	cpuc->txn_flags = 0;
P
Peter Zijlstra 已提交
1864
	perf_pmu_enable(pmu);
1865 1866
	return 0;
}
1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895
/*
 * a fake_cpuc is used to validate event groups. Due to
 * the extra reg logic, we need to also allocate a fake
 * per_core and per_cpu structure. Otherwise, group events
 * using extra reg may conflict without the kernel being
 * able to catch this when the last event gets added to
 * the group.
 */
static void free_fake_cpuc(struct cpu_hw_events *cpuc)
{
	kfree(cpuc->shared_regs);
	kfree(cpuc);
}

static struct cpu_hw_events *allocate_fake_cpuc(void)
{
	struct cpu_hw_events *cpuc;
	int cpu = raw_smp_processor_id();

	cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
	if (!cpuc)
		return ERR_PTR(-ENOMEM);

	/* only needed, if we have extra_regs */
	if (x86_pmu.extra_regs) {
		cpuc->shared_regs = allocate_shared_regs(cpu);
		if (!cpuc->shared_regs)
			goto error;
	}
1896
	cpuc->is_fake = 1;
1897 1898 1899 1900 1901
	return cpuc;
error:
	free_fake_cpuc(cpuc);
	return ERR_PTR(-ENOMEM);
}
1902

1903 1904 1905 1906 1907 1908 1909 1910 1911
/*
 * validate that we can schedule this event
 */
static int validate_event(struct perf_event *event)
{
	struct cpu_hw_events *fake_cpuc;
	struct event_constraint *c;
	int ret = 0;

1912 1913 1914
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1915

1916
	c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1917 1918

	if (!c || !c->weight)
1919
		ret = -EINVAL;
1920 1921 1922 1923

	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(fake_cpuc, event);

1924
	free_fake_cpuc(fake_cpuc);
1925 1926 1927 1928

	return ret;
}

1929 1930 1931 1932
/*
 * validate a single event group
 *
 * validation include:
1933 1934 1935
 *	- check events are compatible which each other
 *	- events do not compete for the same counter
 *	- number of events <= number of counters
1936 1937 1938 1939
 *
 * validation ensures the group can be loaded onto the
 * PMU if it was the only group available.
 */
1940 1941
static int validate_group(struct perf_event *event)
{
1942
	struct perf_event *leader = event->group_leader;
1943
	struct cpu_hw_events *fake_cpuc;
1944
	int ret = -EINVAL, n;
1945

1946 1947 1948
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1949 1950 1951 1952 1953 1954
	/*
	 * the event is not yet connected with its
	 * siblings therefore we must first collect
	 * existing siblings, then add the new event
	 * before we can simulate the scheduling
	 */
1955
	n = collect_events(fake_cpuc, leader, true);
1956
	if (n < 0)
1957
		goto out;
1958

1959 1960
	fake_cpuc->n_events = n;
	n = collect_events(fake_cpuc, event, false);
1961
	if (n < 0)
1962
		goto out;
1963

1964
	fake_cpuc->n_events = n;
1965

1966
	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1967 1968

out:
1969
	free_fake_cpuc(fake_cpuc);
1970
	return ret;
1971 1972
}

1973
static int x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
1974
{
P
Peter Zijlstra 已提交
1975
	struct pmu *tmp;
I
Ingo Molnar 已提交
1976 1977
	int err;

1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988
	switch (event->attr.type) {
	case PERF_TYPE_RAW:
	case PERF_TYPE_HARDWARE:
	case PERF_TYPE_HW_CACHE:
		break;

	default:
		return -ENOENT;
	}

	err = __x86_pmu_event_init(event);
1989
	if (!err) {
1990 1991 1992 1993 1994 1995 1996 1997
		/*
		 * we temporarily connect event to its pmu
		 * such that validate_group() can classify
		 * it as an x86 event using is_x86_event()
		 */
		tmp = event->pmu;
		event->pmu = &pmu;

1998 1999
		if (event->group_leader != event)
			err = validate_group(event);
2000 2001
		else
			err = validate_event(event);
2002 2003

		event->pmu = tmp;
2004
	}
2005
	if (err) {
2006 2007
		if (event->destroy)
			event->destroy(event);
2008
	}
I
Ingo Molnar 已提交
2009

2010 2011 2012
	if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
		event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;

2013
	return err;
I
Ingo Molnar 已提交
2014
}
2015

2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042
static void refresh_pce(void *ignored)
{
	if (current->mm)
		load_mm_cr4(current->mm);
}

static void x86_pmu_event_mapped(struct perf_event *event)
{
	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
		return;

	if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
		on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
}

static void x86_pmu_event_unmapped(struct perf_event *event)
{
	if (!current->mm)
		return;

	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
		return;

	if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
		on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
}

2043 2044 2045 2046
static int x86_pmu_event_idx(struct perf_event *event)
{
	int idx = event->hw.idx;

2047
	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2048 2049
		return 0;

2050 2051
	if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
		idx -= INTEL_PMC_IDX_FIXED;
2052 2053 2054 2055 2056 2057
		idx |= 1 << 30;
	}

	return idx + 1;
}

2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068
static ssize_t get_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      char *buf)
{
	return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
}

static ssize_t set_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      const char *buf, size_t count)
{
2069 2070 2071 2072 2073 2074
	unsigned long val;
	ssize_t ret;

	ret = kstrtoul(buf, 0, &val);
	if (ret)
		return ret;
2075

2076 2077 2078
	if (val > 2)
		return -EINVAL;

2079 2080
	if (x86_pmu.attr_rdpmc_broken)
		return -ENOTSUPP;
2081

2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096
	if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
		/*
		 * Changing into or out of always available, aka
		 * perf-event-bypassing mode.  This path is extremely slow,
		 * but only root can trigger it, so it's okay.
		 */
		if (val == 2)
			static_key_slow_inc(&rdpmc_always_available);
		else
			static_key_slow_dec(&rdpmc_always_available);
		on_each_cpu(refresh_pce, NULL, 1);
	}

	x86_pmu.attr_rdpmc = val;

2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112
	return count;
}

static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);

static struct attribute *x86_pmu_attrs[] = {
	&dev_attr_rdpmc.attr,
	NULL,
};

static struct attribute_group x86_pmu_attr_group = {
	.attrs = x86_pmu_attrs,
};

static const struct attribute_group *x86_pmu_attr_groups[] = {
	&x86_pmu_attr_group,
2113
	&x86_pmu_format_group,
2114
	&x86_pmu_events_group,
2115 2116 2117
	NULL,
};

2118
static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2119
{
2120 2121
	if (x86_pmu.sched_task)
		x86_pmu.sched_task(ctx, sched_in);
2122 2123
}

2124 2125 2126 2127 2128 2129 2130
void perf_check_microcode(void)
{
	if (x86_pmu.check_microcode)
		x86_pmu.check_microcode();
}
EXPORT_SYMBOL_GPL(perf_check_microcode);

2131
static struct pmu pmu = {
2132 2133
	.pmu_enable		= x86_pmu_enable,
	.pmu_disable		= x86_pmu_disable,
P
Peter Zijlstra 已提交
2134

2135
	.attr_groups		= x86_pmu_attr_groups,
2136

2137
	.event_init		= x86_pmu_event_init,
P
Peter Zijlstra 已提交
2138

2139 2140 2141
	.event_mapped		= x86_pmu_event_mapped,
	.event_unmapped		= x86_pmu_event_unmapped,

2142 2143 2144 2145 2146
	.add			= x86_pmu_add,
	.del			= x86_pmu_del,
	.start			= x86_pmu_start,
	.stop			= x86_pmu_stop,
	.read			= x86_pmu_read,
P
Peter Zijlstra 已提交
2147

2148 2149 2150
	.start_txn		= x86_pmu_start_txn,
	.cancel_txn		= x86_pmu_cancel_txn,
	.commit_txn		= x86_pmu_commit_txn,
2151

2152
	.event_idx		= x86_pmu_event_idx,
2153
	.sched_task		= x86_pmu_sched_task,
2154
	.task_ctx_size          = sizeof(struct x86_perf_task_context),
2155 2156
};

2157 2158
void arch_perf_update_userpage(struct perf_event *event,
			       struct perf_event_mmap_page *userpg, u64 now)
2159
{
2160 2161
	struct cyc2ns_data *data;

2162 2163
	userpg->cap_user_time = 0;
	userpg->cap_user_time_zero = 0;
2164 2165
	userpg->cap_user_rdpmc =
		!!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2166 2167
	userpg->pmc_width = x86_pmu.cntval_bits;

2168
	if (!sched_clock_stable())
2169 2170
		return;

2171 2172
	data = cyc2ns_read_begin();

2173 2174 2175 2176
	/*
	 * Internal timekeeping for enabled/running/stopped times
	 * is always in the local_clock domain.
	 */
2177
	userpg->cap_user_time = 1;
2178 2179 2180
	userpg->time_mult = data->cyc2ns_mul;
	userpg->time_shift = data->cyc2ns_shift;
	userpg->time_offset = data->cyc2ns_offset - now;
2181

2182 2183 2184 2185 2186 2187 2188 2189
	/*
	 * cap_user_time_zero doesn't make sense when we're using a different
	 * time base for the records.
	 */
	if (event->clock == &local_clock) {
		userpg->cap_user_time_zero = 1;
		userpg->time_zero = data->cyc2ns_offset;
	}
2190 2191

	cyc2ns_read_end(data);
2192 2193
}

2194 2195 2196 2197 2198 2199
/*
 * callchain support
 */

static int backtrace_stack(void *data, char *name)
{
2200
	return 0;
2201 2202
}

2203
static int backtrace_address(void *data, unsigned long addr, int reliable)
2204 2205 2206
{
	struct perf_callchain_entry *entry = data;

2207
	return perf_callchain_store(entry, addr);
2208 2209 2210 2211 2212
}

static const struct stacktrace_ops backtrace_ops = {
	.stack			= backtrace_stack,
	.address		= backtrace_address,
2213
	.walk_stack		= print_context_stack_bp,
2214 2215
};

2216 2217
void
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2218
{
2219 2220
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
2221
		return;
2222 2223
	}

2224
	perf_callchain_store(entry, regs->ip);
2225

2226
	dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2227 2228
}

2229 2230 2231 2232 2233 2234
static inline int
valid_user_frame(const void __user *fp, unsigned long size)
{
	return (__range_not_ok(fp, size, TASK_SIZE) == 0);
}

2235 2236 2237 2238 2239 2240
static unsigned long get_segment_base(unsigned int segment)
{
	struct desc_struct *desc;
	int idx = segment >> 3;

	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2241
#ifdef CONFIG_MODIFY_LDT_SYSCALL
2242 2243
		struct ldt_struct *ldt;

2244 2245 2246
		if (idx > LDT_ENTRIES)
			return 0;

2247 2248 2249
		/* IRQs are off, so this synchronizes with smp_store_release */
		ldt = lockless_dereference(current->active_mm->context.ldt);
		if (!ldt || idx > ldt->size)
2250 2251
			return 0;

2252
		desc = &ldt->entries[idx];
2253 2254 2255
#else
		return 0;
#endif
2256 2257 2258 2259
	} else {
		if (idx > GDT_ENTRIES)
			return 0;

2260
		desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2261 2262
	}

2263
	return get_desc_base(desc);
2264 2265
}

2266
#ifdef CONFIG_IA32_EMULATION
H
H. Peter Anvin 已提交
2267 2268 2269

#include <asm/compat.h>

2270 2271
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2272
{
2273
	/* 32-bit process in 64-bit kernel. */
2274
	unsigned long ss_base, cs_base;
2275 2276
	struct stack_frame_ia32 frame;
	const void __user *fp;
2277

2278 2279 2280
	if (!test_thread_flag(TIF_IA32))
		return 0;

2281 2282 2283 2284
	cs_base = get_segment_base(regs->cs);
	ss_base = get_segment_base(regs->ss);

	fp = compat_ptr(ss_base + regs->bp);
2285
	pagefault_disable();
2286
	while (entry->nr < sysctl_perf_event_max_stack) {
2287 2288 2289 2290
		unsigned long bytes;
		frame.next_frame     = 0;
		frame.return_address = 0;

2291 2292 2293 2294 2295 2296 2297
		if (!access_ok(VERIFY_READ, fp, 8))
			break;

		bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
		if (bytes != 0)
			break;
		bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2298
		if (bytes != 0)
2299
			break;
2300

2301 2302 2303
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2304 2305
		perf_callchain_store(entry, cs_base + frame.return_address);
		fp = compat_ptr(ss_base + frame.next_frame);
2306
	}
2307
	pagefault_enable();
2308
	return 1;
2309
}
2310 2311 2312 2313 2314 2315 2316
#else
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
{
    return 0;
}
#endif
2317

2318 2319
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2320 2321 2322 2323
{
	struct stack_frame frame;
	const void __user *fp;

2324 2325
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
2326
		return;
2327
	}
2328

2329 2330 2331 2332 2333 2334
	/*
	 * We don't know what to do with VM86 stacks.. ignore them for now.
	 */
	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
		return;

2335
	fp = (void __user *)regs->bp;
2336

2337
	perf_callchain_store(entry, regs->ip);
2338

2339 2340 2341
	if (!current->mm)
		return;

2342 2343 2344
	if (perf_callchain_user32(regs, entry))
		return;

2345
	pagefault_disable();
2346
	while (entry->nr < sysctl_perf_event_max_stack) {
2347
		unsigned long bytes;
2348
		frame.next_frame	     = NULL;
2349 2350
		frame.return_address = 0;

2351 2352 2353 2354 2355 2356 2357
		if (!access_ok(VERIFY_READ, fp, 16))
			break;

		bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8);
		if (bytes != 0)
			break;
		bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8);
2358
		if (bytes != 0)
2359 2360
			break;

2361 2362 2363
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2364
		perf_callchain_store(entry, frame.return_address);
2365
		fp = (void __user *)frame.next_frame;
2366
	}
2367
	pagefault_enable();
2368 2369
}

2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383
/*
 * Deal with code segment offsets for the various execution modes:
 *
 *   VM86 - the good olde 16 bit days, where the linear address is
 *          20 bits and we use regs->ip + 0x10 * regs->cs.
 *
 *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
 *          to figure out what the 32bit base address is.
 *
 *    X32 - has TIF_X32 set, but is running in x86_64
 *
 * X86_64 - CS,DS,SS,ES are all zero based.
 */
static unsigned long code_segment_base(struct pt_regs *regs)
2384
{
2385 2386 2387 2388 2389 2390
	/*
	 * For IA32 we look at the GDT/LDT segment base to convert the
	 * effective IP to a linear address.
	 */

#ifdef CONFIG_X86_32
2391 2392 2393 2394 2395 2396 2397
	/*
	 * If we are in VM86 mode, add the segment offset to convert to a
	 * linear address.
	 */
	if (regs->flags & X86_VM_MASK)
		return 0x10 * regs->cs;

2398
	if (user_mode(regs) && regs->cs != __USER_CS)
2399 2400
		return get_segment_base(regs->cs);
#else
2401 2402 2403
	if (user_mode(regs) && !user_64bit_mode(regs) &&
	    regs->cs != __USER32_CS)
		return get_segment_base(regs->cs);
2404 2405 2406
#endif
	return 0;
}
2407

2408 2409
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
2410
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2411
		return perf_guest_cbs->get_guest_ip();
2412

2413
	return regs->ip + code_segment_base(regs);
2414 2415 2416 2417 2418
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
	int misc = 0;
2419

2420
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2421 2422 2423 2424 2425
		if (perf_guest_cbs->is_user_mode())
			misc |= PERF_RECORD_MISC_GUEST_USER;
		else
			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
	} else {
2426
		if (user_mode(regs))
2427 2428 2429 2430 2431
			misc |= PERF_RECORD_MISC_USER;
		else
			misc |= PERF_RECORD_MISC_KERNEL;
	}

2432
	if (regs->flags & PERF_EFLAGS_EXACT)
P
Peter Zijlstra 已提交
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		misc |= PERF_RECORD_MISC_EXACT_IP;
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	return misc;
}
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void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	cap->version		= x86_pmu.version;
	cap->num_counters_gp	= x86_pmu.num_counters;
	cap->num_counters_fixed	= x86_pmu.num_counters_fixed;
	cap->bit_width_gp	= x86_pmu.cntval_bits;
	cap->bit_width_fixed	= x86_pmu.cntval_bits;
	cap->events_mask	= (unsigned int)x86_pmu.events_maskl;
	cap->events_mask_len	= x86_pmu.events_mask_len;
}
EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);