core.c 56.2 KB
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/*
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 * Performance events x86 architecture code
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 *
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 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
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 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
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 *
 *  For licencing details see kernel-base/COPYING
 */

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#include <linux/perf_event.h>
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#include <linux/capability.h>
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
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#include <linux/module.h>
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#include <linux/kdebug.h>
#include <linux/sched.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/cpu.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <asm/apic.h>
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#include <asm/stacktrace.h>
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#include <asm/nmi.h>
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#include <asm/smp.h>
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#include <asm/alternative.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/timer.h>
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#include <asm/desc.h>
#include <asm/ldt.h>
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#include "perf_event.h"
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struct x86_pmu x86_pmu __read_mostly;
43

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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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	.enabled = 1,
};
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struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;

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u64 __read_mostly hw_cache_event_ids
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
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u64 __read_mostly hw_cache_extra_regs
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				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
58

59
/*
60 61
 * Propagate event elapsed time into the generic event.
 * Can only be executed on the CPU where the event is active.
62 63
 * Returns the delta events processed.
 */
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u64 x86_perf_event_update(struct perf_event *event)
65
{
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	struct hw_perf_event *hwc = &event->hw;
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	int shift = 64 - x86_pmu.cntval_bits;
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	u64 prev_raw_count, new_raw_count;
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	int idx = hwc->idx;
70
	s64 delta;
71

72
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
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		return 0;

75
	/*
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	 * Careful: an NMI might modify the previous event value.
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	 *
	 * Our tactic to handle this is to first atomically read and
	 * exchange a new raw count - then add that new-prev delta
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	 * count to the generic event atomically:
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	 */
again:
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	prev_raw_count = local64_read(&hwc->prev_count);
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	rdpmcl(hwc->event_base_rdpmc, new_raw_count);
85

86
	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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					new_raw_count) != prev_raw_count)
		goto again;

	/*
	 * Now we have the new raw value and have updated the prev
	 * timestamp already. We can now calculate the elapsed delta
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	 * (event-)time and add that to the generic event.
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	 *
	 * Careful, not all hw sign-extends above the physical width
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	 * of the count.
97
	 */
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	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;
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	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
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	return new_raw_count;
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}

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/*
 * Find and validate any extra registers to set up.
 */
static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
{
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	struct hw_perf_event_extra *reg;
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	struct extra_reg *er;

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	reg = &event->hw.extra_reg;
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	if (!x86_pmu.extra_regs)
		return 0;

	for (er = x86_pmu.extra_regs; er->msr; er++) {
		if (er->event != (config & er->config_mask))
			continue;
		if (event->attr.config1 & ~er->valid_mask)
			return -EINVAL;
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		/* Check if the extra msrs can be safely accessed*/
		if (!er->extra_msr_access)
			return -ENXIO;
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		reg->idx = er->idx;
		reg->config = event->attr.config1;
		reg->reg = er->msr;
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		break;
	}
	return 0;
}

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static atomic_t active_events;
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static atomic_t pmc_refcount;
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static DEFINE_MUTEX(pmc_reserve_mutex);

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#ifdef CONFIG_X86_LOCAL_APIC

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static bool reserve_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
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			goto perfctr_fail;
	}

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
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			goto eventsel_fail;
	}

	return true;

eventsel_fail:
	for (i--; i >= 0; i--)
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		release_evntsel_nmi(x86_pmu_config_addr(i));
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	i = x86_pmu.num_counters;
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perfctr_fail:
	for (i--; i >= 0; i--)
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		release_perfctr_nmi(x86_pmu_event_addr(i));
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	return false;
}

static void release_pmc_hardware(void)
{
	int i;

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	for (i = 0; i < x86_pmu.num_counters; i++) {
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		release_perfctr_nmi(x86_pmu_event_addr(i));
		release_evntsel_nmi(x86_pmu_config_addr(i));
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	}
}

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#else

static bool reserve_pmc_hardware(void) { return true; }
static void release_pmc_hardware(void) {}

#endif

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static bool check_hw_exists(void)
{
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	u64 val, val_fail, val_new= ~0;
	int i, reg, reg_fail, ret = 0;
	int bios_fail = 0;
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	int reg_safe = -1;
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	/*
	 * Check to see if the BIOS enabled any of the counters, if so
	 * complain and bail.
	 */
	for (i = 0; i < x86_pmu.num_counters; i++) {
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		reg = x86_pmu_config_addr(i);
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		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
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		if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
			bios_fail = 1;
			val_fail = val;
			reg_fail = reg;
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		} else {
			reg_safe = i;
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		}
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	}

	if (x86_pmu.num_counters_fixed) {
		reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
		ret = rdmsrl_safe(reg, &val);
		if (ret)
			goto msr_fail;
		for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
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			if (val & (0x03 << i*4)) {
				bios_fail = 1;
				val_fail = val;
				reg_fail = reg;
			}
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		}
	}

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	/*
	 * If all the counters are enabled, the below test will always
	 * fail.  The tools will also become useless in this scenario.
	 * Just fail and disable the hardware counters.
	 */

	if (reg_safe == -1) {
		reg = reg_safe;
		goto msr_fail;
	}

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	/*
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	 * Read the current value, change it and read it back to see if it
	 * matches, this is needed to detect certain hardware emulators
	 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
243
	 */
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	reg = x86_pmu_event_addr(reg_safe);
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	if (rdmsrl_safe(reg, &val))
		goto msr_fail;
	val ^= 0xffffUL;
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	ret = wrmsrl_safe(reg, val);
	ret |= rdmsrl_safe(reg, &val_new);
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	if (ret || val != val_new)
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		goto msr_fail;
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	/*
	 * We still allow the PMU driver to operate:
	 */
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	if (bios_fail) {
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		pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
		pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
			      reg_fail, val_fail);
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	}
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	return true;
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msr_fail:
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	pr_cont("Broken PMU hardware detected, using software events only.\n");
	pr_info("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
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		boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
		reg, val_new);
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	return false;
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}

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static void hw_perf_event_destroy(struct perf_event *event)
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{
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	x86_release_hardware();
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	atomic_dec(&active_events);
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}

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void hw_perf_lbr_event_destroy(struct perf_event *event)
{
	hw_perf_event_destroy(event);

	/* undo the lbr/bts event accounting */
	x86_del_exclusive(x86_lbr_exclusive_lbr);
}

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static inline int x86_pmu_initialized(void)
{
	return x86_pmu.handle_irq != NULL;
}

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static inline int
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set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
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{
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	struct perf_event_attr *attr = &event->attr;
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	unsigned int cache_type, cache_op, cache_result;
	u64 config, val;

	config = attr->config;

	cache_type = (config >>  0) & 0xff;
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return -EINVAL;

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return -EINVAL;

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return -EINVAL;

	val = hw_cache_event_ids[cache_type][cache_op][cache_result];

	if (val == 0)
		return -ENOENT;

	if (val == -1)
		return -EINVAL;

	hwc->config |= val;
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	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
	return x86_pmu_extra_regs(val, event);
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}

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int x86_reserve_hardware(void)
{
	int err = 0;

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	if (!atomic_inc_not_zero(&pmc_refcount)) {
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		mutex_lock(&pmc_reserve_mutex);
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		if (atomic_read(&pmc_refcount) == 0) {
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			if (!reserve_pmc_hardware())
				err = -EBUSY;
			else
				reserve_ds_buffers();
		}
		if (!err)
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			atomic_inc(&pmc_refcount);
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		mutex_unlock(&pmc_reserve_mutex);
	}

	return err;
}

void x86_release_hardware(void)
{
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	if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
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		release_pmc_hardware();
		release_ds_buffers();
		mutex_unlock(&pmc_reserve_mutex);
	}
}

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/*
 * Check if we can create event of a certain type (that no conflicting events
 * are present).
 */
int x86_add_exclusive(unsigned int what)
{
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	int i;
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	if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
		mutex_lock(&pmc_reserve_mutex);
		for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
			if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
				goto fail_unlock;
		}
		atomic_inc(&x86_pmu.lbr_exclusive[what]);
		mutex_unlock(&pmc_reserve_mutex);
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	}
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	atomic_inc(&active_events);
	return 0;
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fail_unlock:
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	mutex_unlock(&pmc_reserve_mutex);
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	return -EBUSY;
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}

void x86_del_exclusive(unsigned int what)
{
	atomic_dec(&x86_pmu.lbr_exclusive[what]);
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	atomic_dec(&active_events);
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}

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int x86_setup_perfctr(struct perf_event *event)
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{
	struct perf_event_attr *attr = &event->attr;
	struct hw_perf_event *hwc = &event->hw;
	u64 config;

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	if (!is_sampling_event(event)) {
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		hwc->sample_period = x86_pmu.max_period;
		hwc->last_period = hwc->sample_period;
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		local64_set(&hwc->period_left, hwc->sample_period);
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	}

	if (attr->type == PERF_TYPE_RAW)
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		return x86_pmu_extra_regs(event->attr.config, event);
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	if (attr->type == PERF_TYPE_HW_CACHE)
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		return set_ext_hw_attr(hwc, event);
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	if (attr->config >= x86_pmu.max_events)
		return -EINVAL;

	/*
	 * The generic map:
	 */
	config = x86_pmu.event_map(attr->config);

	if (config == 0)
		return -ENOENT;

	if (config == -1LL)
		return -EINVAL;

	/*
	 * Branch tracing:
	 */
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	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
	    !attr->freq && hwc->sample_period == 1) {
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		/* BTS is not supported by this architecture. */
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		if (!x86_pmu.bts_active)
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			return -EOPNOTSUPP;

		/* BTS is currently only allowed for user-mode. */
		if (!attr->exclude_kernel)
			return -EOPNOTSUPP;
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		/* disallow bts if conflicting events are present */
		if (x86_add_exclusive(x86_lbr_exclusive_lbr))
			return -EBUSY;

		event->destroy = hw_perf_lbr_event_destroy;
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	}

	hwc->config |= config;

	return 0;
}
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/*
 * check that branch_sample_type is compatible with
 * settings needed for precise_ip > 1 which implies
 * using the LBR to capture ALL taken branches at the
 * priv levels of the measurement
 */
static inline int precise_br_compat(struct perf_event *event)
{
	u64 m = event->attr.branch_sample_type;
	u64 b = 0;

	/* must capture all branches */
	if (!(m & PERF_SAMPLE_BRANCH_ANY))
		return 0;

	m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_user)
		b |= PERF_SAMPLE_BRANCH_USER;

	if (!event->attr.exclude_kernel)
		b |= PERF_SAMPLE_BRANCH_KERNEL;

	/*
	 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
	 */

	return m == b;
}

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int x86_pmu_hw_config(struct perf_event *event)
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{
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	if (event->attr.precise_ip) {
		int precise = 0;

		/* Support for constant skid */
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		if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
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			precise++;

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			/* Support for IP fixup */
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			if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
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				precise++;
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			if (x86_pmu.pebs_prec_dist)
				precise++;
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		}
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		if (event->attr.precise_ip > precise)
			return -EOPNOTSUPP;
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	}
	/*
	 * check that PEBS LBR correction does not conflict with
	 * whatever the user is asking with attr->branch_sample_type
	 */
	if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
		u64 *br_type = &event->attr.branch_sample_type;

		if (has_branch_stack(event)) {
			if (!precise_br_compat(event))
				return -EOPNOTSUPP;

			/* branch_sample_type is compatible */

		} else {
			/*
			 * user did not specify  branch_sample_type
			 *
			 * For PEBS fixups, we capture all
			 * the branches at the priv level of the
			 * event.
			 */
			*br_type = PERF_SAMPLE_BRANCH_ANY;

			if (!event->attr.exclude_user)
				*br_type |= PERF_SAMPLE_BRANCH_USER;

			if (!event->attr.exclude_kernel)
				*br_type |= PERF_SAMPLE_BRANCH_KERNEL;
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		}
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	}

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	if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
		event->attach_state |= PERF_ATTACH_TASK_DATA;

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	/*
	 * Generate PMC IRQs:
	 * (keep 'enabled' bit clear for now)
	 */
532
	event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
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	/*
	 * Count user and OS events unless requested not to
	 */
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	if (!event->attr.exclude_user)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
	if (!event->attr.exclude_kernel)
		event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
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	if (event->attr.type == PERF_TYPE_RAW)
		event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
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	if (event->attr.sample_period && x86_pmu.limit_period) {
		if (x86_pmu.limit_period(event, event->attr.sample_period) >
				event->attr.sample_period)
			return -EINVAL;
	}

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	return x86_setup_perfctr(event);
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}

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/*
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 * Setup the hardware configuration for a given attr_type
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 */
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static int __x86_pmu_event_init(struct perf_event *event)
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{
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	int err;
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	if (!x86_pmu_initialized())
		return -ENODEV;
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	err = x86_reserve_hardware();
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	if (err)
		return err;

568
	atomic_inc(&active_events);
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	event->destroy = hw_perf_event_destroy;
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	event->hw.idx = -1;
	event->hw.last_cpu = -1;
	event->hw.last_tag = ~0ULL;
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	/* mark unused */
	event->hw.extra_reg.idx = EXTRA_REG_NONE;
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	event->hw.branch_reg.idx = EXTRA_REG_NONE;

579
	return x86_pmu.hw_config(event);
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}

582
void x86_pmu_disable_all(void)
583
{
584
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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	int idx;

587
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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		u64 val;

590
		if (!test_bit(idx, cpuc->active_mask))
591
			continue;
592
		rdmsrl(x86_pmu_config_addr(idx), val);
593
		if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
594
			continue;
595
		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
596
		wrmsrl(x86_pmu_config_addr(idx), val);
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	}
}

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/*
 * There may be PMI landing after enabled=0. The PMI hitting could be before or
 * after disable_all.
 *
 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
 * It will not be re-enabled in the NMI handler again, because enabled=0. After
 * handling the NMI, disable_all will be called, which will not change the
 * state either. If PMI hits after disable_all, the PMU is already disabled
 * before entering NMI handler. The NMI handler will not change the state
 * either.
 *
 * So either situation is harmless.
 */
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static void x86_pmu_disable(struct pmu *pmu)
614
{
615
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
616

617
	if (!x86_pmu_initialized())
618
		return;
619

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	if (!cpuc->enabled)
		return;

	cpuc->n_added = 0;
	cpuc->enabled = 0;
	barrier();
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	x86_pmu.disable_all();
628
}
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630
void x86_pmu_enable_all(int added)
631
{
632
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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	int idx;

635
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
636
		struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
637

638
		if (!test_bit(idx, cpuc->active_mask))
639
			continue;
640

641
		__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
642 643 644
	}
}

P
Peter Zijlstra 已提交
645
static struct pmu pmu;
646 647 648 649 650 651

static inline int is_x86_event(struct perf_event *event)
{
	return event->pmu == &pmu;
}

652 653 654 655 656 657 658 659 660 661 662 663
/*
 * Event scheduler state:
 *
 * Assign events iterating over all events and counters, beginning
 * with events with least weights first. Keep the current iterator
 * state in struct sched_state.
 */
struct sched_state {
	int	weight;
	int	event;		/* event index */
	int	counter;	/* counter index */
	int	unassigned;	/* number of events to be assigned left */
664
	int	nr_gp;		/* number of GP counters used */
665 666 667
	unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
};

668 669 670
/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
#define	SCHED_STATES_MAX	2

671 672 673
struct perf_sched {
	int			max_weight;
	int			max_events;
674 675
	int			max_gp;
	int			saved_states;
676
	struct event_constraint	**constraints;
677
	struct sched_state	state;
678
	struct sched_state	saved[SCHED_STATES_MAX];
679 680 681 682 683
};

/*
 * Initialize interator that runs through all events and counters.
 */
684
static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
685
			    int num, int wmin, int wmax, int gpmax)
686 687 688 689 690 691
{
	int idx;

	memset(sched, 0, sizeof(*sched));
	sched->max_events	= num;
	sched->max_weight	= wmax;
692
	sched->max_gp		= gpmax;
693
	sched->constraints	= constraints;
694 695

	for (idx = 0; idx < num; idx++) {
696
		if (constraints[idx]->weight == wmin)
697 698 699 700 701 702 703 704
			break;
	}

	sched->state.event	= idx;		/* start with min weight */
	sched->state.weight	= wmin;
	sched->state.unassigned	= num;
}

705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727
static void perf_sched_save_state(struct perf_sched *sched)
{
	if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
		return;

	sched->saved[sched->saved_states] = sched->state;
	sched->saved_states++;
}

static bool perf_sched_restore_state(struct perf_sched *sched)
{
	if (!sched->saved_states)
		return false;

	sched->saved_states--;
	sched->state = sched->saved[sched->saved_states];

	/* continue with next counter: */
	clear_bit(sched->state.counter++, sched->state.used);

	return true;
}

728 729 730 731
/*
 * Select a counter for the current event to schedule. Return true on
 * success.
 */
732
static bool __perf_sched_find_counter(struct perf_sched *sched)
733 734 735 736 737 738 739 740 741 742
{
	struct event_constraint *c;
	int idx;

	if (!sched->state.unassigned)
		return false;

	if (sched->state.event >= sched->max_events)
		return false;

743
	c = sched->constraints[sched->state.event];
744
	/* Prefer fixed purpose counters */
745 746
	if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
		idx = INTEL_PMC_IDX_FIXED;
747
		for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
748 749 750 751
			if (!__test_and_set_bit(idx, sched->state.used))
				goto done;
		}
	}
752

753 754
	/* Grab the first unused counter starting with idx */
	idx = sched->state.counter;
755
	for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
756 757 758 759
		if (!__test_and_set_bit(idx, sched->state.used)) {
			if (sched->state.nr_gp++ >= sched->max_gp)
				return false;

760
			goto done;
761
		}
762 763
	}

764 765 766 767
	return false;

done:
	sched->state.counter = idx;
768

769 770 771 772 773 774 775 776 777 778 779 780 781
	if (c->overlap)
		perf_sched_save_state(sched);

	return true;
}

static bool perf_sched_find_counter(struct perf_sched *sched)
{
	while (!__perf_sched_find_counter(sched)) {
		if (!perf_sched_restore_state(sched))
			return false;
	}

782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805
	return true;
}

/*
 * Go through all unassigned events and find the next one to schedule.
 * Take events with the least weight first. Return true on success.
 */
static bool perf_sched_next_event(struct perf_sched *sched)
{
	struct event_constraint *c;

	if (!sched->state.unassigned || !--sched->state.unassigned)
		return false;

	do {
		/* next event */
		sched->state.event++;
		if (sched->state.event >= sched->max_events) {
			/* next weight */
			sched->state.event = 0;
			sched->state.weight++;
			if (sched->state.weight > sched->max_weight)
				return false;
		}
806
		c = sched->constraints[sched->state.event];
807 808 809 810 811 812 813 814 815 816
	} while (c->weight != sched->state.weight);

	sched->state.counter = 0;	/* start with first counter */

	return true;
}

/*
 * Assign a counter for each event.
 */
817
int perf_assign_events(struct event_constraint **constraints, int n,
818
			int wmin, int wmax, int gpmax, int *assign)
819 820 821
{
	struct perf_sched sched;

822
	perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
823 824 825 826 827 828 829 830 831 832

	do {
		if (!perf_sched_find_counter(&sched))
			break;	/* failed */
		if (assign)
			assign[sched.state.event] = sched.state.counter;
	} while (perf_sched_next_event(&sched));

	return sched.state.unassigned;
}
833
EXPORT_SYMBOL_GPL(perf_assign_events);
834

835
int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
836
{
837
	struct event_constraint *c;
838
	unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
839
	struct perf_event *e;
840
	int i, wmin, wmax, unsched = 0;
841 842 843 844
	struct hw_perf_event *hwc;

	bitmap_zero(used_mask, X86_PMC_IDX_MAX);

845 846 847
	if (x86_pmu.start_scheduling)
		x86_pmu.start_scheduling(cpuc);

848
	for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
849
		cpuc->event_constraint[i] = NULL;
850
		c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
851
		cpuc->event_constraint[i] = c;
852

853 854
		wmin = min(wmin, c->weight);
		wmax = max(wmax, c->weight);
855 856
	}

857 858 859
	/*
	 * fastpath, try to reuse previous register
	 */
860
	for (i = 0; i < n; i++) {
861
		hwc = &cpuc->event_list[i]->hw;
862
		c = cpuc->event_constraint[i];
863 864 865 866 867 868

		/* never assigned */
		if (hwc->idx == -1)
			break;

		/* constraint still honored */
869
		if (!test_bit(hwc->idx, c->idxmsk))
870 871 872 873 874 875
			break;

		/* not already used */
		if (test_bit(hwc->idx, used_mask))
			break;

P
Peter Zijlstra 已提交
876
		__set_bit(hwc->idx, used_mask);
877 878 879 880
		if (assign)
			assign[i] = hwc->idx;
	}

881
	/* slow path */
882
	if (i != n) {
883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898
		int gpmax = x86_pmu.num_counters;

		/*
		 * Do not allow scheduling of more than half the available
		 * generic counters.
		 *
		 * This helps avoid counter starvation of sibling thread by
		 * ensuring at most half the counters cannot be in exclusive
		 * mode. There is no designated counters for the limits. Any
		 * N/2 counters can be used. This helps with events with
		 * specific counter constraints.
		 */
		if (is_ht_workaround_enabled() && !cpuc->is_fake &&
		    READ_ONCE(cpuc->excl_cntrs->exclusive_present))
			gpmax /= 2;

899
		unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
900
					     wmax, gpmax, assign);
901
	}
902

903
	/*
904 905 906 907 908 909 910 911
	 * In case of success (unsched = 0), mark events as committed,
	 * so we do not put_constraint() in case new events are added
	 * and fail to be scheduled
	 *
	 * We invoke the lower level commit callback to lock the resource
	 *
	 * We do not need to do all of this in case we are called to
	 * validate an event group (assign == NULL)
912
	 */
913
	if (!unsched && assign) {
914 915 916
		for (i = 0; i < n; i++) {
			e = cpuc->event_list[i];
			e->hw.flags |= PERF_X86_EVENT_COMMITTED;
917
			if (x86_pmu.commit_scheduling)
918
				x86_pmu.commit_scheduling(cpuc, i, assign[i]);
919
		}
920
	} else {
921
		for (i = 0; i < n; i++) {
922 923 924 925 926 927 928 929
			e = cpuc->event_list[i];
			/*
			 * do not put_constraint() on comitted events,
			 * because they are good to go
			 */
			if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
				continue;

930 931 932
			/*
			 * release events that failed scheduling
			 */
933
			if (x86_pmu.put_event_constraints)
934
				x86_pmu.put_event_constraints(cpuc, e);
935 936
		}
	}
937 938 939 940

	if (x86_pmu.stop_scheduling)
		x86_pmu.stop_scheduling(cpuc);

941
	return unsched ? -EINVAL : 0;
942 943 944 945 946 947 948 949 950 951 952
}

/*
 * dogrp: true if must collect siblings events (group)
 * returns total number of events and error code
 */
static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
{
	struct perf_event *event;
	int n, max_count;

953
	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
954 955 956 957 958 959

	/* current number of events already accepted */
	n = cpuc->n_events;

	if (is_x86_event(leader)) {
		if (n >= max_count)
960
			return -EINVAL;
961 962 963 964 965 966 967 968
		cpuc->event_list[n] = leader;
		n++;
	}
	if (!dogrp)
		return n;

	list_for_each_entry(event, &leader->sibling_list, group_entry) {
		if (!is_x86_event(event) ||
969
		    event->state <= PERF_EVENT_STATE_OFF)
970 971 972
			continue;

		if (n >= max_count)
973
			return -EINVAL;
974 975 976 977 978 979 980 981

		cpuc->event_list[n] = event;
		n++;
	}
	return n;
}

static inline void x86_assign_hw_event(struct perf_event *event,
982
				struct cpu_hw_events *cpuc, int i)
983
{
984 985 986 987 988
	struct hw_perf_event *hwc = &event->hw;

	hwc->idx = cpuc->assign[i];
	hwc->last_cpu = smp_processor_id();
	hwc->last_tag = ++cpuc->tags[i];
989

990
	if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
991 992
		hwc->config_base = 0;
		hwc->event_base	= 0;
993
	} else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
994
		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
995 996
		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
		hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
997
	} else {
998 999
		hwc->config_base = x86_pmu_config_addr(hwc->idx);
		hwc->event_base  = x86_pmu_event_addr(hwc->idx);
1000
		hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1001 1002 1003
	}
}

1004 1005 1006 1007 1008 1009 1010 1011 1012
static inline int match_prev_assignment(struct hw_perf_event *hwc,
					struct cpu_hw_events *cpuc,
					int i)
{
	return hwc->idx == cpuc->assign[i] &&
		hwc->last_cpu == smp_processor_id() &&
		hwc->last_tag == cpuc->tags[i];
}

P
Peter Zijlstra 已提交
1013
static void x86_pmu_start(struct perf_event *event, int flags);
1014

P
Peter Zijlstra 已提交
1015
static void x86_pmu_enable(struct pmu *pmu)
1016
{
1017
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1018 1019
	struct perf_event *event;
	struct hw_perf_event *hwc;
1020
	int i, added = cpuc->n_added;
1021

1022
	if (!x86_pmu_initialized())
1023
		return;
1024 1025 1026 1027

	if (cpuc->enabled)
		return;

1028
	if (cpuc->n_added) {
1029
		int n_running = cpuc->n_events - cpuc->n_added;
1030 1031 1032 1033 1034 1035
		/*
		 * apply assignment obtained either from
		 * hw_perf_group_sched_in() or x86_pmu_enable()
		 *
		 * step1: save events moving to new counters
		 */
1036
		for (i = 0; i < n_running; i++) {
1037 1038 1039
			event = cpuc->event_list[i];
			hwc = &event->hw;

1040 1041 1042 1043 1044 1045 1046 1047
			/*
			 * we can avoid reprogramming counter if:
			 * - assigned same counter as last time
			 * - running on same CPU as last time
			 * - no other event has used the counter since
			 */
			if (hwc->idx == -1 ||
			    match_prev_assignment(hwc, cpuc, i))
1048 1049
				continue;

P
Peter Zijlstra 已提交
1050 1051 1052 1053 1054 1055 1056 1057
			/*
			 * Ensure we don't accidentally enable a stopped
			 * counter simply because we rescheduled.
			 */
			if (hwc->state & PERF_HES_STOPPED)
				hwc->state |= PERF_HES_ARCH;

			x86_pmu_stop(event, PERF_EF_UPDATE);
1058 1059
		}

1060 1061 1062
		/*
		 * step2: reprogram moved events into new counters
		 */
1063 1064 1065 1066
		for (i = 0; i < cpuc->n_events; i++) {
			event = cpuc->event_list[i];
			hwc = &event->hw;

1067
			if (!match_prev_assignment(hwc, cpuc, i))
1068
				x86_assign_hw_event(event, cpuc, i);
1069 1070
			else if (i < n_running)
				continue;
1071

P
Peter Zijlstra 已提交
1072 1073 1074 1075
			if (hwc->state & PERF_HES_ARCH)
				continue;

			x86_pmu_start(event, PERF_EF_RELOAD);
1076 1077 1078 1079
		}
		cpuc->n_added = 0;
		perf_events_lapic_init();
	}
1080 1081 1082 1083

	cpuc->enabled = 1;
	barrier();

1084
	x86_pmu.enable_all(added);
1085 1086
}

1087
static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
I
Ingo Molnar 已提交
1088

1089 1090
/*
 * Set the next IRQ period, based on the hwc->period_left value.
1091
 * To be called with the event disabled in hw:
1092
 */
1093
int x86_perf_event_set_period(struct perf_event *event)
I
Ingo Molnar 已提交
1094
{
1095
	struct hw_perf_event *hwc = &event->hw;
1096
	s64 left = local64_read(&hwc->period_left);
1097
	s64 period = hwc->sample_period;
1098
	int ret = 0, idx = hwc->idx;
1099

1100
	if (idx == INTEL_PMC_IDX_FIXED_BTS)
1101 1102
		return 0;

1103
	/*
1104
	 * If we are way outside a reasonable range then just skip forward:
1105 1106 1107
	 */
	if (unlikely(left <= -period)) {
		left = period;
1108
		local64_set(&hwc->period_left, left);
1109
		hwc->last_period = period;
1110
		ret = 1;
1111 1112 1113 1114
	}

	if (unlikely(left <= 0)) {
		left += period;
1115
		local64_set(&hwc->period_left, left);
1116
		hwc->last_period = period;
1117
		ret = 1;
1118
	}
1119
	/*
1120
	 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1121 1122 1123
	 */
	if (unlikely(left < 2))
		left = 2;
I
Ingo Molnar 已提交
1124

1125 1126 1127
	if (left > x86_pmu.max_period)
		left = x86_pmu.max_period;

1128 1129 1130
	if (x86_pmu.limit_period)
		left = x86_pmu.limit_period(event, left);

1131
	per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1132

1133 1134 1135 1136 1137 1138 1139
	if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
	    local64_read(&hwc->prev_count) != (u64)-left) {
		/*
		 * The hw event starts counting from this event offset,
		 * mark it to be able to extra future deltas:
		 */
		local64_set(&hwc->prev_count, (u64)-left);
1140

1141 1142
		wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
	}
1143 1144 1145 1146 1147 1148 1149

	/*
	 * Due to erratum on certan cpu we need
	 * a second write to be sure the register
	 * is updated properly
	 */
	if (x86_pmu.perfctr_second_write) {
1150
		wrmsrl(hwc->event_base,
1151
			(u64)(-left) & x86_pmu.cntval_mask);
1152
	}
1153

1154
	perf_event_update_userpage(event);
1155

1156
	return ret;
1157 1158
}

1159
void x86_pmu_enable_event(struct perf_event *event)
1160
{
T
Tejun Heo 已提交
1161
	if (__this_cpu_read(cpu_hw_events.enabled))
1162 1163
		__x86_pmu_enable_event(&event->hw,
				       ARCH_PERFMON_EVENTSEL_ENABLE);
I
Ingo Molnar 已提交
1164 1165
}

1166
/*
P
Peter Zijlstra 已提交
1167
 * Add a single event to the PMU.
1168 1169 1170
 *
 * The event is added to the group of enabled events
 * but only if it can be scehduled with existing events.
1171
 */
P
Peter Zijlstra 已提交
1172
static int x86_pmu_add(struct perf_event *event, int flags)
1173
{
1174
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1175 1176 1177
	struct hw_perf_event *hwc;
	int assign[X86_PMC_IDX_MAX];
	int n, n0, ret;
1178

1179
	hwc = &event->hw;
1180

1181
	n0 = cpuc->n_events;
1182 1183 1184
	ret = n = collect_events(cpuc, event, false);
	if (ret < 0)
		goto out;
1185

P
Peter Zijlstra 已提交
1186 1187 1188 1189
	hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
	if (!(flags & PERF_EF_START))
		hwc->state |= PERF_HES_ARCH;

1190 1191
	/*
	 * If group events scheduling transaction was started,
L
Lucas De Marchi 已提交
1192
	 * skip the schedulability test here, it will be performed
1193
	 * at commit time (->commit_txn) as a whole.
1194
	 */
1195
	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1196
		goto done_collect;
1197

1198
	ret = x86_pmu.schedule_events(cpuc, n, assign);
1199
	if (ret)
1200
		goto out;
1201 1202 1203 1204 1205
	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));
1206

1207
done_collect:
1208 1209 1210 1211
	/*
	 * Commit the collect_events() state. See x86_pmu_del() and
	 * x86_pmu_*_txn().
	 */
1212
	cpuc->n_events = n;
1213
	cpuc->n_added += n - n0;
1214
	cpuc->n_txn += n - n0;
1215

1216 1217 1218
	ret = 0;
out:
	return ret;
I
Ingo Molnar 已提交
1219 1220
}

P
Peter Zijlstra 已提交
1221
static void x86_pmu_start(struct perf_event *event, int flags)
1222
{
1223
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
P
Peter Zijlstra 已提交
1224 1225
	int idx = event->hw.idx;

P
Peter Zijlstra 已提交
1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237
	if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

	if (WARN_ON_ONCE(idx == -1))
		return;

	if (flags & PERF_EF_RELOAD) {
		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
		x86_perf_event_set_period(event);
	}

	event->hw.state = 0;
1238

P
Peter Zijlstra 已提交
1239 1240
	cpuc->events[idx] = event;
	__set_bit(idx, cpuc->active_mask);
1241
	__set_bit(idx, cpuc->running);
1242
	x86_pmu.enable(event);
P
Peter Zijlstra 已提交
1243
	perf_event_update_userpage(event);
1244 1245
}

1246
void perf_event_print_debug(void)
I
Ingo Molnar 已提交
1247
{
1248
	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
A
Andi Kleen 已提交
1249
	u64 pebs, debugctl;
1250
	struct cpu_hw_events *cpuc;
1251
	unsigned long flags;
1252 1253
	int cpu, idx;

1254
	if (!x86_pmu.num_counters)
1255
		return;
I
Ingo Molnar 已提交
1256

1257
	local_irq_save(flags);
I
Ingo Molnar 已提交
1258 1259

	cpu = smp_processor_id();
1260
	cpuc = &per_cpu(cpu_hw_events, cpu);
I
Ingo Molnar 已提交
1261

1262
	if (x86_pmu.version >= 2) {
1263 1264 1265 1266 1267 1268 1269 1270 1271 1272
		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
		rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);

		pr_info("\n");
		pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
		pr_info("CPU#%d: status:     %016llx\n", cpu, status);
		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1273 1274 1275 1276
		if (x86_pmu.pebs_constraints) {
			rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
			pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
		}
A
Andi Kleen 已提交
1277 1278 1279 1280
		if (x86_pmu.lbr_nr) {
			rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
			pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);
		}
1281
	}
1282
	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
I
Ingo Molnar 已提交
1283

1284
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1285 1286
		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
I
Ingo Molnar 已提交
1287

1288
		prev_left = per_cpu(pmc_prev_left[idx], cpu);
I
Ingo Molnar 已提交
1289

1290
		pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
I
Ingo Molnar 已提交
1291
			cpu, idx, pmc_ctrl);
1292
		pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
I
Ingo Molnar 已提交
1293
			cpu, idx, pmc_count);
1294
		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1295
			cpu, idx, prev_left);
I
Ingo Molnar 已提交
1296
	}
1297
	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1298 1299
		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);

1300
		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1301 1302
			cpu, idx, pmc_count);
	}
1303
	local_irq_restore(flags);
I
Ingo Molnar 已提交
1304 1305
}

1306
void x86_pmu_stop(struct perf_event *event, int flags)
I
Ingo Molnar 已提交
1307
{
1308
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1309
	struct hw_perf_event *hwc = &event->hw;
I
Ingo Molnar 已提交
1310

P
Peter Zijlstra 已提交
1311 1312 1313 1314 1315 1316
	if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
		x86_pmu.disable(event);
		cpuc->events[hwc->idx] = NULL;
		WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
		hwc->state |= PERF_HES_STOPPED;
	}
1317

P
Peter Zijlstra 已提交
1318 1319 1320 1321 1322 1323 1324 1325
	if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
		/*
		 * Drain the remaining delta count out of a event
		 * that we are disabling:
		 */
		x86_perf_event_update(event);
		hwc->state |= PERF_HES_UPTODATE;
	}
1326 1327
}

P
Peter Zijlstra 已提交
1328
static void x86_pmu_del(struct perf_event *event, int flags)
1329
{
1330
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1331 1332
	int i;

1333 1334 1335 1336 1337
	/*
	 * event is descheduled
	 */
	event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;

1338 1339 1340 1341
	/*
	 * If we're called during a txn, we don't need to do anything.
	 * The events never got scheduled and ->cancel_txn will truncate
	 * the event_list.
1342 1343 1344
	 *
	 * XXX assumes any ->del() called during a TXN will only be on
	 * an event added during that same TXN.
1345
	 */
1346
	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1347 1348
		return;

1349 1350 1351
	/*
	 * Not a TXN, therefore cleanup properly.
	 */
P
Peter Zijlstra 已提交
1352
	x86_pmu_stop(event, PERF_EF_UPDATE);
1353

1354
	for (i = 0; i < cpuc->n_events; i++) {
1355 1356 1357
		if (event == cpuc->event_list[i])
			break;
	}
1358

1359 1360
	if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
		return;
P
Peter Zijlstra 已提交
1361

1362 1363 1364
	/* If we have a newly added event; make sure to decrease n_added. */
	if (i >= cpuc->n_events - cpuc->n_added)
		--cpuc->n_added;
1365

1366 1367 1368 1369
	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(cpuc, event);

	/* Delete the array entry. */
1370
	while (++i < cpuc->n_events) {
1371
		cpuc->event_list[i-1] = cpuc->event_list[i];
1372 1373
		cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
	}
1374
	--cpuc->n_events;
1375

1376
	perf_event_update_userpage(event);
I
Ingo Molnar 已提交
1377 1378
}

1379
int x86_pmu_handle_irq(struct pt_regs *regs)
1380
{
1381
	struct perf_sample_data data;
1382 1383
	struct cpu_hw_events *cpuc;
	struct perf_event *event;
V
Vince Weaver 已提交
1384
	int idx, handled = 0;
1385 1386
	u64 val;

1387
	cpuc = this_cpu_ptr(&cpu_hw_events);
1388

1389 1390 1391 1392 1393 1394 1395 1396 1397 1398
	/*
	 * Some chipsets need to unmask the LVTPC in a particular spot
	 * inside the nmi handler.  As a result, the unmasking was pushed
	 * into all the nmi handlers.
	 *
	 * This generic handler doesn't seem to have any issues where the
	 * unmasking occurs so it was left at the top.
	 */
	apic_write(APIC_LVTPC, APIC_DM_NMI);

1399
	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1400 1401 1402 1403 1404 1405 1406 1407
		if (!test_bit(idx, cpuc->active_mask)) {
			/*
			 * Though we deactivated the counter some cpus
			 * might still deliver spurious interrupts still
			 * in flight. Catch them:
			 */
			if (__test_and_clear_bit(idx, cpuc->running))
				handled++;
1408
			continue;
1409
		}
1410

1411
		event = cpuc->events[idx];
1412

1413
		val = x86_perf_event_update(event);
1414
		if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1415
			continue;
1416

1417
		/*
1418
		 * event overflow
1419
		 */
1420
		handled++;
1421
		perf_sample_data_init(&data, 0, event->hw.last_period);
1422

1423
		if (!x86_perf_event_set_period(event))
1424 1425
			continue;

1426
		if (perf_event_overflow(event, &data, regs))
P
Peter Zijlstra 已提交
1427
			x86_pmu_stop(event, 0);
1428
	}
1429

1430 1431 1432
	if (handled)
		inc_irq_stat(apic_perf_irqs);

1433 1434
	return handled;
}
1435

1436
void perf_events_lapic_init(void)
I
Ingo Molnar 已提交
1437
{
1438
	if (!x86_pmu.apic || !x86_pmu_initialized())
I
Ingo Molnar 已提交
1439
		return;
1440

I
Ingo Molnar 已提交
1441
	/*
1442
	 * Always use NMI for PMU
I
Ingo Molnar 已提交
1443
	 */
1444
	apic_write(APIC_LVTPC, APIC_DM_NMI);
I
Ingo Molnar 已提交
1445 1446
}

1447
static int
1448
perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
I
Ingo Molnar 已提交
1449
{
1450 1451
	u64 start_clock;
	u64 finish_clock;
P
Peter Zijlstra 已提交
1452
	int ret;
1453

1454 1455 1456 1457
	/*
	 * All PMUs/events that share this PMI handler should make sure to
	 * increment active_events for their events.
	 */
1458
	if (!atomic_read(&active_events))
1459
		return NMI_DONE;
1460

P
Peter Zijlstra 已提交
1461
	start_clock = sched_clock();
1462
	ret = x86_pmu.handle_irq(regs);
P
Peter Zijlstra 已提交
1463
	finish_clock = sched_clock();
1464 1465 1466 1467

	perf_sample_event_took(finish_clock - start_clock);

	return ret;
I
Ingo Molnar 已提交
1468
}
1469
NOKPROBE_SYMBOL(perf_event_nmi_handler);
I
Ingo Molnar 已提交
1470

1471 1472
struct event_constraint emptyconstraint;
struct event_constraint unconstrained;
1473

1474
static int
1475 1476 1477
x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
	unsigned int cpu = (long)hcpu;
1478
	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1479
	int i, ret = NOTIFY_OK;
1480 1481 1482

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_UP_PREPARE:
1483 1484
		for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
			cpuc->kfree_on_online[i] = NULL;
1485
		if (x86_pmu.cpu_prepare)
1486
			ret = x86_pmu.cpu_prepare(cpu);
1487 1488 1489 1490 1491 1492 1493
		break;

	case CPU_STARTING:
		if (x86_pmu.cpu_starting)
			x86_pmu.cpu_starting(cpu);
		break;

1494
	case CPU_ONLINE:
1495 1496 1497 1498
		for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
			kfree(cpuc->kfree_on_online[i]);
			cpuc->kfree_on_online[i] = NULL;
		}
1499 1500
		break;

1501 1502 1503 1504 1505
	case CPU_DYING:
		if (x86_pmu.cpu_dying)
			x86_pmu.cpu_dying(cpu);
		break;

1506
	case CPU_UP_CANCELED:
1507 1508 1509 1510 1511 1512 1513 1514 1515
	case CPU_DEAD:
		if (x86_pmu.cpu_dead)
			x86_pmu.cpu_dead(cpu);
		break;

	default:
		break;
	}

1516
	return ret;
1517 1518
}

1519 1520 1521 1522 1523 1524 1525 1526
static void __init pmu_check_apic(void)
{
	if (cpu_has_apic)
		return;

	x86_pmu.apic = 0;
	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
	pr_info("no hardware sampling interrupt available.\n");
1527 1528 1529 1530 1531 1532 1533 1534 1535

	/*
	 * If we have a PMU initialized but no APIC
	 * interrupts, we cannot sample hardware
	 * events (user-space has to fall back and
	 * sample via a hrtimer based software event):
	 */
	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;

1536 1537
}

1538 1539 1540 1541 1542
static struct attribute_group x86_pmu_format_group = {
	.name = "format",
	.attrs = NULL,
};

1543 1544 1545 1546 1547 1548
/*
 * Remove all undefined events (x86_pmu.event_map(id) == 0)
 * out of events_attr attributes.
 */
static void __init filter_events(struct attribute **attrs)
{
1549 1550
	struct device_attribute *d;
	struct perf_pmu_events_attr *pmu_attr;
1551
	int offset = 0;
1552 1553 1554
	int i, j;

	for (i = 0; attrs[i]; i++) {
1555 1556 1557 1558 1559
		d = (struct device_attribute *)attrs[i];
		pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
		/* str trumps id */
		if (pmu_attr->event_str)
			continue;
1560
		if (x86_pmu.event_map(i + offset))
1561 1562 1563 1564 1565 1566 1567
			continue;

		for (j = i; attrs[j]; j++)
			attrs[j] = attrs[j + 1];

		/* Check the shifted attr. */
		i--;
1568 1569 1570 1571 1572 1573 1574 1575

		/*
		 * event_map() is index based, the attrs array is organized
		 * by increasing event index. If we shift the events, then
		 * we need to compensate for the event_map(), otherwise
		 * we are looking up the wrong event in the map
		 */
		offset++;
1576 1577 1578
	}
}

1579
/* Merge two pointer arrays */
1580
__init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604
{
	struct attribute **new;
	int j, i;

	for (j = 0; a[j]; j++)
		;
	for (i = 0; b[i]; i++)
		j++;
	j++;

	new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
	if (!new)
		return NULL;

	j = 0;
	for (i = 0; a[i]; i++)
		new[j++] = a[i];
	for (i = 0; b[i]; i++)
		new[j++] = b[i];
	new[j] = NULL;

	return new;
}

1605
ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1606 1607 1608 1609 1610
{
	struct perf_pmu_events_attr *pmu_attr = \
		container_of(attr, struct perf_pmu_events_attr, attr);
	u64 config = x86_pmu.event_map(pmu_attr->id);

1611 1612 1613
	/* string trumps id */
	if (pmu_attr->event_str)
		return sprintf(page, "%s", pmu_attr->event_str);
1614

1615 1616
	return x86_pmu.events_sysfs_show(page, config);
}
1617
EXPORT_SYMBOL_GPL(events_sysfs_show);
1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631

EVENT_ATTR(cpu-cycles,			CPU_CYCLES		);
EVENT_ATTR(instructions,		INSTRUCTIONS		);
EVENT_ATTR(cache-references,		CACHE_REFERENCES	);
EVENT_ATTR(cache-misses, 		CACHE_MISSES		);
EVENT_ATTR(branch-instructions,		BRANCH_INSTRUCTIONS	);
EVENT_ATTR(branch-misses,		BRANCH_MISSES		);
EVENT_ATTR(bus-cycles,			BUS_CYCLES		);
EVENT_ATTR(stalled-cycles-frontend,	STALLED_CYCLES_FRONTEND	);
EVENT_ATTR(stalled-cycles-backend,	STALLED_CYCLES_BACKEND	);
EVENT_ATTR(ref-cycles,			REF_CPU_CYCLES		);

static struct attribute *empty_attrs;

P
Peter Huewe 已提交
1632
static struct attribute *events_attr[] = {
1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650
	EVENT_PTR(CPU_CYCLES),
	EVENT_PTR(INSTRUCTIONS),
	EVENT_PTR(CACHE_REFERENCES),
	EVENT_PTR(CACHE_MISSES),
	EVENT_PTR(BRANCH_INSTRUCTIONS),
	EVENT_PTR(BRANCH_MISSES),
	EVENT_PTR(BUS_CYCLES),
	EVENT_PTR(STALLED_CYCLES_FRONTEND),
	EVENT_PTR(STALLED_CYCLES_BACKEND),
	EVENT_PTR(REF_CPU_CYCLES),
	NULL,
};

static struct attribute_group x86_pmu_events_group = {
	.name = "events",
	.attrs = events_attr,
};

1651
ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689
{
	u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
	u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
	bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
	bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
	bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
	bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
	ssize_t ret;

	/*
	* We have whole page size to spend and just little data
	* to write, so we can safely use sprintf.
	*/
	ret = sprintf(page, "event=0x%02llx", event);

	if (umask)
		ret += sprintf(page + ret, ",umask=0x%02llx", umask);

	if (edge)
		ret += sprintf(page + ret, ",edge");

	if (pc)
		ret += sprintf(page + ret, ",pc");

	if (any)
		ret += sprintf(page + ret, ",any");

	if (inv)
		ret += sprintf(page + ret, ",inv");

	if (cmask)
		ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);

	ret += sprintf(page + ret, "\n");

	return ret;
}

1690
static int __init init_hw_perf_events(void)
1691
{
1692
	struct x86_pmu_quirk *quirk;
1693 1694
	int err;

1695
	pr_info("Performance Events: ");
1696

1697 1698
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_INTEL:
1699
		err = intel_pmu_init();
1700
		break;
1701
	case X86_VENDOR_AMD:
1702
		err = amd_pmu_init();
1703
		break;
1704
	default:
1705
		err = -ENOTSUPP;
1706
	}
1707
	if (err != 0) {
1708
		pr_cont("no PMU driver, software events only.\n");
1709
		return 0;
1710
	}
1711

1712 1713
	pmu_check_apic();

1714
	/* sanity check that the hardware exists or is emulated */
1715
	if (!check_hw_exists())
1716
		return 0;
1717

1718
	pr_cont("%s PMU driver.\n", x86_pmu.name);
1719

1720 1721
	x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */

1722 1723
	for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
		quirk->func();
1724

1725 1726
	if (!x86_pmu.intel_ctrl)
		x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
I
Ingo Molnar 已提交
1727

1728
	perf_events_lapic_init();
1729
	register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1730

1731
	unconstrained = (struct event_constraint)
1732
		__EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1733
				   0, x86_pmu.num_counters, 0, 0);
1734

1735
	x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1736

1737 1738 1739
	if (x86_pmu.event_attrs)
		x86_pmu_events_group.attrs = x86_pmu.event_attrs;

1740 1741
	if (!x86_pmu.events_sysfs_show)
		x86_pmu_events_group.attrs = &empty_attrs;
1742 1743
	else
		filter_events(x86_pmu_events_group.attrs);
1744

1745 1746 1747 1748 1749 1750 1751 1752
	if (x86_pmu.cpu_events) {
		struct attribute **tmp;

		tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
		if (!WARN_ON(!tmp))
			x86_pmu_events_group.attrs = tmp;
	}

I
Ingo Molnar 已提交
1753
	pr_info("... version:                %d\n",     x86_pmu.version);
1754 1755 1756
	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
	pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
I
Ingo Molnar 已提交
1757
	pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1758
	pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1759
	pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1760

P
Peter Zijlstra 已提交
1761
	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1762
	perf_cpu_notifier(x86_pmu_notifier);
1763 1764

	return 0;
I
Ingo Molnar 已提交
1765
}
1766
early_initcall(init_hw_perf_events);
I
Ingo Molnar 已提交
1767

1768
static inline void x86_pmu_read(struct perf_event *event)
1769
{
1770
	x86_perf_event_update(event);
1771 1772
}

1773 1774 1775 1776
/*
 * Start group events scheduling transaction
 * Set the flag to make pmu::enable() not perform the
 * schedulability test, it will be performed at commit time
1777 1778 1779 1780
 *
 * We only support PERF_PMU_TXN_ADD transactions. Save the
 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
 * transactions.
1781
 */
1782
static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1783
{
1784 1785 1786 1787 1788 1789 1790 1791
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	WARN_ON_ONCE(cpuc->txn_flags);		/* txn already in flight */

	cpuc->txn_flags = txn_flags;
	if (txn_flags & ~PERF_PMU_TXN_ADD)
		return;

P
Peter Zijlstra 已提交
1792
	perf_pmu_disable(pmu);
T
Tejun Heo 已提交
1793
	__this_cpu_write(cpu_hw_events.n_txn, 0);
1794 1795 1796 1797 1798 1799 1800
}

/*
 * Stop group events scheduling transaction
 * Clear the flag and pmu::enable() will perform the
 * schedulability test.
 */
P
Peter Zijlstra 已提交
1801
static void x86_pmu_cancel_txn(struct pmu *pmu)
1802
{
1803 1804 1805 1806 1807 1808 1809 1810 1811 1812
	unsigned int txn_flags;
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	WARN_ON_ONCE(!cpuc->txn_flags);	/* no txn in flight */

	txn_flags = cpuc->txn_flags;
	cpuc->txn_flags = 0;
	if (txn_flags & ~PERF_PMU_TXN_ADD)
		return;

1813
	/*
1814 1815
	 * Truncate collected array by the number of events added in this
	 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1816
	 */
T
Tejun Heo 已提交
1817 1818
	__this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
	__this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
P
Peter Zijlstra 已提交
1819
	perf_pmu_enable(pmu);
1820 1821 1822 1823 1824 1825
}

/*
 * Commit group events scheduling transaction
 * Perform the group schedulability test as a whole
 * Return 0 if success
1826 1827
 *
 * Does not cancel the transaction on failure; expects the caller to do this.
1828
 */
P
Peter Zijlstra 已提交
1829
static int x86_pmu_commit_txn(struct pmu *pmu)
1830
{
1831
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1832 1833 1834
	int assign[X86_PMC_IDX_MAX];
	int n, ret;

1835 1836 1837 1838 1839 1840 1841
	WARN_ON_ONCE(!cpuc->txn_flags);	/* no txn in flight */

	if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
		cpuc->txn_flags = 0;
		return 0;
	}

1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
	n = cpuc->n_events;

	if (!x86_pmu_initialized())
		return -EAGAIN;

	ret = x86_pmu.schedule_events(cpuc, n, assign);
	if (ret)
		return ret;

	/*
	 * copy new assignment, now we know it is possible
	 * will be used by hw_perf_enable()
	 */
	memcpy(cpuc->assign, assign, n*sizeof(int));

1857
	cpuc->txn_flags = 0;
P
Peter Zijlstra 已提交
1858
	perf_pmu_enable(pmu);
1859 1860
	return 0;
}
1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889
/*
 * a fake_cpuc is used to validate event groups. Due to
 * the extra reg logic, we need to also allocate a fake
 * per_core and per_cpu structure. Otherwise, group events
 * using extra reg may conflict without the kernel being
 * able to catch this when the last event gets added to
 * the group.
 */
static void free_fake_cpuc(struct cpu_hw_events *cpuc)
{
	kfree(cpuc->shared_regs);
	kfree(cpuc);
}

static struct cpu_hw_events *allocate_fake_cpuc(void)
{
	struct cpu_hw_events *cpuc;
	int cpu = raw_smp_processor_id();

	cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
	if (!cpuc)
		return ERR_PTR(-ENOMEM);

	/* only needed, if we have extra_regs */
	if (x86_pmu.extra_regs) {
		cpuc->shared_regs = allocate_shared_regs(cpu);
		if (!cpuc->shared_regs)
			goto error;
	}
1890
	cpuc->is_fake = 1;
1891 1892 1893 1894 1895
	return cpuc;
error:
	free_fake_cpuc(cpuc);
	return ERR_PTR(-ENOMEM);
}
1896

1897 1898 1899 1900 1901 1902 1903 1904 1905
/*
 * validate that we can schedule this event
 */
static int validate_event(struct perf_event *event)
{
	struct cpu_hw_events *fake_cpuc;
	struct event_constraint *c;
	int ret = 0;

1906 1907 1908
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1909

1910
	c = x86_pmu.get_event_constraints(fake_cpuc, -1, event);
1911 1912

	if (!c || !c->weight)
1913
		ret = -EINVAL;
1914 1915 1916 1917

	if (x86_pmu.put_event_constraints)
		x86_pmu.put_event_constraints(fake_cpuc, event);

1918
	free_fake_cpuc(fake_cpuc);
1919 1920 1921 1922

	return ret;
}

1923 1924 1925 1926
/*
 * validate a single event group
 *
 * validation include:
1927 1928 1929
 *	- check events are compatible which each other
 *	- events do not compete for the same counter
 *	- number of events <= number of counters
1930 1931 1932 1933
 *
 * validation ensures the group can be loaded onto the
 * PMU if it was the only group available.
 */
1934 1935
static int validate_group(struct perf_event *event)
{
1936
	struct perf_event *leader = event->group_leader;
1937
	struct cpu_hw_events *fake_cpuc;
1938
	int ret = -EINVAL, n;
1939

1940 1941 1942
	fake_cpuc = allocate_fake_cpuc();
	if (IS_ERR(fake_cpuc))
		return PTR_ERR(fake_cpuc);
1943 1944 1945 1946 1947 1948
	/*
	 * the event is not yet connected with its
	 * siblings therefore we must first collect
	 * existing siblings, then add the new event
	 * before we can simulate the scheduling
	 */
1949
	n = collect_events(fake_cpuc, leader, true);
1950
	if (n < 0)
1951
		goto out;
1952

1953 1954
	fake_cpuc->n_events = n;
	n = collect_events(fake_cpuc, event, false);
1955
	if (n < 0)
1956
		goto out;
1957

1958
	fake_cpuc->n_events = n;
1959

1960
	ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1961 1962

out:
1963
	free_fake_cpuc(fake_cpuc);
1964
	return ret;
1965 1966
}

1967
static int x86_pmu_event_init(struct perf_event *event)
I
Ingo Molnar 已提交
1968
{
P
Peter Zijlstra 已提交
1969
	struct pmu *tmp;
I
Ingo Molnar 已提交
1970 1971
	int err;

1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982
	switch (event->attr.type) {
	case PERF_TYPE_RAW:
	case PERF_TYPE_HARDWARE:
	case PERF_TYPE_HW_CACHE:
		break;

	default:
		return -ENOENT;
	}

	err = __x86_pmu_event_init(event);
1983
	if (!err) {
1984 1985 1986 1987 1988 1989 1990 1991
		/*
		 * we temporarily connect event to its pmu
		 * such that validate_group() can classify
		 * it as an x86 event using is_x86_event()
		 */
		tmp = event->pmu;
		event->pmu = &pmu;

1992 1993
		if (event->group_leader != event)
			err = validate_group(event);
1994 1995
		else
			err = validate_event(event);
1996 1997

		event->pmu = tmp;
1998
	}
1999
	if (err) {
2000 2001
		if (event->destroy)
			event->destroy(event);
2002
	}
I
Ingo Molnar 已提交
2003

2004 2005 2006
	if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
		event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;

2007
	return err;
I
Ingo Molnar 已提交
2008
}
2009

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036
static void refresh_pce(void *ignored)
{
	if (current->mm)
		load_mm_cr4(current->mm);
}

static void x86_pmu_event_mapped(struct perf_event *event)
{
	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
		return;

	if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
		on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
}

static void x86_pmu_event_unmapped(struct perf_event *event)
{
	if (!current->mm)
		return;

	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
		return;

	if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
		on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
}

2037 2038 2039 2040
static int x86_pmu_event_idx(struct perf_event *event)
{
	int idx = event->hw.idx;

2041
	if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2042 2043
		return 0;

2044 2045
	if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
		idx -= INTEL_PMC_IDX_FIXED;
2046 2047 2048 2049 2050 2051
		idx |= 1 << 30;
	}

	return idx + 1;
}

2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062
static ssize_t get_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      char *buf)
{
	return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
}

static ssize_t set_attr_rdpmc(struct device *cdev,
			      struct device_attribute *attr,
			      const char *buf, size_t count)
{
2063 2064 2065 2066 2067 2068
	unsigned long val;
	ssize_t ret;

	ret = kstrtoul(buf, 0, &val);
	if (ret)
		return ret;
2069

2070 2071 2072
	if (val > 2)
		return -EINVAL;

2073 2074
	if (x86_pmu.attr_rdpmc_broken)
		return -ENOTSUPP;
2075

2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090
	if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
		/*
		 * Changing into or out of always available, aka
		 * perf-event-bypassing mode.  This path is extremely slow,
		 * but only root can trigger it, so it's okay.
		 */
		if (val == 2)
			static_key_slow_inc(&rdpmc_always_available);
		else
			static_key_slow_dec(&rdpmc_always_available);
		on_each_cpu(refresh_pce, NULL, 1);
	}

	x86_pmu.attr_rdpmc = val;

2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106
	return count;
}

static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);

static struct attribute *x86_pmu_attrs[] = {
	&dev_attr_rdpmc.attr,
	NULL,
};

static struct attribute_group x86_pmu_attr_group = {
	.attrs = x86_pmu_attrs,
};

static const struct attribute_group *x86_pmu_attr_groups[] = {
	&x86_pmu_attr_group,
2107
	&x86_pmu_format_group,
2108
	&x86_pmu_events_group,
2109 2110 2111
	NULL,
};

2112
static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2113
{
2114 2115
	if (x86_pmu.sched_task)
		x86_pmu.sched_task(ctx, sched_in);
2116 2117
}

2118 2119 2120 2121 2122 2123 2124
void perf_check_microcode(void)
{
	if (x86_pmu.check_microcode)
		x86_pmu.check_microcode();
}
EXPORT_SYMBOL_GPL(perf_check_microcode);

2125
static struct pmu pmu = {
2126 2127
	.pmu_enable		= x86_pmu_enable,
	.pmu_disable		= x86_pmu_disable,
P
Peter Zijlstra 已提交
2128

2129
	.attr_groups		= x86_pmu_attr_groups,
2130

2131
	.event_init		= x86_pmu_event_init,
P
Peter Zijlstra 已提交
2132

2133 2134 2135
	.event_mapped		= x86_pmu_event_mapped,
	.event_unmapped		= x86_pmu_event_unmapped,

2136 2137 2138 2139 2140
	.add			= x86_pmu_add,
	.del			= x86_pmu_del,
	.start			= x86_pmu_start,
	.stop			= x86_pmu_stop,
	.read			= x86_pmu_read,
P
Peter Zijlstra 已提交
2141

2142 2143 2144
	.start_txn		= x86_pmu_start_txn,
	.cancel_txn		= x86_pmu_cancel_txn,
	.commit_txn		= x86_pmu_commit_txn,
2145

2146
	.event_idx		= x86_pmu_event_idx,
2147
	.sched_task		= x86_pmu_sched_task,
2148
	.task_ctx_size          = sizeof(struct x86_perf_task_context),
2149 2150
};

2151 2152
void arch_perf_update_userpage(struct perf_event *event,
			       struct perf_event_mmap_page *userpg, u64 now)
2153
{
2154 2155
	struct cyc2ns_data *data;

2156 2157
	userpg->cap_user_time = 0;
	userpg->cap_user_time_zero = 0;
2158 2159
	userpg->cap_user_rdpmc =
		!!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2160 2161
	userpg->pmc_width = x86_pmu.cntval_bits;

2162
	if (!sched_clock_stable())
2163 2164
		return;

2165 2166
	data = cyc2ns_read_begin();

2167 2168 2169 2170
	/*
	 * Internal timekeeping for enabled/running/stopped times
	 * is always in the local_clock domain.
	 */
2171
	userpg->cap_user_time = 1;
2172 2173 2174
	userpg->time_mult = data->cyc2ns_mul;
	userpg->time_shift = data->cyc2ns_shift;
	userpg->time_offset = data->cyc2ns_offset - now;
2175

2176 2177 2178 2179 2180 2181 2182 2183
	/*
	 * cap_user_time_zero doesn't make sense when we're using a different
	 * time base for the records.
	 */
	if (event->clock == &local_clock) {
		userpg->cap_user_time_zero = 1;
		userpg->time_zero = data->cyc2ns_offset;
	}
2184 2185

	cyc2ns_read_end(data);
2186 2187
}

2188 2189 2190 2191 2192 2193
/*
 * callchain support
 */

static int backtrace_stack(void *data, char *name)
{
2194
	return 0;
2195 2196
}

2197
static int backtrace_address(void *data, unsigned long addr, int reliable)
2198 2199 2200
{
	struct perf_callchain_entry *entry = data;

2201
	return perf_callchain_store(entry, addr);
2202 2203 2204 2205 2206
}

static const struct stacktrace_ops backtrace_ops = {
	.stack			= backtrace_stack,
	.address		= backtrace_address,
2207
	.walk_stack		= print_context_stack_bp,
2208 2209
};

2210 2211
void
perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2212
{
2213 2214
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
2215
		return;
2216 2217
	}

2218
	perf_callchain_store(entry, regs->ip);
2219

2220
	dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2221 2222
}

2223 2224 2225 2226 2227 2228
static inline int
valid_user_frame(const void __user *fp, unsigned long size)
{
	return (__range_not_ok(fp, size, TASK_SIZE) == 0);
}

2229 2230 2231 2232 2233 2234
static unsigned long get_segment_base(unsigned int segment)
{
	struct desc_struct *desc;
	int idx = segment >> 3;

	if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2235
#ifdef CONFIG_MODIFY_LDT_SYSCALL
2236 2237
		struct ldt_struct *ldt;

2238 2239 2240
		if (idx > LDT_ENTRIES)
			return 0;

2241 2242 2243
		/* IRQs are off, so this synchronizes with smp_store_release */
		ldt = lockless_dereference(current->active_mm->context.ldt);
		if (!ldt || idx > ldt->size)
2244 2245
			return 0;

2246
		desc = &ldt->entries[idx];
2247 2248 2249
#else
		return 0;
#endif
2250 2251 2252 2253
	} else {
		if (idx > GDT_ENTRIES)
			return 0;

2254
		desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2255 2256
	}

2257
	return get_desc_base(desc);
2258 2259
}

2260
#ifdef CONFIG_IA32_EMULATION
H
H. Peter Anvin 已提交
2261 2262 2263

#include <asm/compat.h>

2264 2265
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2266
{
2267
	/* 32-bit process in 64-bit kernel. */
2268
	unsigned long ss_base, cs_base;
2269 2270
	struct stack_frame_ia32 frame;
	const void __user *fp;
2271

2272 2273 2274
	if (!test_thread_flag(TIF_IA32))
		return 0;

2275 2276 2277 2278
	cs_base = get_segment_base(regs->cs);
	ss_base = get_segment_base(regs->ss);

	fp = compat_ptr(ss_base + regs->bp);
2279
	pagefault_disable();
2280 2281 2282 2283 2284
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
		unsigned long bytes;
		frame.next_frame     = 0;
		frame.return_address = 0;

2285 2286 2287 2288 2289 2290 2291
		if (!access_ok(VERIFY_READ, fp, 8))
			break;

		bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
		if (bytes != 0)
			break;
		bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2292
		if (bytes != 0)
2293
			break;
2294

2295 2296 2297
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2298 2299
		perf_callchain_store(entry, cs_base + frame.return_address);
		fp = compat_ptr(ss_base + frame.next_frame);
2300
	}
2301
	pagefault_enable();
2302
	return 1;
2303
}
2304 2305 2306 2307 2308 2309 2310
#else
static inline int
perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
{
    return 0;
}
#endif
2311

2312 2313
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2314 2315 2316 2317
{
	struct stack_frame frame;
	const void __user *fp;

2318 2319
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
		/* TODO: We don't support guest os callchain now */
2320
		return;
2321
	}
2322

2323 2324 2325 2326 2327 2328
	/*
	 * We don't know what to do with VM86 stacks.. ignore them for now.
	 */
	if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
		return;

2329
	fp = (void __user *)regs->bp;
2330

2331
	perf_callchain_store(entry, regs->ip);
2332

2333 2334 2335
	if (!current->mm)
		return;

2336 2337 2338
	if (perf_callchain_user32(regs, entry))
		return;

2339
	pagefault_disable();
2340
	while (entry->nr < PERF_MAX_STACK_DEPTH) {
2341
		unsigned long bytes;
2342
		frame.next_frame	     = NULL;
2343 2344
		frame.return_address = 0;

2345 2346 2347 2348 2349 2350 2351
		if (!access_ok(VERIFY_READ, fp, 16))
			break;

		bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8);
		if (bytes != 0)
			break;
		bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8);
2352
		if (bytes != 0)
2353 2354
			break;

2355 2356 2357
		if (!valid_user_frame(fp, sizeof(frame)))
			break;

2358
		perf_callchain_store(entry, frame.return_address);
2359
		fp = (void __user *)frame.next_frame;
2360
	}
2361
	pagefault_enable();
2362 2363
}

2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377
/*
 * Deal with code segment offsets for the various execution modes:
 *
 *   VM86 - the good olde 16 bit days, where the linear address is
 *          20 bits and we use regs->ip + 0x10 * regs->cs.
 *
 *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
 *          to figure out what the 32bit base address is.
 *
 *    X32 - has TIF_X32 set, but is running in x86_64
 *
 * X86_64 - CS,DS,SS,ES are all zero based.
 */
static unsigned long code_segment_base(struct pt_regs *regs)
2378
{
2379 2380 2381 2382 2383 2384
	/*
	 * For IA32 we look at the GDT/LDT segment base to convert the
	 * effective IP to a linear address.
	 */

#ifdef CONFIG_X86_32
2385 2386 2387 2388 2389 2390 2391
	/*
	 * If we are in VM86 mode, add the segment offset to convert to a
	 * linear address.
	 */
	if (regs->flags & X86_VM_MASK)
		return 0x10 * regs->cs;

2392
	if (user_mode(regs) && regs->cs != __USER_CS)
2393 2394
		return get_segment_base(regs->cs);
#else
2395 2396 2397
	if (user_mode(regs) && !user_64bit_mode(regs) &&
	    regs->cs != __USER32_CS)
		return get_segment_base(regs->cs);
2398 2399 2400
#endif
	return 0;
}
2401

2402 2403
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
2404
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2405
		return perf_guest_cbs->get_guest_ip();
2406

2407
	return regs->ip + code_segment_base(regs);
2408 2409 2410 2411 2412
}

unsigned long perf_misc_flags(struct pt_regs *regs)
{
	int misc = 0;
2413

2414
	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2415 2416 2417 2418 2419
		if (perf_guest_cbs->is_user_mode())
			misc |= PERF_RECORD_MISC_GUEST_USER;
		else
			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
	} else {
2420
		if (user_mode(regs))
2421 2422 2423 2424 2425
			misc |= PERF_RECORD_MISC_USER;
		else
			misc |= PERF_RECORD_MISC_KERNEL;
	}

2426
	if (regs->flags & PERF_EFLAGS_EXACT)
P
Peter Zijlstra 已提交
2427
		misc |= PERF_RECORD_MISC_EXACT_IP;
2428 2429 2430

	return misc;
}
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void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	cap->version		= x86_pmu.version;
	cap->num_counters_gp	= x86_pmu.num_counters;
	cap->num_counters_fixed	= x86_pmu.num_counters_fixed;
	cap->bit_width_gp	= x86_pmu.cntval_bits;
	cap->bit_width_fixed	= x86_pmu.cntval_bits;
	cap->events_mask	= (unsigned int)x86_pmu.events_maskl;
	cap->events_mask_len	= x86_pmu.events_mask_len;
}
EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);