intel_hdmi.c 27.8 KB
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/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
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#include "drm_edid.h"
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#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

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static void
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
	struct drm_device *dev = intel_hdmi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t enabled_bits;

	enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;

	WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
	     "HDMI port enabled, expecting disabled\n");
}

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struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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{
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	return container_of(encoder, struct intel_hdmi, base.base);
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}

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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_hdmi, base);
}

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void intel_dip_infoframe_csum(struct dip_infoframe *frame)
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{
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	uint8_t *data = (uint8_t *)frame;
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	uint8_t sum = 0;
	unsigned i;

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	frame->checksum = 0;
	frame->ecc = 0;
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	for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
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		sum += data[i];

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	frame->checksum = 0x100 - sum;
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}

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static u32 g4x_infoframe_index(struct dip_infoframe *frame)
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{
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	switch (frame->type) {
	case DIP_TYPE_AVI:
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		return VIDEO_DIP_SELECT_AVI;
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	case DIP_TYPE_SPD:
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		return VIDEO_DIP_SELECT_SPD;
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	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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		return 0;
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	}
}

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static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
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{
	switch (frame->type) {
	case DIP_TYPE_AVI:
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		return VIDEO_DIP_ENABLE_AVI;
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	case DIP_TYPE_SPD:
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		return VIDEO_DIP_ENABLE_SPD;
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	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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		return 0;
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	}
}

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static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
{
	switch (frame->type) {
	case DIP_TYPE_AVI:
		return VIDEO_DIP_ENABLE_AVI_HSW;
	case DIP_TYPE_SPD:
		return VIDEO_DIP_ENABLE_SPD_HSW;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		return 0;
	}
}

static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
{
	switch (frame->type) {
	case DIP_TYPE_AVI:
		return HSW_TVIDEO_DIP_AVI_DATA(pipe);
	case DIP_TYPE_SPD:
		return HSW_TVIDEO_DIP_SPD_DATA(pipe);
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		return 0;
	}
}

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static void g4x_write_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
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{
	uint32_t *data = (uint32_t *)frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	u32 val = I915_READ(VIDEO_DIP_CTL);
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	unsigned i, len = DIP_HEADER_SIZE + frame->len;
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(frame);
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	val &= ~g4x_infoframe_enable(frame);
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	I915_WRITE(VIDEO_DIP_CTL, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
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		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}
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	mmiowb();
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	val |= g4x_infoframe_enable(frame);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(VIDEO_DIP_CTL, val);
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	POSTING_READ(VIDEO_DIP_CTL);
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}

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static void ibx_write_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
	u32 val = I915_READ(reg);

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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(frame);
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	val &= ~g4x_infoframe_enable(frame);
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	I915_WRITE(reg, val);

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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	mmiowb();
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	val |= g4x_infoframe_enable(frame);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}

static void cpt_write_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
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{
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	uint32_t *data = (uint32_t *)frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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	unsigned i, len = DIP_HEADER_SIZE + frame->len;
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	u32 val = I915_READ(reg);
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(frame);
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	/* The DIP control register spec says that we need to update the AVI
	 * infoframe without clearing its enable bit */
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	if (frame->type != DIP_TYPE_AVI)
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		val &= ~g4x_infoframe_enable(frame);
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	I915_WRITE(reg, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
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		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	mmiowb();
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	val |= g4x_infoframe_enable(frame);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}
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static void vlv_write_infoframe(struct drm_encoder *encoder,
				     struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
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	u32 val = I915_READ(reg);
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(frame);
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	val &= ~g4x_infoframe_enable(frame);
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	I915_WRITE(reg, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	mmiowb();
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	val |= g4x_infoframe_enable(frame);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}

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static void hsw_write_infoframe(struct drm_encoder *encoder,
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				struct dip_infoframe *frame)
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{
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	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
	unsigned int i, len = DIP_HEADER_SIZE + frame->len;
	u32 val = I915_READ(ctl_reg);
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	if (data_reg == 0)
		return;

	val &= ~hsw_infoframe_enable(frame);
	I915_WRITE(ctl_reg, val);

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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(data_reg + i, *data);
		data++;
	}
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	mmiowb();
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	val |= hsw_infoframe_enable(frame);
	I915_WRITE(ctl_reg, val);
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	POSTING_READ(ctl_reg);
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}

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static void intel_set_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	intel_dip_infoframe_csum(frame);
	intel_hdmi->write_infoframe(encoder, frame);
}

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static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
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					 struct drm_display_mode *adjusted_mode)
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{
	struct dip_infoframe avi_if = {
		.type = DIP_TYPE_AVI,
		.ver = DIP_VERSION_AVI,
		.len = DIP_LEN_AVI,
	};

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	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
		avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;

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	intel_set_infoframe(encoder, &avi_if);
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}

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static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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{
	struct dip_infoframe spd_if;

	memset(&spd_if, 0, sizeof(spd_if));
	spd_if.type = DIP_TYPE_SPD;
	spd_if.ver = DIP_VERSION_SPD;
	spd_if.len = DIP_LEN_SPD;
	strcpy(spd_if.body.spd.vn, "Intel");
	strcpy(spd_if.body.spd.pd, "Integrated gfx");
	spd_if.body.spd.sdi = DIP_SPD_PC;

	intel_set_infoframe(encoder, &spd_if);
}

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static void g4x_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = VIDEO_DIP_CTL;
	u32 val = I915_READ(reg);
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	u32 port;
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	assert_hdmi_port_disabled(intel_hdmi);

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	/* If the registers were not initialized yet, they might be zeroes,
	 * which means we're selecting the AVI DIP and we're setting its
	 * frequency to once. This seems to really confuse the HW and make
	 * things stop working (the register spec says the AVI always needs to
	 * be sent every VSync). So here we avoid writing to the register more
	 * than we need and also explicitly select the AVI DIP and explicitly
	 * set its frequency to every VSync. Avoiding to write it twice seems to
	 * be enough to solve the problem, but being defensive shouldn't hurt us
	 * either. */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
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		POSTING_READ(reg);
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		return;
	}

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	switch (intel_hdmi->sdvox_reg) {
	case SDVOB:
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		port = VIDEO_DIP_PORT_B;
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		break;
	case SDVOC:
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		port = VIDEO_DIP_PORT_C;
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		break;
	default:
		return;
	}

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	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
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			POSTING_READ(reg);
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		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

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	val |= VIDEO_DIP_ENABLE;
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	val &= ~VIDEO_DIP_ENABLE_VENDOR;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}

static void ibx_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
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	u32 port;
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	assert_hdmi_port_disabled(intel_hdmi);

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	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
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		POSTING_READ(reg);
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		return;
	}

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	switch (intel_hdmi->sdvox_reg) {
	case HDMIB:
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		port = VIDEO_DIP_PORT_B;
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		break;
	case HDMIC:
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		port = VIDEO_DIP_PORT_C;
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		break;
	case HDMID:
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		port = VIDEO_DIP_PORT_D;
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		break;
	default:
		return;
	}

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	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
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			POSTING_READ(reg);
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		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

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	val |= VIDEO_DIP_ENABLE;
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	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}

static void cpt_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);

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	assert_hdmi_port_disabled(intel_hdmi);

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	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
		I915_WRITE(reg, val);
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		POSTING_READ(reg);
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		return;
	}

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	/* Set both together, unset both together: see the spec. */
	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
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	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}

static void vlv_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);

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	assert_hdmi_port_disabled(intel_hdmi);

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	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

	if (!intel_hdmi->has_hdmi_sink) {
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
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		POSTING_READ(reg);
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		return;
	}

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	val |= VIDEO_DIP_ENABLE;
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	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}

static void hsw_set_infoframes(struct drm_encoder *encoder,
			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
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	u32 val = I915_READ(reg);
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	assert_hdmi_port_disabled(intel_hdmi);

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	if (!intel_hdmi->has_hdmi_sink) {
		I915_WRITE(reg, 0);
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		POSTING_READ(reg);
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		return;
	}

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	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
		 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);

	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
}

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static void intel_hdmi_mode_set(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	u32 sdvox;

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	sdvox = SDVO_ENCODING_HDMI;
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	if (!HAS_PCH_SPLIT(dev))
		sdvox |= intel_hdmi->color_range;
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	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
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	if (intel_crtc->bpp > 24)
		sdvox |= COLOR_FORMAT_12bpc;
	else
		sdvox |= COLOR_FORMAT_8bpc;

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	/* Required on CPT */
	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
		sdvox |= HDMI_MODE_SELECT;

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	if (intel_hdmi->has_audio) {
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		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
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		sdvox |= SDVO_AUDIO_ENABLE;
589
		sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
590
		intel_write_eld(encoder, adjusted_mode);
591
	}
592

593 594
	if (HAS_PCH_CPT(dev))
		sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
595
	else if (intel_crtc->pipe == PIPE_B)
596
		sdvox |= SDVO_PIPE_B_SELECT;
597

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598 599
	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
	POSTING_READ(intel_hdmi->sdvox_reg);
600

601
	intel_hdmi->set_infoframes(encoder, adjusted_mode);
602 603
}

604 605
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
				    enum pipe *pipe)
606
{
607
	struct drm_device *dev = encoder->base.dev;
608
	struct drm_i915_private *dev_priv = dev->dev_private;
609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 tmp;

	tmp = I915_READ(intel_hdmi->sdvox_reg);

	if (!(tmp & SDVO_ENABLE))
		return false;

	if (HAS_PCH_CPT(dev))
		*pipe = PORT_TO_PIPE_CPT(tmp);
	else
		*pipe = PORT_TO_PIPE(tmp);

	return true;
}

625
static void intel_enable_hdmi(struct intel_encoder *encoder)
626
{
627
	struct drm_device *dev = encoder->base.dev;
628
	struct drm_i915_private *dev_priv = dev->dev_private;
629
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
630
	u32 temp;
631 632 633 634
	u32 enable_bits = SDVO_ENABLE;

	if (intel_hdmi->has_audio)
		enable_bits |= SDVO_AUDIO_ENABLE;
635

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636
	temp = I915_READ(intel_hdmi->sdvox_reg);
637

638 639 640
	/* HW workaround for IBX, we need to move the port to transcoder A
	 * before disabling it. */
	if (HAS_PCH_IBX(dev)) {
641
		struct drm_crtc *crtc = encoder->base.crtc;
642 643
		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;

644 645 646
		/* Restore the transcoder select bit. */
		if (pipe == PIPE_B)
			enable_bits |= SDVO_PIPE_B_SELECT;
647 648
	}

649 650 651
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
652
	if (HAS_PCH_SPLIT(dev)) {
C
Chris Wilson 已提交
653 654
		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
655 656
	}

657 658 659 660 661 662 663 664 665 666 667
	temp |= enable_bits;

	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
668
	}
669 670 671 672 673 674 675 676
}

static void intel_disable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;
677
	u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702

	temp = I915_READ(intel_hdmi->sdvox_reg);

	/* HW workaround for IBX, we need to move the port to transcoder A
	 * before disabling it. */
	if (HAS_PCH_IBX(dev)) {
		struct drm_crtc *crtc = encoder->base.crtc;
		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;

		if (temp & SDVO_PIPE_B_SELECT) {
			temp &= ~SDVO_PIPE_B_SELECT;
			I915_WRITE(intel_hdmi->sdvox_reg, temp);
			POSTING_READ(intel_hdmi->sdvox_reg);

			/* Again we need to write this twice. */
			I915_WRITE(intel_hdmi->sdvox_reg, temp);
			POSTING_READ(intel_hdmi->sdvox_reg);

			/* Transcoder selection bits only update
			 * effectively on vblank. */
			if (crtc)
				intel_wait_for_vblank(dev, pipe);
			else
				msleep(50);
		}
703
	}
704

705 706 707 708 709 710 711 712 713
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}

	temp &= ~enable_bits;
714

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715 716
	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);
717 718 719 720

	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
721
	if (HAS_PCH_SPLIT(dev)) {
C
Chris Wilson 已提交
722 723
		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
724
	}
725 726 727 728 729 730 731 732
}

static int intel_hdmi_mode_valid(struct drm_connector *connector,
				 struct drm_display_mode *mode)
{
	if (mode->clock > 165000)
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
733
		return MODE_CLOCK_LOW;
734 735 736 737 738 739 740 741

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	return MODE_OK;
}

static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
742
				  const struct drm_display_mode *mode,
743 744 745 746 747
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}

748 749 750 751 752 753 754
static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
{
	struct drm_device *dev = intel_hdmi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t bit;

	switch (intel_hdmi->sdvox_reg) {
755
	case SDVOB:
756 757
		bit = HDMIB_HOTPLUG_LIVE_STATUS;
		break;
758
	case SDVOC:
759 760 761 762 763 764 765 766 767 768
		bit = HDMIC_HOTPLUG_LIVE_STATUS;
		break;
	default:
		bit = 0;
		break;
	}

	return I915_READ(PORT_HOTPLUG_STAT) & bit;
}

769
static enum drm_connector_status
770
intel_hdmi_detect(struct drm_connector *connector, bool force)
771
{
772
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
773 774
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
775
	enum drm_connector_status status = connector_status_disconnected;
776

777 778 779
	if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
		return status;

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Chris Wilson 已提交
780
	intel_hdmi->has_hdmi_sink = false;
781
	intel_hdmi->has_audio = false;
782
	edid = drm_get_edid(connector,
783 784
			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
785

786
	if (edid) {
787
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
788
			status = connector_status_connected;
789 790 791
			if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
				intel_hdmi->has_hdmi_sink =
						drm_detect_hdmi_monitor(edid);
792
			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
793 794
		}
		kfree(edid);
795
	}
796

797
	if (status == connector_status_connected) {
798 799 800
		if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
			intel_hdmi->has_audio =
				(intel_hdmi->force_audio == HDMI_AUDIO_ON);
801 802
	}

803
	return status;
804 805 806 807
}

static int intel_hdmi_get_modes(struct drm_connector *connector)
{
808
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
809
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
810 811 812 813 814

	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */

815
	return intel_ddc_get_modes(connector,
816 817
				   intel_gmbus_get_adapter(dev_priv,
							   intel_hdmi->ddc_bus));
818 819
}

820 821 822 823 824 825 826 827 828
static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	bool has_audio = false;

	edid = drm_get_edid(connector,
829 830
			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
831 832 833 834 835 836 837 838 839
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

	return has_audio;
}

840 841
static int
intel_hdmi_set_property(struct drm_connector *connector,
842 843
			struct drm_property *property,
			uint64_t val)
844 845
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
846
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
847 848 849 850 851 852
	int ret;

	ret = drm_connector_property_set_value(connector, property, val);
	if (ret)
		return ret;

853
	if (property == dev_priv->force_audio_property) {
854
		enum hdmi_force_audio i = val;
855 856 857
		bool has_audio;

		if (i == intel_hdmi->force_audio)
858 859
			return 0;

860
		intel_hdmi->force_audio = i;
861

862
		if (i == HDMI_AUDIO_AUTO)
863 864
			has_audio = intel_hdmi_detect_audio(connector);
		else
865
			has_audio = (i == HDMI_AUDIO_ON);
866

867 868
		if (i == HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink = 0;
869

870
		intel_hdmi->has_audio = has_audio;
871 872 873
		goto done;
	}

874 875 876 877 878 879 880 881
	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_hdmi->color_range)
			return 0;

		intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
		goto done;
	}

882 883 884 885 886
	return -EINVAL;

done:
	if (intel_hdmi->base.base.crtc) {
		struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
887 888
		intel_set_mode(crtc, &crtc->mode,
			       crtc->x, crtc->y, crtc->fb);
889 890 891 892 893
	}

	return 0;
}

894 895 896 897
static void intel_hdmi_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
898
	kfree(connector);
899 900
}

901 902 903
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
	.mode_fixup = intel_hdmi_mode_fixup,
	.mode_set = intel_ddi_mode_set,
904
	.disable = intel_encoder_noop,
905 906
};

907 908 909
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	.mode_fixup = intel_hdmi_mode_fixup,
	.mode_set = intel_hdmi_mode_set,
910
	.disable = intel_encoder_noop,
911 912 913
};

static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
914
	.dpms = intel_connector_dpms,
915 916
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
917
	.set_property = intel_hdmi_set_property,
918 919 920 921 922 923
	.destroy = intel_hdmi_destroy,
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
924
	.best_encoder = intel_best_encoder,
925 926 927
};

static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
C
Chris Wilson 已提交
928
	.destroy = intel_encoder_destroy,
929 930
};

931 932 933
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
934
	intel_attach_force_audio_property(connector);
935
	intel_attach_broadcast_rgb_property(connector);
936 937
}

938
void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
939 940 941
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
942
	struct intel_encoder *intel_encoder;
943
	struct intel_connector *intel_connector;
C
Chris Wilson 已提交
944
	struct intel_hdmi *intel_hdmi;
945

C
Chris Wilson 已提交
946 947
	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
	if (!intel_hdmi)
948
		return;
949 950 951

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
C
Chris Wilson 已提交
952
		kfree(intel_hdmi);
953 954 955
		return;
	}

C
Chris Wilson 已提交
956
	intel_encoder = &intel_hdmi->base;
957 958 959
	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

960
	connector = &intel_connector->base;
961
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
962
			   DRM_MODE_CONNECTOR_HDMIA);
963 964
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

965
	intel_encoder->type = INTEL_OUTPUT_HDMI;
966

967
	connector->polled = DRM_CONNECTOR_POLL_HPD;
968
	connector->interlace_allowed = 1;
969
	connector->doublescan_allowed = 0;
J
Jesse Barnes 已提交
970
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
971

972 973
	intel_encoder->cloneable = false;

974 975 976
	intel_hdmi->ddi_port = port;
	switch (port) {
	case PORT_B:
977
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
978
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
979 980
		break;
	case PORT_C:
981 982
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
983 984
		break;
	case PORT_D:
985 986
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
987 988 989 990
		break;
	case PORT_A:
		/* Internal port only for eDP. */
	default:
991
		BUG();
992
	}
993

C
Chris Wilson 已提交
994
	intel_hdmi->sdvox_reg = sdvox_reg;
995

996
	if (!HAS_PCH_SPLIT(dev)) {
997
		intel_hdmi->write_infoframe = g4x_write_infoframe;
998
		intel_hdmi->set_infoframes = g4x_set_infoframes;
999 1000
	} else if (IS_VALLEYVIEW(dev)) {
		intel_hdmi->write_infoframe = vlv_write_infoframe;
1001
		intel_hdmi->set_infoframes = vlv_set_infoframes;
1002 1003
	} else if (IS_HASWELL(dev)) {
		intel_hdmi->write_infoframe = hsw_write_infoframe;
1004
		intel_hdmi->set_infoframes = hsw_set_infoframes;
1005 1006
	} else if (HAS_PCH_IBX(dev)) {
		intel_hdmi->write_infoframe = ibx_write_infoframe;
1007
		intel_hdmi->set_infoframes = ibx_set_infoframes;
1008 1009
	} else {
		intel_hdmi->write_infoframe = cpt_write_infoframe;
1010
		intel_hdmi->set_infoframes = cpt_set_infoframes;
1011
	}
1012

1013 1014 1015
	if (IS_HASWELL(dev)) {
		intel_encoder->enable = intel_enable_ddi;
		intel_encoder->disable = intel_disable_ddi;
1016
		intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1017 1018 1019 1020 1021
		drm_encoder_helper_add(&intel_encoder->base,
				       &intel_hdmi_helper_funcs_hsw);
	} else {
		intel_encoder->enable = intel_enable_hdmi;
		intel_encoder->disable = intel_disable_hdmi;
1022
		intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1023 1024 1025
		drm_encoder_helper_add(&intel_encoder->base,
				       &intel_hdmi_helper_funcs);
	}
1026
	intel_connector->get_hw_state = intel_connector_get_hw_state;
1027

1028

1029 1030
	intel_hdmi_add_properties(intel_hdmi, connector);

1031
	intel_connector_attach_encoder(intel_connector, intel_encoder);
1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042
	drm_sysfs_connector_add(connector);

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}