mpc8568mds.dts 10.6 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
/*
 * MPC8568E MDS Device Tree Source
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


/*
/memreserve/	00000000 1000000;
*/

/ {
	model = "MPC8568EMDS";
19
	compatible = "MPC8568EMDS", "MPC85xxMDS";
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8568@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;	// 32 bytes
			i-cache-line-size = <20>;	// 32 bytes
			d-cache-size = <8000>;		// L1, 32K
			i-cache-size = <8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 10000000>;
	};

	bcsr@f8000000 {
		device_type = "board-control";
		reg = <f8000000 8000>;
	};

	soc8568@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0 e0000000 00100000>;
		reg = <e0000000 00100000>;
		bus-frequency = <0>;

58 59 60 61
		memory-controller@2000 {
			compatible = "fsl,8568-memory-controller";
			reg = <2000 1000>;
			interrupt-parent = <&mpic>;
62
			interrupts = <12 2>;
63 64 65 66 67 68 69 70
		};

		l2-cache-controller@20000 {
			compatible = "fsl,8568-l2-cache-controller";
			reg = <20000 1000>;
			cache-line-size = <20>;	// 32 bytes
			cache-size = <80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
71
			interrupts = <10 2>;
72 73
		};

74
		i2c@3000 {
75 76
			#address-cells = <1>;
			#size-cells = <0>;
77 78 79
			device_type = "i2c";
			compatible = "fsl-i2c";
			reg = <3000 100>;
80
			interrupts = <2b 2>;
81
			interrupt-parent = <&mpic>;
82
			dfsrr;
83 84 85 86 87

			rtc@68 {
				compatible = "dallas,ds1374";
				reg = <68>;
			};
88 89 90
		};

		i2c@3100 {
91 92
			#address-cells = <1>;
			#size-cells = <0>;
93 94 95
			device_type = "i2c";
			compatible = "fsl-i2c";
			reg = <3100 100>;
96
			interrupts = <2b 2>;
97
			interrupt-parent = <&mpic>;
98 99 100 101 102 103 104 105 106
			dfsrr;
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "mdio";
			compatible = "gianfar";
			reg = <24520 20>;
107 108
			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
109
				interrupts = <1 1>;
110 111 112
				reg = <0>;
				device_type = "ethernet-phy";
			};
113 114
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
115
				interrupts = <2 1>;
116 117 118
				reg = <1>;
				device_type = "ethernet-phy";
			};
119 120
			phy2: ethernet-phy@2 {
				interrupt-parent = <&mpic>;
121
				interrupts = <1 1>;
122 123 124
				reg = <2>;
				device_type = "ethernet-phy";
			};
125 126
			phy3: ethernet-phy@3 {
				interrupt-parent = <&mpic>;
127
				interrupts = <2 1>;
128 129 130 131 132 133 134 135 136 137 138 139
				reg = <3>;
				device_type = "ethernet-phy";
			};
		};

		ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <24000 1000>;
140 141 142 143 144
			/*
			 * mac-address is deprecated and will be removed
			 * in 2.6.25.  Only recent versions of
			 * U-Boot support local-mac-address, however.
			 */
145
			mac-address = [ 00 00 00 00 00 00 ];
146
			local-mac-address = [ 00 00 00 00 00 00 ];
147
 			interrupts = <1d 2 1e 2 22 2>;
148 149
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
150 151 152 153 154 155 156 157 158
		};

		ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <25000 1000>;
159 160 161 162 163 164 165
			/*
			 * mac-address is deprecated and will be removed
			 * in 2.6.25.  Only recent versions of
			 * U-Boot support local-mac-address, however.
			 */
			mac-address = [ 00 00 00 00 00 00 ];
			local-mac-address = [ 00 00 00 00 00 00 ];
166
 			interrupts = <23 2 24 2 28 2>;
167 168
			interrupt-parent = <&mpic>;
			phy-handle = <&phy3>;
169 170 171 172 173 174 175
		};

		serial@4500 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <4500 100>;
			clock-frequency = <0>;
176
			interrupts = <2a 2>;
177
			interrupt-parent = <&mpic>;
178 179
		};

180 181 182 183 184 185
		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,mpc8548-guts";
			reg = <e0000 1000>;
			fsl,has-rstcr;
		};

186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214
		pci@8000 {
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map = <
				/* IDSEL 0x12 AD18 */
				9000 0 0 1 &mpic 5 1
				9000 0 0 2 &mpic 6 1
				9000 0 0 3 &mpic 7 1
				9000 0 0 4 &mpic 4 1

				/* IDSEL 0x13 AD19 */
				9800 0 0 1 &mpic 6 1
				9800 0 0 2 &mpic 7 1
				9800 0 0 3 &mpic 4 1
				9800 0 0 4 &mpic 5 1>;

			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
			bus-range = <0 ff>;
			ranges = <02000000 0 80000000 80000000 0 20000000
				  01000000 0 00000000 e2000000 0 00800000>;
			clock-frequency = <3f940aa>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = <8000 1000>;
			compatible = "fsl,mpc8540-pci";
			device_type = "pci";
		};

215 216 217 218 219 220 221 222 223 224 225 226 227 228
		/* PCI Express */
		pcie@a000 {
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map = <

				/* IDSEL 0x0 (PEX) */
				00000 0 0 1 &mpic 0 1
				00000 0 0 2 &mpic 1 1
				00000 0 0 3 &mpic 2 1
				00000 0 0 4 &mpic 3 1>;

			interrupt-parent = <&mpic>;
			interrupts = <1a 2>;
			bus-range = <0 ff>;
229 230
			ranges = <02000000 0 a0000000 a0000000 0 10000000
				  01000000 0 00000000 e2800000 0 00800000>;
231 232 233 234 235 236 237 238 239
			clock-frequency = <1fca055>;
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = <a000 1000>;
			compatible = "fsl,mpc8548-pcie";
			device_type = "pci";
		};

240 241 242 243 244
		serial@4600 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <4600 100>;
			clock-frequency = <0>;
245
			interrupts = <2a 2>;
246
			interrupt-parent = <&mpic>;
247 248 249 250 251 252 253
		};

		crypto@30000 {
			device_type = "crypto";
			model = "SEC2";
			compatible = "talitos";
			reg = <30000 f000>;
254
			interrupts = <2d 2>;
255
			interrupt-parent = <&mpic>;
256 257 258 259 260 261
			num-channels = <4>;
			channel-fifo-len = <18>;
			exec-units-mask = <000000fe>;
			descriptor-types-mask = <012b0ebf>;
		};

262
		mpic: pic@40000 {
263 264 265 266 267 268 269 270 271 272 273 274 275 276
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <40000 40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
                        big-endian;
		};
		par_io@e0100 {
			reg = <e0100 100>;
			device_type = "par_io";
			num-ports = <7>;

277
			pio1: ucc_pin@01 {
278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					4  0a  1  0  2  0 	/* TxD0 */
					4  09  1  0  2  0 	/* TxD1 */
					4  08  1  0  2  0 	/* TxD2 */
					4  07  1  0  2  0 	/* TxD3 */
					4  17  1  0  2  0 	/* TxD4 */
					4  16  1  0  2  0 	/* TxD5 */
					4  15  1  0  2  0 	/* TxD6 */
					4  14  1  0  2  0 	/* TxD7 */
					4  0f  2  0  2  0 	/* RxD0 */
					4  0e  2  0  2  0 	/* RxD1 */
					4  0d  2  0  2  0 	/* RxD2 */
					4  0c  2  0  2  0 	/* RxD3 */
					4  1d  2  0  2  0 	/* RxD4 */
					4  1c  2  0  2  0 	/* RxD5 */
					4  1b  2  0  2  0 	/* RxD6 */
					4  1a  2  0  2  0 	/* RxD7 */
					4  0b  1  0  2  0 	/* TX_EN */
					4  18  1  0  2  0 	/* TX_ER */
					4  0f  2  0  2  0 	/* RX_DV */
					4  1e  2  0  2  0 	/* RX_ER */
					4  11  2  0  2  0 	/* RX_CLK */
					4  13  1  0  2  0 	/* GTX_CLK */
					1  1f  2  0  3  0>;	/* GTX125 */
			};
304
			pio2: ucc_pin@02 {
305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					5  0a 1  0  2  0   /* TxD0 */
					5  09 1  0  2  0   /* TxD1 */
					5  08 1  0  2  0   /* TxD2 */
					5  07 1  0  2  0   /* TxD3 */
					5  17 1  0  2  0   /* TxD4 */
					5  16 1  0  2  0   /* TxD5 */
					5  15 1  0  2  0   /* TxD6 */
					5  14 1  0  2  0   /* TxD7 */
					5  0f 2  0  2  0   /* RxD0 */
					5  0e 2  0  2  0   /* RxD1 */
					5  0d 2  0  2  0   /* RxD2 */
					5  0c 2  0  2  0   /* RxD3 */
					5  1d 2  0  2  0   /* RxD4 */
					5  1c 2  0  2  0   /* RxD5 */
					5  1b 2  0  2  0   /* RxD6 */
					5  1a 2  0  2  0   /* RxD7 */
					5  0b 1  0  2  0   /* TX_EN */
					5  18 1  0  2  0   /* TX_ER */
					5  10 2  0  2  0   /* RX_DV */
					5  1e 2  0  2  0   /* RX_ER */
					5  11 2  0  2  0   /* RX_CLK */
					5  13 1  0  2  0   /* GTX_CLK */
					1  1f 2  0  3  0   /* GTX125 */
					4  06 3  0  2  0   /* MDIO */
					4  05 1  0  2  0>; /* MDC */
			};
		};
	};

	qe@e0080000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "qe";
		model = "QE";
		ranges = <0 e0080000 00040000>;
		reg = <e0080000 480>;
		brg-frequency = <0>;
		bus-frequency = <179A7B00>;

		muram@10000 {
			device_type = "muram";
			ranges = <0 00010000 0000c000>;

			data-only@0{
				reg = <0 c000>;
			};
		};

		spi@4c0 {
			device_type = "spi";
			compatible = "fsl_spi";
			reg = <4c0 40>;
			interrupts = <2>;
360
			interrupt-parent = <&qeic>;
361 362 363 364 365 366 367 368
			mode = "cpu";
		};

		spi@500 {
			device_type = "spi";
			compatible = "fsl_spi";
			reg = <500 40>;
			interrupts = <1>;
369
			interrupt-parent = <&qeic>;
370 371 372 373 374 375 376 377 378 379
			mode = "cpu";
		};

		ucc@2000 {
			device_type = "network";
			compatible = "ucc_geth";
			model = "UCC";
			device-id = <1>;
			reg = <2000 200>;
			interrupts = <20>;
380
			interrupt-parent = <&qeic>;
381 382 383 384 385 386 387
			/*
			 * mac-address is deprecated and will be removed
			 * in 2.6.25.  Only recent versions of
			 * U-Boot support local-mac-address, however.
			 */
			mac-address = [ 00 00 00 00 00 00 ];
			local-mac-address = [ 00 00 00 00 00 00 ];
388 389
			rx-clock = <0>;
			tx-clock = <19>;
390
			phy-handle = <&qe_phy0>;
391
			phy-connection-type = "gmii";
392
			pio-handle = <&pio1>;
393 394 395 396 397 398 399 400 401
		};

		ucc@3000 {
			device_type = "network";
			compatible = "ucc_geth";
			model = "UCC";
			device-id = <2>;
			reg = <3000 200>;
			interrupts = <21>;
402
			interrupt-parent = <&qeic>;
403 404 405 406 407 408 409
			/*
			 * mac-address is deprecated and will be removed
			 * in 2.6.25.  Only recent versions of
			 * U-Boot support local-mac-address, however.
			 */
			mac-address = [ 00 00 00 00 00 00 ];
			local-mac-address = [ 00 00 00 00 00 00 ];
410 411
			rx-clock = <0>;
			tx-clock = <14>;
412
			phy-handle = <&qe_phy1>;
413
			phy-connection-type = "gmii";
414
			pio-handle = <&pio2>;
415 416 417 418 419 420 421 422 423 424 425
		};

		mdio@2120 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2120 18>;
			device_type = "mdio";
			compatible = "ucc_geth_phy";

			/* These are the same PHYs as on
			 * gianfar's MDIO bus */
426 427
			qe_phy0: ethernet-phy@00 {
				interrupt-parent = <&mpic>;
428
				interrupts = <1 1>;
429 430 431
				reg = <0>;
				device_type = "ethernet-phy";
			};
432 433
			qe_phy1: ethernet-phy@01 {
				interrupt-parent = <&mpic>;
434
				interrupts = <2 1>;
435 436 437
				reg = <1>;
				device_type = "ethernet-phy";
			};
438 439
			qe_phy2: ethernet-phy@02 {
				interrupt-parent = <&mpic>;
440
				interrupts = <1 1>;
441 442 443
				reg = <2>;
				device_type = "ethernet-phy";
			};
444 445
			qe_phy3: ethernet-phy@03 {
				interrupt-parent = <&mpic>;
446
				interrupts = <2 1>;
447 448 449 450 451
				reg = <3>;
				device_type = "ethernet-phy";
			};
		};

452
		qeic: qeic@80 {
453 454 455 456 457 458
			interrupt-controller;
			device_type = "qeic";
			#address-cells = <0>;
			#interrupt-cells = <1>;
			reg = <80 80>;
			big-endian;
459
			interrupts = <2e 2 2e 2>; //high:30 low:30
460
			interrupt-parent = <&mpic>;
461 462 463 464
		};

	};
};