sata_nv.c 69.3 KB
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/*
 *  sata_nv.c - NVIDIA nForce SATA
 *
 *  Copyright 2004 NVIDIA Corp.  All rights reserved.
 *  Copyright 2004 Andrew Chew
 *
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 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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 *
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 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  No hardware documentation available outside of NVIDIA.
 *  This driver programs the NVIDIA SATA controller in a similar
 *  fashion as with other PCI IDE BMDMA controllers, with a few
 *  NV-specific details such as register offsets, SATA phy location,
 *  hotplug info, etc.
 *
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 *  CK804/MCP04 controllers support an alternate programming interface
 *  similar to the ADMA specification (with some modifications).
 *  This allows the use of NCQ. Non-DMA-mapped ATA commands are still
 *  sent through the legacy interface.
 *
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 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_device.h>
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#include <linux/libata.h>

#define DRV_NAME			"sata_nv"
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#define DRV_VERSION			"3.5"
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#define NV_ADMA_DMA_BOUNDARY		0xffffffffUL
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enum {
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	NV_MMIO_BAR			= 5,

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	NV_PORTS			= 2,
	NV_PIO_MASK			= 0x1f,
	NV_MWDMA_MASK			= 0x07,
	NV_UDMA_MASK			= 0x7f,
	NV_PORT0_SCR_REG_OFFSET		= 0x00,
	NV_PORT1_SCR_REG_OFFSET		= 0x40,
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	/* INT_STATUS/ENABLE */
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	NV_INT_STATUS			= 0x10,
	NV_INT_ENABLE			= 0x11,
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	NV_INT_STATUS_CK804		= 0x440,
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	NV_INT_ENABLE_CK804		= 0x441,
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	/* INT_STATUS/ENABLE bits */
	NV_INT_DEV			= 0x01,
	NV_INT_PM			= 0x02,
	NV_INT_ADDED			= 0x04,
	NV_INT_REMOVED			= 0x08,

	NV_INT_PORT_SHIFT		= 4,	/* each port occupies 4 bits */

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	NV_INT_ALL			= 0x0f,
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	NV_INT_MASK			= NV_INT_DEV |
					  NV_INT_ADDED | NV_INT_REMOVED,
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	/* INT_CONFIG */
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	NV_INT_CONFIG			= 0x12,
	NV_INT_CONFIG_METHD		= 0x01, // 0 = INT, 1 = SMI
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	// For PCI config register 20
	NV_MCP_SATA_CFG_20		= 0x50,
	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
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	NV_MCP_SATA_CFG_20_PORT0_EN	= (1 << 17),
	NV_MCP_SATA_CFG_20_PORT1_EN	= (1 << 16),
	NV_MCP_SATA_CFG_20_PORT0_PWB_EN	= (1 << 14),
	NV_MCP_SATA_CFG_20_PORT1_PWB_EN	= (1 << 12),

	NV_ADMA_MAX_CPBS		= 32,
	NV_ADMA_CPB_SZ			= 128,
	NV_ADMA_APRD_SZ			= 16,
	NV_ADMA_SGTBL_LEN		= (1024 - NV_ADMA_CPB_SZ) /
					   NV_ADMA_APRD_SZ,
	NV_ADMA_SGTBL_TOTAL_LEN		= NV_ADMA_SGTBL_LEN + 5,
	NV_ADMA_SGTBL_SZ                = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
	NV_ADMA_PORT_PRIV_DMA_SZ        = NV_ADMA_MAX_CPBS *
					   (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),

	/* BAR5 offset to ADMA general registers */
	NV_ADMA_GEN			= 0x400,
	NV_ADMA_GEN_CTL			= 0x00,
	NV_ADMA_NOTIFIER_CLEAR		= 0x30,

	/* BAR5 offset to ADMA ports */
	NV_ADMA_PORT			= 0x480,

	/* size of ADMA port register space  */
	NV_ADMA_PORT_SIZE		= 0x100,

	/* ADMA port registers */
	NV_ADMA_CTL			= 0x40,
	NV_ADMA_CPB_COUNT		= 0x42,
	NV_ADMA_NEXT_CPB_IDX		= 0x43,
	NV_ADMA_STAT			= 0x44,
	NV_ADMA_CPB_BASE_LOW		= 0x48,
	NV_ADMA_CPB_BASE_HIGH		= 0x4C,
	NV_ADMA_APPEND			= 0x50,
	NV_ADMA_NOTIFIER		= 0x68,
	NV_ADMA_NOTIFIER_ERROR		= 0x6C,

	/* NV_ADMA_CTL register bits */
	NV_ADMA_CTL_HOTPLUG_IEN		= (1 << 0),
	NV_ADMA_CTL_CHANNEL_RESET	= (1 << 5),
	NV_ADMA_CTL_GO			= (1 << 7),
	NV_ADMA_CTL_AIEN		= (1 << 8),
	NV_ADMA_CTL_READ_NON_COHERENT	= (1 << 11),
	NV_ADMA_CTL_WRITE_NON_COHERENT	= (1 << 12),

	/* CPB response flag bits */
	NV_CPB_RESP_DONE		= (1 << 0),
	NV_CPB_RESP_ATA_ERR		= (1 << 3),
	NV_CPB_RESP_CMD_ERR		= (1 << 4),
	NV_CPB_RESP_CPB_ERR		= (1 << 7),

	/* CPB control flag bits */
	NV_CPB_CTL_CPB_VALID		= (1 << 0),
	NV_CPB_CTL_QUEUE		= (1 << 1),
	NV_CPB_CTL_APRD_VALID		= (1 << 2),
	NV_CPB_CTL_IEN			= (1 << 3),
	NV_CPB_CTL_FPDMA		= (1 << 4),

	/* APRD flags */
	NV_APRD_WRITE			= (1 << 1),
	NV_APRD_END			= (1 << 2),
	NV_APRD_CONT			= (1 << 3),

	/* NV_ADMA_STAT flags */
	NV_ADMA_STAT_TIMEOUT		= (1 << 0),
	NV_ADMA_STAT_HOTUNPLUG		= (1 << 1),
	NV_ADMA_STAT_HOTPLUG		= (1 << 2),
	NV_ADMA_STAT_CPBERR		= (1 << 4),
	NV_ADMA_STAT_SERROR		= (1 << 5),
	NV_ADMA_STAT_CMD_COMPLETE	= (1 << 6),
	NV_ADMA_STAT_IDLE		= (1 << 8),
	NV_ADMA_STAT_LEGACY		= (1 << 9),
	NV_ADMA_STAT_STOPPED		= (1 << 10),
	NV_ADMA_STAT_DONE		= (1 << 12),
	NV_ADMA_STAT_ERR		= NV_ADMA_STAT_CPBERR |
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					  NV_ADMA_STAT_TIMEOUT,
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	/* port flags */
	NV_ADMA_PORT_REGISTER_MODE	= (1 << 0),
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	NV_ADMA_ATAPI_SETUP_COMPLETE	= (1 << 1),
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	/* MCP55 reg offset */
	NV_CTL_MCP55			= 0x400,
	NV_INT_STATUS_MCP55		= 0x440,
	NV_INT_ENABLE_MCP55		= 0x444,
	NV_NCQ_REG_MCP55		= 0x448,

	/* MCP55 */
	NV_INT_ALL_MCP55		= 0xffff,
	NV_INT_PORT_SHIFT_MCP55		= 16,	/* each port occupies 16 bits */
	NV_INT_MASK_MCP55		= NV_INT_ALL_MCP55 & 0xfffd,

	/* SWNCQ ENABLE BITS*/
	NV_CTL_PRI_SWNCQ		= 0x02,
	NV_CTL_SEC_SWNCQ		= 0x04,

	/* SW NCQ status bits*/
	NV_SWNCQ_IRQ_DEV		= (1 << 0),
	NV_SWNCQ_IRQ_PM			= (1 << 1),
	NV_SWNCQ_IRQ_ADDED		= (1 << 2),
	NV_SWNCQ_IRQ_REMOVED		= (1 << 3),

	NV_SWNCQ_IRQ_BACKOUT		= (1 << 4),
	NV_SWNCQ_IRQ_SDBFIS		= (1 << 5),
	NV_SWNCQ_IRQ_DHREGFIS		= (1 << 6),
	NV_SWNCQ_IRQ_DMASETUP		= (1 << 7),

	NV_SWNCQ_IRQ_HOTPLUG		= NV_SWNCQ_IRQ_ADDED |
					  NV_SWNCQ_IRQ_REMOVED,

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};

/* ADMA Physical Region Descriptor - one SG segment */
struct nv_adma_prd {
	__le64			addr;
	__le32			len;
	u8			flags;
	u8			packet_len;
	__le16			reserved;
};

enum nv_adma_regbits {
	CMDEND	= (1 << 15),		/* end of command list */
	WNB	= (1 << 14),		/* wait-not-BSY */
	IGN	= (1 << 13),		/* ignore this entry */
	CS1n	= (1 << (4 + 8)),	/* std. PATA signals follow... */
	DA2	= (1 << (2 + 8)),
	DA1	= (1 << (1 + 8)),
	DA0	= (1 << (0 + 8)),
};

/* ADMA Command Parameter Block
   The first 5 SG segments are stored inside the Command Parameter Block itself.
   If there are more than 5 segments the remainder are stored in a separate
   memory area indicated by next_aprd. */
struct nv_adma_cpb {
	u8			resp_flags;    /* 0 */
	u8			reserved1;     /* 1 */
	u8			ctl_flags;     /* 2 */
	/* len is length of taskfile in 64 bit words */
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	u8			len;		/* 3  */
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	u8			tag;           /* 4 */
	u8			next_cpb_idx;  /* 5 */
	__le16			reserved2;     /* 6-7 */
	__le16			tf[12];        /* 8-31 */
	struct nv_adma_prd	aprd[5];       /* 32-111 */
	__le64			next_aprd;     /* 112-119 */
	__le64			reserved3;     /* 120-127 */
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};
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struct nv_adma_port_priv {
	struct nv_adma_cpb	*cpb;
	dma_addr_t		cpb_dma;
	struct nv_adma_prd	*aprd;
	dma_addr_t		aprd_dma;
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	void __iomem		*ctl_block;
	void __iomem		*gen_block;
	void __iomem		*notifier_clear_block;
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	u64			adma_dma_mask;
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	u8			flags;
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	int			last_issue_ncq;
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};

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struct nv_host_priv {
	unsigned long		type;
};

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struct defer_queue {
	u32		defer_bits;
	unsigned int	head;
	unsigned int	tail;
	unsigned int	tag[ATA_MAX_QUEUE];
};

enum ncq_saw_flag_list {
	ncq_saw_d2h	= (1U << 0),
	ncq_saw_dmas	= (1U << 1),
	ncq_saw_sdb	= (1U << 2),
	ncq_saw_backout	= (1U << 3),
};

struct nv_swncq_port_priv {
	struct ata_prd	*prd;	 /* our SG list */
	dma_addr_t	prd_dma; /* and its DMA mapping */
	void __iomem	*sactive_block;
	void __iomem	*irq_block;
	void __iomem	*tag_block;
	u32		qc_active;

	unsigned int	last_issue_tag;

	/* fifo circular queue to store deferral command */
	struct defer_queue defer_queue;

	/* for NCQ interrupt analysis */
	u32		dhfis_bits;
	u32		dmafis_bits;
	u32		sdbfis_bits;

	unsigned int	ncq_flags;
};


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#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT)))))
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static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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#ifdef CONFIG_PM
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static int nv_pci_device_resume(struct pci_dev *pdev);
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#endif
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static void nv_ck804_host_stop(struct ata_host *host);
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static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
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static int nv_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
static int nv_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
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static void nv_nf2_freeze(struct ata_port *ap);
static void nv_nf2_thaw(struct ata_port *ap);
static void nv_ck804_freeze(struct ata_port *ap);
static void nv_ck804_thaw(struct ata_port *ap);
static void nv_error_handler(struct ata_port *ap);
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static int nv_adma_slave_config(struct scsi_device *sdev);
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static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
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static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
static void nv_adma_irq_clear(struct ata_port *ap);
static int nv_adma_port_start(struct ata_port *ap);
static void nv_adma_port_stop(struct ata_port *ap);
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#ifdef CONFIG_PM
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static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int nv_adma_port_resume(struct ata_port *ap);
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#endif
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static void nv_adma_freeze(struct ata_port *ap);
static void nv_adma_thaw(struct ata_port *ap);
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static void nv_adma_error_handler(struct ata_port *ap);
static void nv_adma_host_stop(struct ata_host *host);
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static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
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static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
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static void nv_mcp55_thaw(struct ata_port *ap);
static void nv_mcp55_freeze(struct ata_port *ap);
static void nv_swncq_error_handler(struct ata_port *ap);
static int nv_swncq_slave_config(struct scsi_device *sdev);
static int nv_swncq_port_start(struct ata_port *ap);
static void nv_swncq_qc_prep(struct ata_queued_cmd *qc);
static void nv_swncq_fill_sg(struct ata_queued_cmd *qc);
static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc);
static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis);
static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance);
#ifdef CONFIG_PM
static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int nv_swncq_port_resume(struct ata_port *ap);
#endif

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enum nv_host_type
{
	GENERIC,
	NFORCE2,
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	NFORCE3 = NFORCE2,	/* NF2 == NF3 as far as sata_nv is concerned */
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	CK804,
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	ADMA,
	SWNCQ,
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};

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static const struct pci_device_id nv_pci_tbl[] = {
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	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
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	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), SWNCQ },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), SWNCQ },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), SWNCQ },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), SWNCQ },
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	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
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	{ } /* terminate list */
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};

static struct pci_driver nv_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= nv_pci_tbl,
	.probe			= nv_init_one,
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#ifdef CONFIG_PM
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	.suspend		= ata_pci_device_suspend,
	.resume			= nv_pci_device_resume,
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#endif
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	.remove			= ata_pci_remove_one,
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};

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static struct scsi_host_template nv_sht = {
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	ATA_BMDMA_SHT(DRV_NAME),
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};

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static struct scsi_host_template nv_adma_sht = {
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	ATA_NCQ_SHT(DRV_NAME),
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	.can_queue		= NV_ADMA_MAX_CPBS,
	.sg_tablesize		= NV_ADMA_SGTBL_TOTAL_LEN,
	.dma_boundary		= NV_ADMA_DMA_BOUNDARY,
	.slave_configure	= nv_adma_slave_config,
};

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static struct scsi_host_template nv_swncq_sht = {
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	ATA_NCQ_SHT(DRV_NAME),
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	.can_queue		= ATA_MAX_QUEUE,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= nv_swncq_slave_config,
};

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static const struct ata_port_operations nv_generic_ops = {
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	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
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	.mode_filter		= ata_pci_default_filter,
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	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
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	.data_xfer		= ata_data_xfer,
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	.irq_clear		= ata_bmdma_irq_clear,
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	.irq_on			= ata_irq_on,
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	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
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	.port_start		= ata_sff_port_start,
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};

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static const struct ata_port_operations nv_nf2_ops = {
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
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	.mode_filter		= ata_pci_default_filter,
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	.freeze			= nv_nf2_freeze,
	.thaw			= nv_nf2_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
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	.data_xfer		= ata_data_xfer,
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	.irq_clear		= ata_bmdma_irq_clear,
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	.irq_on			= ata_irq_on,
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	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
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	.port_start		= ata_sff_port_start,
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};

static const struct ata_port_operations nv_ck804_ops = {
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
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	.mode_filter		= ata_pci_default_filter,
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	.freeze			= nv_ck804_freeze,
	.thaw			= nv_ck804_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
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	.data_xfer		= ata_data_xfer,
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	.irq_clear		= ata_bmdma_irq_clear,
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	.irq_on			= ata_irq_on,
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	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
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	.port_start		= ata_sff_port_start,
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	.host_stop		= nv_ck804_host_stop,
};

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static const struct ata_port_operations nv_adma_ops = {
	.tf_load		= ata_tf_load,
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	.tf_read		= nv_adma_tf_read,
486
	.check_atapi_dma	= nv_adma_check_atapi_dma,
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	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
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	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
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	.qc_defer		= ata_std_qc_defer,
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	.qc_prep		= nv_adma_qc_prep,
	.qc_issue		= nv_adma_qc_issue,
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	.mode_filter		= ata_pci_default_filter,
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	.freeze			= nv_adma_freeze,
	.thaw			= nv_adma_thaw,
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	.error_handler		= nv_adma_error_handler,
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	.post_internal_cmd	= nv_adma_post_internal_cmd,
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	.data_xfer		= ata_data_xfer,
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	.irq_clear		= nv_adma_irq_clear,
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	.irq_on			= ata_irq_on,
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	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= nv_adma_port_start,
	.port_stop		= nv_adma_port_stop,
509
#ifdef CONFIG_PM
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	.port_suspend		= nv_adma_port_suspend,
	.port_resume		= nv_adma_port_resume,
512
#endif
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	.host_stop		= nv_adma_host_stop,
};

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static const struct ata_port_operations nv_swncq_ops = {
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_defer		= ata_std_qc_defer,
	.qc_prep		= nv_swncq_qc_prep,
	.qc_issue		= nv_swncq_qc_issue,
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	.mode_filter		= ata_pci_default_filter,
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	.freeze			= nv_mcp55_freeze,
	.thaw			= nv_mcp55_thaw,
	.error_handler		= nv_swncq_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.data_xfer		= ata_data_xfer,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
#ifdef CONFIG_PM
	.port_suspend		= nv_swncq_port_suspend,
	.port_resume		= nv_swncq_port_resume,
#endif
	.port_start		= nv_swncq_port_start,
};

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static const struct ata_port_info nv_port_info[] = {
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	/* generic */
	{
		.sht		= &nv_sht,
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		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_generic_ops,
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		.irq_handler	= nv_generic_interrupt,
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	},
	/* nforce2/3 */
	{
		.sht		= &nv_sht,
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		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_nf2_ops,
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		.irq_handler	= nv_nf2_interrupt,
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	},
	/* ck804 */
	{
		.sht		= &nv_sht,
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		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_ck804_ops,
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		.irq_handler	= nv_ck804_interrupt,
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	},
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	/* ADMA */
	{
		.sht		= &nv_adma_sht,
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO | ATA_FLAG_NCQ,
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_adma_ops,
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		.irq_handler	= nv_adma_interrupt,
587
	},
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	/* SWNCQ */
	{
		.sht		= &nv_swncq_sht,
		.flags	        = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_NCQ,
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_swncq_ops,
		.irq_handler	= nv_swncq_interrupt,
	},
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};

MODULE_AUTHOR("NVIDIA");
MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
MODULE_VERSION(DRV_VERSION);

607
static int adma_enabled = 1;
608
static int swncq_enabled;
609

610 611 612
static void nv_adma_register_mode(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
613
	void __iomem *mmio = pp->ctl_block;
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	u16 tmp, status;
	int count = 0;
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	if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
		return;

620
	status = readw(mmio + NV_ADMA_STAT);
621
	while (!(status & NV_ADMA_STAT_IDLE) && count < 20) {
622 623 624 625
		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
626
	if (count == 20)
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		ata_port_printk(ap, KERN_WARNING,
			"timeout waiting for ADMA IDLE, stat=0x%hx\n",
			status);

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	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);

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	count = 0;
	status = readw(mmio + NV_ADMA_STAT);
636
	while (!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
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		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
641
	if (count == 20)
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		ata_port_printk(ap, KERN_WARNING,
			 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
			 status);

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	pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
}

static void nv_adma_mode(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
652
	void __iomem *mmio = pp->ctl_block;
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	u16 tmp, status;
	int count = 0;
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	if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
		return;
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	WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);

	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);

664
	status = readw(mmio + NV_ADMA_STAT);
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	while (((status & NV_ADMA_STAT_LEGACY) ||
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	      !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
671
	if (count == 20)
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		ata_port_printk(ap, KERN_WARNING,
			"timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
			status);

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	pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
}

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static int nv_adma_slave_config(struct scsi_device *sdev)
{
	struct ata_port *ap = ata_shost_to_port(sdev->host);
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	struct nv_adma_port_priv *pp = ap->private_data;
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	struct nv_adma_port_priv *port0, *port1;
	struct scsi_device *sdev0, *sdev1;
685
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
686
	unsigned long segment_boundary, flags;
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	unsigned short sg_tablesize;
	int rc;
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	int adma_enable;
	u32 current_reg, new_reg, config_mask;
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	rc = ata_scsi_slave_config(sdev);

	if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
		/* Not a proper libata device, ignore */
		return rc;

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	spin_lock_irqsave(ap->lock, flags);

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	if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) {
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		/*
		 * NVIDIA reports that ADMA mode does not support ATAPI commands.
		 * Therefore ATAPI commands are sent through the legacy interface.
		 * However, the legacy interface only supports 32-bit DMA.
		 * Restrict DMA parameters as required by the legacy interface
		 * when an ATAPI device is connected.
		 */
		segment_boundary = ATA_DMA_BOUNDARY;
		/* Subtract 1 since an extra entry may be needed for padding, see
		   libata-scsi.c */
		sg_tablesize = LIBATA_MAX_PRD - 1;
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		/* Since the legacy DMA engine is in use, we need to disable ADMA
		   on the port. */
		adma_enable = 0;
		nv_adma_register_mode(ap);
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	} else {
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		segment_boundary = NV_ADMA_DMA_BOUNDARY;
		sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
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		adma_enable = 1;
721
	}
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	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);

725
	if (ap->port_no == 1)
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		config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
			      NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
	else
		config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
			      NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
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	if (adma_enable) {
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		new_reg = current_reg | config_mask;
		pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
735
	} else {
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		new_reg = current_reg & ~config_mask;
		pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
	}
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740
	if (current_reg != new_reg)
741
		pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
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	port0 = ap->host->ports[0]->private_data;
	port1 = ap->host->ports[1]->private_data;
	sdev0 = ap->host->ports[0]->link.device[0].sdev;
	sdev1 = ap->host->ports[1]->link.device[0].sdev;
	if ((port0->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
	    (port1->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)) {
		/** We have to set the DMA mask to 32-bit if either port is in
		    ATAPI mode, since they are on the same PCI device which is
		    used for DMA mapping. If we set the mask we also need to set
		    the bounce limit on both ports to ensure that the block
		    layer doesn't feed addresses that cause DMA mapping to
		    choke. If either SCSI device is not allocated yet, it's OK
		    since that port will discover its correct setting when it
		    does get allocated.
		    Note: Setting 32-bit mask should not fail. */
		if (sdev0)
			blk_queue_bounce_limit(sdev0->request_queue,
					       ATA_DMA_MASK);
		if (sdev1)
			blk_queue_bounce_limit(sdev1->request_queue,
					       ATA_DMA_MASK);

		pci_set_dma_mask(pdev, ATA_DMA_MASK);
	} else {
		/** This shouldn't fail as it was set to this value before */
		pci_set_dma_mask(pdev, pp->adma_dma_mask);
		if (sdev0)
			blk_queue_bounce_limit(sdev0->request_queue,
					       pp->adma_dma_mask);
		if (sdev1)
			blk_queue_bounce_limit(sdev1->request_queue,
					       pp->adma_dma_mask);
	}

777 778 779
	blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
	blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize);
	ata_port_printk(ap, KERN_INFO,
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		"DMA mask 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
		(unsigned long long)*ap->host->dev->dma_mask,
		segment_boundary, sg_tablesize);

	spin_unlock_irqrestore(ap->lock, flags);

786 787 788
	return rc;
}

789 790 791 792 793 794
static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
}

795 796
static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
797 798 799 800 801 802 803
	/* Other than when internal or pass-through commands are executed,
	   the only time this function will be called in ADMA mode will be
	   if a command fails. In the failure case we don't care about going
	   into register mode with ADMA commands pending, as the commands will
	   all shortly be aborted anyway. We assume that NCQ commands are not
	   issued via passthrough, which is the only way that switching into
	   ADMA mode could abort outstanding commands. */
804 805 806 807 808
	nv_adma_register_mode(ap);

	ata_tf_read(ap, tf);
}

809
static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
810 811 812
{
	unsigned int idx = 0;

813
	if (tf->flags & ATA_TFLAG_ISADDR) {
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		if (tf->flags & ATA_TFLAG_LBA48) {
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR   << 8) | tf->hob_feature | WNB);
			cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAL  << 8) | tf->hob_lbal);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAM  << 8) | tf->hob_lbam);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAH  << 8) | tf->hob_lbah);
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR    << 8) | tf->feature);
		} else
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR    << 8) | tf->feature | WNB);
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		cpb[idx++] = cpu_to_le16((ATA_REG_NSECT  << 8) | tf->nsect);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAL   << 8) | tf->lbal);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAM   << 8) | tf->lbam);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAH   << 8) | tf->lbah);
828
	}
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830
	if (tf->flags & ATA_TFLAG_DEVICE)
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		cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
832 833

	cpb[idx++] = cpu_to_le16((ATA_REG_CMD    << 8) | tf->command | CMDEND);
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835
	while (idx < 12)
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		cpb[idx++] = cpu_to_le16(IGN);
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	return idx;
}

841
static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
842 843
{
	struct nv_adma_port_priv *pp = ap->private_data;
844
	u8 flags = pp->cpb[cpb_num].resp_flags;
845 846 847

	VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);

848 849 850 851
	if (unlikely((force_err ||
		     flags & (NV_CPB_RESP_ATA_ERR |
			      NV_CPB_RESP_CMD_ERR |
			      NV_CPB_RESP_CPB_ERR)))) {
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		struct ata_eh_info *ehi = &ap->link.eh_info;
853 854 855
		int freeze = 0;

		ata_ehi_clear_desc(ehi);
856
		__ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags);
857
		if (flags & NV_CPB_RESP_ATA_ERR) {
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			ata_ehi_push_desc(ehi, "ATA error");
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			ehi->err_mask |= AC_ERR_DEV;
		} else if (flags & NV_CPB_RESP_CMD_ERR) {
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			ata_ehi_push_desc(ehi, "CMD error");
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			ehi->err_mask |= AC_ERR_DEV;
		} else if (flags & NV_CPB_RESP_CPB_ERR) {
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			ata_ehi_push_desc(ehi, "CPB error");
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			ehi->err_mask |= AC_ERR_SYSTEM;
			freeze = 1;
		} else {
			/* notifier error, but no error in CPB flags? */
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			ata_ehi_push_desc(ehi, "unknown");
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			ehi->err_mask |= AC_ERR_OTHER;
			freeze = 1;
		}
		/* Kill all commands. EH will determine what actually failed. */
		if (freeze)
			ata_port_freeze(ap);
		else
			ata_port_abort(ap);
		return 1;
879
	}
880

881
	if (likely(flags & NV_CPB_RESP_DONE)) {
882
		struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
883 884
		VPRINTK("CPB flags done, flags=0x%x\n", flags);
		if (likely(qc)) {
885
			DPRINTK("Completing qc from tag %d\n", cpb_num);
886
			ata_qc_complete(qc);
887
		} else {
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			struct ata_eh_info *ehi = &ap->link.eh_info;
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			/* Notifier bits set without a command may indicate the drive
			   is misbehaving. Raise host state machine violation on this
			   condition. */
892 893 894
			ata_port_printk(ap, KERN_ERR,
					"notifier for tag %d with no cmd?\n",
					cpb_num);
895
			ehi->err_mask |= AC_ERR_HSM;
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			ehi->action |= ATA_EH_RESET;
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			ata_port_freeze(ap);
			return 1;
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		}
	}
901
	return 0;
902 903
}

904 905
static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
{
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	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
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	/* freeze if hotplugged */
	if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
		ata_port_freeze(ap);
		return 1;
	}

	/* bail out if not our interrupt */
	if (!(irq_stat & NV_INT_DEV))
		return 0;

	/* DEV interrupt w/ no active qc? */
	if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
		ata_check_status(ap);
		return 1;
	}

	/* handle interrupt */
925
	return ata_host_intr(ap, qc);
926 927
}

928 929 930 931
static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	int i, handled = 0;
932
	u32 notifier_clears[2];
933 934 935 936 937

	spin_lock(&host->lock);

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
938
		notifier_clears[i] = 0;
939 940 941

		if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
			struct nv_adma_port_priv *pp = ap->private_data;
942
			void __iomem *mmio = pp->ctl_block;
943 944 945
			u16 status;
			u32 gen_ctl;
			u32 notifier, notifier_error;
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947 948 949 950 951 952 953
			/* if ADMA is disabled, use standard ata interrupt handler */
			if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
				u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
					>> (NV_INT_PORT_SHIFT * i);
				handled += nv_host_intr(ap, irq_stat);
				continue;
			}
954

955
			/* if in ATA register mode, check for standard interrupts */
956
			if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
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957
				u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
958
					>> (NV_INT_PORT_SHIFT * i);
959
				if (ata_tag_valid(ap->link.active_tag))
960 961 962 963
					/** NV_INT_DEV indication seems unreliable at times
					    at least in ADMA mode. Force it on always when a
					    command is active, to prevent losing interrupts. */
					irq_stat |= NV_INT_DEV;
964
				handled += nv_host_intr(ap, irq_stat);
965 966 967 968
			}

			notifier = readl(mmio + NV_ADMA_NOTIFIER);
			notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
969
			notifier_clears[i] = notifier | notifier_error;
970

971
			gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
972

973
			if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
974 975 976 977 978 979 980 981 982 983 984 985 986
			    !notifier_error)
				/* Nothing to do */
				continue;

			status = readw(mmio + NV_ADMA_STAT);

			/* Clear status. Ensure the controller sees the clearing before we start
			   looking at any of the CPB statuses, so that any CPB completions after
			   this point in the handler will raise another interrupt. */
			writew(status, mmio + NV_ADMA_STAT);
			readw(mmio + NV_ADMA_STAT); /* flush posted write */
			rmb();

987 988 989 990 991
			handled++; /* irq handled if we got here */

			/* freeze if hotplugged or controller error */
			if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
					       NV_ADMA_STAT_HOTUNPLUG |
992 993
					       NV_ADMA_STAT_TIMEOUT |
					       NV_ADMA_STAT_SERROR))) {
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				struct ata_eh_info *ehi = &ap->link.eh_info;
995 996

				ata_ehi_clear_desc(ehi);
997
				__ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status);
998 999
				if (status & NV_ADMA_STAT_TIMEOUT) {
					ehi->err_mask |= AC_ERR_SYSTEM;
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					ata_ehi_push_desc(ehi, "timeout");
1001 1002
				} else if (status & NV_ADMA_STAT_HOTPLUG) {
					ata_ehi_hotplugged(ehi);
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					ata_ehi_push_desc(ehi, "hotplug");
1004 1005
				} else if (status & NV_ADMA_STAT_HOTUNPLUG) {
					ata_ehi_hotplugged(ehi);
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					ata_ehi_push_desc(ehi, "hot unplug");
1007 1008
				} else if (status & NV_ADMA_STAT_SERROR) {
					/* let libata analyze SError and figure out the cause */
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					ata_ehi_push_desc(ehi, "SError");
				} else
					ata_ehi_push_desc(ehi, "unknown");
1012 1013 1014 1015
				ata_port_freeze(ap);
				continue;
			}

1016
			if (status & (NV_ADMA_STAT_DONE |
1017 1018 1019
				      NV_ADMA_STAT_CPBERR |
				      NV_ADMA_STAT_CMD_COMPLETE)) {
				u32 check_commands = notifier_clears[i];
1020
				int pos, error = 0;
1021

1022 1023 1024 1025 1026 1027 1028 1029 1030
				if (status & NV_ADMA_STAT_CPBERR) {
					/* Check all active commands */
					if (ata_tag_valid(ap->link.active_tag))
						check_commands = 1 <<
							ap->link.active_tag;
					else
						check_commands = ap->
							link.sactive;
				}
1031

1032
				/** Check CPBs for completed commands */
1033 1034 1035
				while ((pos = ffs(check_commands)) && !error) {
					pos--;
					error = nv_adma_check_cpb(ap, pos,
1036 1037
						notifier_error & (1 << pos));
					check_commands &= ~(1 << pos);
1038 1039 1040 1041
				}
			}
		}
	}
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1042

1043
	if (notifier_clears[0] || notifier_clears[1]) {
1044 1045
		/* Note: Both notifier clear registers must be written
		   if either is set, even if one is zero, according to NVIDIA. */
1046 1047 1048 1049
		struct nv_adma_port_priv *pp = host->ports[0]->private_data;
		writel(notifier_clears[0], pp->notifier_clear_block);
		pp = host->ports[1]->private_data;
		writel(notifier_clears[1], pp->notifier_clear_block);
1050
	}
1051 1052 1053 1054 1055 1056

	spin_unlock(&host->lock);

	return IRQ_RETVAL(handled);
}

1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
static void nv_adma_freeze(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	nv_ck804_freeze(ap);

	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
		return;

	/* clear any outstanding CK804 notifications */
1069
	writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
1070 1071 1072 1073
		ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);

	/* Disable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
1074
	writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
1075
		mmio + NV_ADMA_CTL);
1076
	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091
}

static void nv_adma_thaw(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	nv_ck804_thaw(ap);

	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
		return;

	/* Enable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
1092
	writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
1093
		mmio + NV_ADMA_CTL);
1094
	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
1095 1096
}

1097 1098
static void nv_adma_irq_clear(struct ata_port *ap)
{
1099 1100
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
1101
	u32 notifier_clears[2];
1102

1103 1104 1105 1106 1107 1108
	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
		ata_bmdma_irq_clear(ap);
		return;
	}

	/* clear any outstanding CK804 notifications */
1109
	writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
1110
		ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
1111

1112 1113
	/* clear ADMA status */
	writew(0xffff, mmio + NV_ADMA_STAT);
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1114

1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127
	/* clear notifiers - note both ports need to be written with
	   something even though we are only clearing on one */
	if (ap->port_no == 0) {
		notifier_clears[0] = 0xFFFFFFFF;
		notifier_clears[1] = 0;
	} else {
		notifier_clears[0] = 0;
		notifier_clears[1] = 0xFFFFFFFF;
	}
	pp = ap->host->ports[0]->private_data;
	writel(notifier_clears[0], pp->notifier_clear_block);
	pp = ap->host->ports[1]->private_data;
	writel(notifier_clears[1], pp->notifier_clear_block);
1128 1129
}

1130
static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
1131
{
1132
	struct nv_adma_port_priv *pp = qc->ap->private_data;
1133

1134
	if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
1135
		ata_bmdma_post_internal_cmd(qc);
1136 1137 1138 1139 1140 1141 1142 1143 1144
}

static int nv_adma_port_start(struct ata_port *ap)
{
	struct device *dev = ap->host->dev;
	struct nv_adma_port_priv *pp;
	int rc;
	void *mem;
	dma_addr_t mem_dma;
1145
	void __iomem *mmio;
1146
	struct pci_dev *pdev = to_pci_dev(dev);
1147 1148 1149 1150
	u16 tmp;

	VPRINTK("ENTER\n");

1151 1152 1153 1154 1155 1156 1157 1158 1159
	/* Ensure DMA mask is set to 32-bit before allocating legacy PRD and
	   pad buffers */
	rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (rc)
		return rc;

1160 1161 1162 1163
	rc = ata_port_start(ap);
	if (rc)
		return rc;

1164 1165 1166
	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
	if (!pp)
		return -ENOMEM;
1167

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	mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
1169 1170
	       ap->port_no * NV_ADMA_PORT_SIZE;
	pp->ctl_block = mmio;
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	pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
1172 1173 1174
	pp->notifier_clear_block = pp->gen_block +
	       NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);

1175 1176 1177 1178 1179 1180 1181 1182 1183
	/* Now that the legacy PRD and padding buffer are allocated we can
	   safely raise the DMA mask to allocate the CPB/APRD table.
	   These are allowed to fail since we store the value that ends up
	   being used to set as the bounce limit in slave_config later if
	   needed. */
	pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
	pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
	pp->adma_dma_mask = *dev->dma_mask;

1184 1185 1186 1187
	mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
				  &mem_dma, GFP_KERNEL);
	if (!mem)
		return -ENOMEM;
1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198
	memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);

	/*
	 * First item in chunk of DMA memory:
	 * 128-byte command parameter block (CPB)
	 * one for each command tag
	 */
	pp->cpb     = mem;
	pp->cpb_dma = mem_dma;

	writel(mem_dma & 0xFFFFFFFF, 	mmio + NV_ADMA_CPB_BASE_LOW);
1199
	writel((mem_dma >> 16) >> 16,	mmio + NV_ADMA_CPB_BASE_HIGH);
1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220

	mem     += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
	mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;

	/*
	 * Second item: block of ADMA_SGTBL_LEN s/g entries
	 */
	pp->aprd = mem;
	pp->aprd_dma = mem_dma;

	ap->private_data = pp;

	/* clear any outstanding interrupt conditions */
	writew(0xffff, mmio + NV_ADMA_STAT);

	/* initialize port variables */
	pp->flags = NV_ADMA_PORT_REGISTER_MODE;

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

1221
	/* clear GO for register mode, enable interrupt */
1222
	tmp = readw(mmio + NV_ADMA_CTL);
1223 1224
	writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
1225 1226 1227

	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1228
	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
1229 1230
	udelay(1);
	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1231
	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
1232 1233 1234 1235 1236 1237 1238

	return 0;
}

static void nv_adma_port_stop(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
1239
	void __iomem *mmio = pp->ctl_block;
1240 1241 1242 1243 1244

	VPRINTK("ENTER\n");
	writew(0, mmio + NV_ADMA_CTL);
}

1245
#ifdef CONFIG_PM
1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270
static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;

	/* Go to register mode - clears GO */
	nv_adma_register_mode(ap);

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

	/* disable interrupt, shut down port */
	writew(0, mmio + NV_ADMA_CTL);

	return 0;
}

static int nv_adma_port_resume(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	/* set CPB block location */
	writel(pp->cpb_dma & 0xFFFFFFFF, 	mmio + NV_ADMA_CPB_BASE_LOW);
1271
	writel((pp->cpb_dma >> 16) >> 16,	mmio + NV_ADMA_CPB_BASE_HIGH);
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283

	/* clear any outstanding interrupt conditions */
	writew(0xffff, mmio + NV_ADMA_STAT);

	/* initialize port variables */
	pp->flags |= NV_ADMA_PORT_REGISTER_MODE;

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

	/* clear GO for register mode, enable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
1284 1285
	writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
1286 1287 1288

	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1289
	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
1290 1291
	udelay(1);
	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1292
	readw(mmio + NV_ADMA_CTL);	/* flush posted write */
1293 1294 1295

	return 0;
}
1296
#endif
1297

1298
static void nv_adma_setup_port(struct ata_port *ap)
1299
{
1300 1301
	void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
	struct ata_ioports *ioport = &ap->ioaddr;
1302 1303 1304

	VPRINTK("ENTER\n");

1305
	mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
1306

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	ioport->cmd_addr	= mmio;
	ioport->data_addr	= mmio + (ATA_REG_DATA * 4);
1309
	ioport->error_addr	=
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1310 1311 1312 1313 1314 1315
	ioport->feature_addr	= mmio + (ATA_REG_ERR * 4);
	ioport->nsect_addr	= mmio + (ATA_REG_NSECT * 4);
	ioport->lbal_addr	= mmio + (ATA_REG_LBAL * 4);
	ioport->lbam_addr	= mmio + (ATA_REG_LBAM * 4);
	ioport->lbah_addr	= mmio + (ATA_REG_LBAH * 4);
	ioport->device_addr	= mmio + (ATA_REG_DEVICE * 4);
1316
	ioport->status_addr	=
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1317
	ioport->command_addr	= mmio + (ATA_REG_STATUS * 4);
1318
	ioport->altstatus_addr	=
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1319
	ioport->ctl_addr	= mmio + 0x20;
1320 1321
}

1322
static int nv_adma_host_init(struct ata_host *host)
1323
{
1324
	struct pci_dev *pdev = to_pci_dev(host->dev);
1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338
	unsigned int i;
	u32 tmp32;

	VPRINTK("ENTER\n");

	/* enable ADMA on the ports */
	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
	tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
		 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
		 NV_MCP_SATA_CFG_20_PORT1_EN |
		 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;

	pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);

1339 1340
	for (i = 0; i < host->n_ports; i++)
		nv_adma_setup_port(host->ports[i]);
1341 1342 1343 1344 1345 1346 1347 1348 1349

	return 0;
}

static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
			      struct scatterlist *sg,
			      int idx,
			      struct nv_adma_prd *aprd)
{
1350
	u8 flags = 0;
1351 1352 1353 1354 1355 1356 1357 1358 1359
	if (qc->tf.flags & ATA_TFLAG_WRITE)
		flags |= NV_APRD_WRITE;
	if (idx == qc->n_elem - 1)
		flags |= NV_APRD_END;
	else if (idx != 4)
		flags |= NV_APRD_CONT;

	aprd->addr  = cpu_to_le64(((u64)sg_dma_address(sg)));
	aprd->len   = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
1360
	aprd->flags = flags;
1361
	aprd->packet_len = 0;
1362 1363 1364 1365 1366 1367 1368
}

static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	struct nv_adma_prd *aprd;
	struct scatterlist *sg;
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	unsigned int si;
1370 1371 1372

	VPRINTK("ENTER\n");

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1373 1374 1375 1376
	for_each_sg(qc->sg, sg, qc->n_elem, si) {
		aprd = (si < 5) ? &cpb->aprd[si] :
			       &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)];
		nv_adma_fill_aprd(qc, sg, si, aprd);
1377
	}
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	if (si > 5)
1379
		cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
1380 1381
	else
		cpb->next_aprd = cpu_to_le64(0);
1382 1383
}

1384 1385 1386 1387 1388
static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;

	/* ADMA engine can only be used for non-ATAPI DMA commands,
1389
	   or interrupt-driven no-data commands. */
1390
	if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
1391
	   (qc->tf.flags & ATA_TFLAG_POLLING))
1392 1393
		return 1;

1394
	if ((qc->flags & ATA_QCFLAG_DMAMAP) ||
1395 1396 1397 1398 1399 1400
	   (qc->tf.protocol == ATA_PROT_NODATA))
		return 0;

	return 1;
}

1401 1402 1403 1404 1405 1406 1407
static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
	u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
		       NV_CPB_CTL_IEN;

1408
	if (nv_adma_use_reg_mode(qc)) {
1409 1410
		BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
			(qc->flags & ATA_QCFLAG_DMAMAP));
1411
		nv_adma_register_mode(qc->ap);
1412 1413 1414 1415
		ata_qc_prep(qc);
		return;
	}

1416 1417 1418 1419
	cpb->resp_flags = NV_CPB_RESP_DONE;
	wmb();
	cpb->ctl_flags = 0;
	wmb();
1420 1421 1422 1423 1424 1425 1426 1427 1428

	cpb->len		= 3;
	cpb->tag		= qc->tag;
	cpb->next_cpb_idx	= 0;

	/* turn on NCQ flags for NCQ commands */
	if (qc->tf.protocol == ATA_PROT_NCQ)
		ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;

1429 1430
	VPRINTK("qc->flags = 0x%lx\n", qc->flags);

1431 1432
	nv_adma_tf_to_cpb(&qc->tf, cpb->tf);

1433
	if (qc->flags & ATA_QCFLAG_DMAMAP) {
1434 1435 1436 1437
		nv_adma_fill_sg(qc, cpb);
		ctl_flags |= NV_CPB_CTL_APRD_VALID;
	} else
		memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
1438

1439 1440
	/* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID
	   until we are finished filling in all of the contents */
1441 1442
	wmb();
	cpb->ctl_flags = ctl_flags;
1443 1444
	wmb();
	cpb->resp_flags = 0;
1445 1446 1447 1448
}

static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
{
1449
	struct nv_adma_port_priv *pp = qc->ap->private_data;
1450
	void __iomem *mmio = pp->ctl_block;
1451
	int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
1452 1453 1454

	VPRINTK("ENTER\n");

1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
	/* We can't handle result taskfile with NCQ commands, since
	   retrieving the taskfile switches us out of ADMA mode and would abort
	   existing commands. */
	if (unlikely(qc->tf.protocol == ATA_PROT_NCQ &&
		     (qc->flags & ATA_QCFLAG_RESULT_TF))) {
		ata_dev_printk(qc->dev, KERN_ERR,
			"NCQ w/ RESULT_TF not allowed\n");
		return AC_ERR_SYSTEM;
	}

1465
	if (nv_adma_use_reg_mode(qc)) {
1466
		/* use ATA register mode */
1467
		VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
1468 1469
		BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
			(qc->flags & ATA_QCFLAG_DMAMAP));
1470 1471 1472 1473 1474 1475 1476 1477
		nv_adma_register_mode(qc->ap);
		return ata_qc_issue_prot(qc);
	} else
		nv_adma_mode(qc->ap);

	/* write append register, command tag in lower 8 bits
	   and (number of cpbs to append -1) in top 8 bits */
	wmb();
1478

1479
	if (curr_ncq != pp->last_issue_ncq) {
1480 1481
		/* Seems to need some delay before switching between NCQ and
		   non-NCQ commands, else we get command timeouts and such. */
1482 1483 1484 1485
		udelay(20);
		pp->last_issue_ncq = curr_ncq;
	}

1486 1487
	writew(qc->tag, mmio + NV_ADMA_APPEND);

1488
	DPRINTK("Issued tag %u\n", qc->tag);
1489 1490 1491 1492

	return 0;
}

1493
static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
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{
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	struct ata_host *host = dev_instance;
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	unsigned int i;
	unsigned int handled = 0;
	unsigned long flags;

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	spin_lock_irqsave(&host->lock, flags);
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	for (i = 0; i < host->n_ports; i++) {
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		struct ata_port *ap;

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		ap = host->ports[i];
1506
		if (ap &&
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		    !(ap->flags & ATA_FLAG_DISABLED)) {
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			struct ata_queued_cmd *qc;

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			qc = ata_qc_from_tag(ap, ap->link.active_tag);
1511
			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
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				handled += ata_host_intr(ap, qc);
1513 1514 1515 1516
			else
				// No request pending?  Clear interrupt status
				// anyway, in case there's one pending.
				ap->ops->check_status(ap);
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		}

	}

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	spin_unlock_irqrestore(&host->lock, flags);
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	return IRQ_RETVAL(handled);
}

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static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
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{
	int i, handled = 0;

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	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
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		if (ap && !(ap->flags & ATA_FLAG_DISABLED))
			handled += nv_host_intr(ap, irq_stat);

		irq_stat >>= NV_INT_PORT_SHIFT;
	}

	return IRQ_RETVAL(handled);
}

1542
static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
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{
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	struct ata_host *host = dev_instance;
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	u8 irq_stat;
	irqreturn_t ret;

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	spin_lock(&host->lock);
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	irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
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	ret = nv_do_interrupt(host, irq_stat);
	spin_unlock(&host->lock);
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	return ret;
}

1556
static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
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{
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	struct ata_host *host = dev_instance;
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	u8 irq_stat;
	irqreturn_t ret;

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	spin_lock(&host->lock);
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	irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
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	ret = nv_do_interrupt(host, irq_stat);
	spin_unlock(&host->lock);
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	return ret;
}

1570
static int nv_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
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1571 1572
{
	if (sc_reg > SCR_CONTROL)
1573
		return -EINVAL;
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1575 1576
	*val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
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}

1579
static int nv_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
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1580 1581
{
	if (sc_reg > SCR_CONTROL)
1582
		return -EINVAL;
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	iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
1585
	return 0;
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}

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static void nv_nf2_freeze(struct ata_port *ap)
{
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	void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
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	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

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	mask = ioread8(scr_addr + NV_INT_ENABLE);
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	mask &= ~(NV_INT_ALL << shift);
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	iowrite8(mask, scr_addr + NV_INT_ENABLE);
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}

static void nv_nf2_thaw(struct ata_port *ap)
{
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	void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
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	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

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	iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
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	mask = ioread8(scr_addr + NV_INT_ENABLE);
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	mask |= (NV_INT_MASK << shift);
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	iowrite8(mask, scr_addr + NV_INT_ENABLE);
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}

static void nv_ck804_freeze(struct ata_port *ap)
{
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	void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
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	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

	mask = readb(mmio_base + NV_INT_ENABLE_CK804);
	mask &= ~(NV_INT_ALL << shift);
	writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
}

static void nv_ck804_thaw(struct ata_port *ap)
{
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	void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
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	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

	writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);

	mask = readb(mmio_base + NV_INT_ENABLE_CK804);
	mask |= (NV_INT_MASK << shift);
	writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
}

1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663
static void nv_mcp55_freeze(struct ata_port *ap)
{
	void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
	int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
	u32 mask;

	writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);

	mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
	mask &= ~(NV_INT_ALL_MCP55 << shift);
	writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
	ata_bmdma_freeze(ap);
}

static void nv_mcp55_thaw(struct ata_port *ap)
{
	void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
	int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
	u32 mask;

	writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);

	mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
	mask |= (NV_INT_MASK_MCP55 << shift);
	writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
	ata_bmdma_thaw(ap);
}

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static int nv_hardreset(struct ata_link *link, unsigned int *class,
1665
			unsigned long deadline)
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{
	unsigned int dummy;

	/* SATA hardreset fails to retrieve proper device signature on
	 * some controllers.  Don't classify on hardreset.  For more
1671
	 * info, see http://bugzilla.kernel.org/show_bug.cgi?id=3352
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	 */
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	return sata_std_hardreset(link, &dummy, deadline);
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}

static void nv_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
			   nv_hardreset, ata_std_postreset);
}

1682 1683 1684
static void nv_adma_error_handler(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
1685
	if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
1686
		void __iomem *mmio = pp->ctl_block;
1687 1688
		int i;
		u16 tmp;
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1690
		if (ata_tag_valid(ap->link.active_tag) || ap->link.sactive) {
1691 1692 1693 1694
			u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
			u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
			u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
			u32 status = readw(mmio + NV_ADMA_STAT);
1695 1696
			u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
			u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
1697

1698 1699
			ata_port_printk(ap, KERN_ERR,
				"EH in ADMA mode, notifier 0x%X "
1700 1701 1702 1703
				"notifier_error 0x%X gen_ctl 0x%X status 0x%X "
				"next cpb count 0x%X next cpb idx 0x%x\n",
				notifier, notifier_error, gen_ctl, status,
				cpb_count, next_cpb_idx);
1704

1705
			for (i = 0; i < NV_ADMA_MAX_CPBS; i++) {
1706
				struct nv_adma_cpb *cpb = &pp->cpb[i];
1707
				if ((ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) ||
1708
				    ap->link.sactive & (1 << i))
1709 1710 1711 1712 1713
					ata_port_printk(ap, KERN_ERR,
						"CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
						i, cpb->ctl_flags, cpb->resp_flags);
			}
		}
1714 1715 1716 1717

		/* Push us back into port register mode for error handling. */
		nv_adma_register_mode(ap);

1718 1719
		/* Mark all of the CPBs as invalid to prevent them from
		   being executed */
1720
		for (i = 0; i < NV_ADMA_MAX_CPBS; i++)
1721 1722 1723 1724 1725 1726 1727 1728
			pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;

		/* clear CPB fetch count */
		writew(0, mmio + NV_ADMA_CPB_COUNT);

		/* Reset channel */
		tmp = readw(mmio + NV_ADMA_CTL);
		writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1729
		readw(mmio + NV_ADMA_CTL);	/* flush posted write */
1730 1731
		udelay(1);
		writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1732
		readw(mmio + NV_ADMA_CTL);	/* flush posted write */
1733 1734 1735 1736 1737 1738
	}

	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
			   nv_hardreset, ata_std_postreset);
}

1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858
static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
{
	struct nv_swncq_port_priv *pp = ap->private_data;
	struct defer_queue *dq = &pp->defer_queue;

	/* queue is full */
	WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE);
	dq->defer_bits |= (1 << qc->tag);
	dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag;
}

static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap)
{
	struct nv_swncq_port_priv *pp = ap->private_data;
	struct defer_queue *dq = &pp->defer_queue;
	unsigned int tag;

	if (dq->head == dq->tail)	/* null queue */
		return NULL;

	tag = dq->tag[dq->head & (ATA_MAX_QUEUE - 1)];
	dq->tag[dq->head++ & (ATA_MAX_QUEUE - 1)] = ATA_TAG_POISON;
	WARN_ON(!(dq->defer_bits & (1 << tag)));
	dq->defer_bits &= ~(1 << tag);

	return ata_qc_from_tag(ap, tag);
}

static void nv_swncq_fis_reinit(struct ata_port *ap)
{
	struct nv_swncq_port_priv *pp = ap->private_data;

	pp->dhfis_bits = 0;
	pp->dmafis_bits = 0;
	pp->sdbfis_bits = 0;
	pp->ncq_flags = 0;
}

static void nv_swncq_pp_reinit(struct ata_port *ap)
{
	struct nv_swncq_port_priv *pp = ap->private_data;
	struct defer_queue *dq = &pp->defer_queue;

	dq->head = 0;
	dq->tail = 0;
	dq->defer_bits = 0;
	pp->qc_active = 0;
	pp->last_issue_tag = ATA_TAG_POISON;
	nv_swncq_fis_reinit(ap);
}

static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis)
{
	struct nv_swncq_port_priv *pp = ap->private_data;

	writew(fis, pp->irq_block);
}

static void __ata_bmdma_stop(struct ata_port *ap)
{
	struct ata_queued_cmd qc;

	qc.ap = ap;
	ata_bmdma_stop(&qc);
}

static void nv_swncq_ncq_stop(struct ata_port *ap)
{
	struct nv_swncq_port_priv *pp = ap->private_data;
	unsigned int i;
	u32 sactive;
	u32 done_mask;

	ata_port_printk(ap, KERN_ERR,
			"EH in SWNCQ mode,QC:qc_active 0x%X sactive 0x%X\n",
			ap->qc_active, ap->link.sactive);
	ata_port_printk(ap, KERN_ERR,
		"SWNCQ:qc_active 0x%X defer_bits 0x%X last_issue_tag 0x%x\n  "
		"dhfis 0x%X dmafis 0x%X sdbfis 0x%X\n",
		pp->qc_active, pp->defer_queue.defer_bits, pp->last_issue_tag,
		pp->dhfis_bits, pp->dmafis_bits, pp->sdbfis_bits);

	ata_port_printk(ap, KERN_ERR, "ATA_REG 0x%X ERR_REG 0x%X\n",
			ap->ops->check_status(ap),
			ioread8(ap->ioaddr.error_addr));

	sactive = readl(pp->sactive_block);
	done_mask = pp->qc_active ^ sactive;

	ata_port_printk(ap, KERN_ERR, "tag : dhfis dmafis sdbfis sacitve\n");
	for (i = 0; i < ATA_MAX_QUEUE; i++) {
		u8 err = 0;
		if (pp->qc_active & (1 << i))
			err = 0;
		else if (done_mask & (1 << i))
			err = 1;
		else
			continue;

		ata_port_printk(ap, KERN_ERR,
				"tag 0x%x: %01x %01x %01x %01x %s\n", i,
				(pp->dhfis_bits >> i) & 0x1,
				(pp->dmafis_bits >> i) & 0x1,
				(pp->sdbfis_bits >> i) & 0x1,
				(sactive >> i) & 0x1,
				(err ? "error! tag doesn't exit" : " "));
	}

	nv_swncq_pp_reinit(ap);
	ap->ops->irq_clear(ap);
	__ata_bmdma_stop(ap);
	nv_swncq_irq_clear(ap, 0xffff);
}

static void nv_swncq_error_handler(struct ata_port *ap)
{
	struct ata_eh_context *ehc = &ap->link.eh_context;

	if (ap->link.sactive) {
		nv_swncq_ncq_stop(ap);
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		ehc->i.action |= ATA_EH_RESET;
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	}

	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
			   nv_hardreset, ata_std_postreset);
}

#ifdef CONFIG_PM
static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg)
{
	void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
	u32 tmp;

	/* clear irq */
	writel(~0, mmio + NV_INT_STATUS_MCP55);

	/* disable irq */
	writel(0, mmio + NV_INT_ENABLE_MCP55);

	/* disable swncq */
	tmp = readl(mmio + NV_CTL_MCP55);
	tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ);
	writel(tmp, mmio + NV_CTL_MCP55);

	return 0;
}

static int nv_swncq_port_resume(struct ata_port *ap)
{
	void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
	u32 tmp;

	/* clear irq */
	writel(~0, mmio + NV_INT_STATUS_MCP55);

	/* enable irq */
	writel(0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);

	/* enable swncq */
	tmp = readl(mmio + NV_CTL_MCP55);
	writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);

	return 0;
}
#endif

static void nv_swncq_host_init(struct ata_host *host)
{
	u32 tmp;
	void __iomem *mmio = host->iomap[NV_MMIO_BAR];
	struct pci_dev *pdev = to_pci_dev(host->dev);
	u8 regval;

	/* disable  ECO 398 */
	pci_read_config_byte(pdev, 0x7f, &regval);
	regval &= ~(1 << 7);
	pci_write_config_byte(pdev, 0x7f, regval);

	/* enable swncq */
	tmp = readl(mmio + NV_CTL_MCP55);
	VPRINTK("HOST_CTL:0x%X\n", tmp);
	writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);

	/* enable irq intr */
	tmp = readl(mmio + NV_INT_ENABLE_MCP55);
	VPRINTK("HOST_ENABLE:0x%X\n", tmp);
	writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);

	/*  clear port irq */
	writel(~0x0, mmio + NV_INT_STATUS_MCP55);
}

static int nv_swncq_slave_config(struct scsi_device *sdev)
{
	struct ata_port *ap = ata_shost_to_port(sdev->host);
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_device *dev;
	int rc;
	u8 rev;
	u8 check_maxtor = 0;
	unsigned char model_num[ATA_ID_PROD_LEN + 1];

	rc = ata_scsi_slave_config(sdev);
	if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
		/* Not a proper libata device, ignore */
		return rc;

	dev = &ap->link.device[sdev->id];
	if (!(ap->flags & ATA_FLAG_NCQ) || dev->class == ATA_DEV_ATAPI)
		return rc;

	/* if MCP51 and Maxtor, then disable ncq */
	if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA ||
		pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2)
		check_maxtor = 1;

	/* if MCP55 and rev <= a2 and Maxtor, then disable ncq */
	if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA ||
		pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2) {
		pci_read_config_byte(pdev, 0x8, &rev);
		if (rev <= 0xa2)
			check_maxtor = 1;
	}

	if (!check_maxtor)
		return rc;

	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	if (strncmp(model_num, "Maxtor", 6) == 0) {
		ata_scsi_change_queue_depth(sdev, 1);
		ata_dev_printk(dev, KERN_NOTICE,
			"Disabling SWNCQ mode (depth %x)\n", sdev->queue_depth);
	}

	return rc;
}

static int nv_swncq_port_start(struct ata_port *ap)
{
	struct device *dev = ap->host->dev;
	void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
	struct nv_swncq_port_priv *pp;
	int rc;

	rc = ata_port_start(ap);
	if (rc)
		return rc;

	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
	if (!pp)
		return -ENOMEM;

	pp->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE,
				      &pp->prd_dma, GFP_KERNEL);
	if (!pp->prd)
		return -ENOMEM;
	memset(pp->prd, 0, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE);

	ap->private_data = pp;
	pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE;
	pp->irq_block = mmio + NV_INT_STATUS_MCP55 + ap->port_no * 2;
	pp->tag_block = mmio + NV_NCQ_REG_MCP55 + ap->port_no * 2;

	return 0;
}

static void nv_swncq_qc_prep(struct ata_queued_cmd *qc)
{
	if (qc->tf.protocol != ATA_PROT_NCQ) {
		ata_qc_prep(qc);
		return;
	}

	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
		return;

	nv_swncq_fill_sg(qc);
}

static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct scatterlist *sg;
	struct nv_swncq_port_priv *pp = ap->private_data;
	struct ata_prd *prd;
T
Tejun Heo 已提交
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	unsigned int si, idx;
2026 2027 2028 2029

	prd = pp->prd + ATA_MAX_PRD * qc->tag;

	idx = 0;
T
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	for_each_sg(qc->sg, sg, qc->n_elem, si) {
2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051
		u32 addr, offset;
		u32 sg_len, len;

		addr = (u32)sg_dma_address(sg);
		sg_len = sg_dma_len(sg);

		while (sg_len) {
			offset = addr & 0xffff;
			len = sg_len;
			if ((offset + sg_len) > 0x10000)
				len = 0x10000 - offset;

			prd[idx].addr = cpu_to_le32(addr);
			prd[idx].flags_len = cpu_to_le32(len & 0xffff);

			idx++;
			sg_len -= len;
			addr += len;
		}
	}

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	prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139
}

static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap,
					  struct ata_queued_cmd *qc)
{
	struct nv_swncq_port_priv *pp = ap->private_data;

	if (qc == NULL)
		return 0;

	DPRINTK("Enter\n");

	writel((1 << qc->tag), pp->sactive_block);
	pp->last_issue_tag = qc->tag;
	pp->dhfis_bits &= ~(1 << qc->tag);
	pp->dmafis_bits &= ~(1 << qc->tag);
	pp->qc_active |= (0x1 << qc->tag);

	ap->ops->tf_load(ap, &qc->tf);	 /* load tf registers */
	ap->ops->exec_command(ap, &qc->tf);

	DPRINTK("Issued tag %u\n", qc->tag);

	return 0;
}

static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct nv_swncq_port_priv *pp = ap->private_data;

	if (qc->tf.protocol != ATA_PROT_NCQ)
		return ata_qc_issue_prot(qc);

	DPRINTK("Enter\n");

	if (!pp->qc_active)
		nv_swncq_issue_atacmd(ap, qc);
	else
		nv_swncq_qc_to_dq(ap, qc);	/* add qc to defer queue */

	return 0;
}

static void nv_swncq_hotplug(struct ata_port *ap, u32 fis)
{
	u32 serror;
	struct ata_eh_info *ehi = &ap->link.eh_info;

	ata_ehi_clear_desc(ehi);

	/* AHCI needs SError cleared; otherwise, it might lock up */
	sata_scr_read(&ap->link, SCR_ERROR, &serror);
	sata_scr_write(&ap->link, SCR_ERROR, serror);

	/* analyze @irq_stat */
	if (fis & NV_SWNCQ_IRQ_ADDED)
		ata_ehi_push_desc(ehi, "hot plug");
	else if (fis & NV_SWNCQ_IRQ_REMOVED)
		ata_ehi_push_desc(ehi, "hot unplug");

	ata_ehi_hotplugged(ehi);

	/* okay, let's hand over to EH */
	ehi->serror |= serror;

	ata_port_freeze(ap);
}

static int nv_swncq_sdbfis(struct ata_port *ap)
{
	struct ata_queued_cmd *qc;
	struct nv_swncq_port_priv *pp = ap->private_data;
	struct ata_eh_info *ehi = &ap->link.eh_info;
	u32 sactive;
	int nr_done = 0;
	u32 done_mask;
	int i;
	u8 host_stat;
	u8 lack_dhfis = 0;

	host_stat = ap->ops->bmdma_status(ap);
	if (unlikely(host_stat & ATA_DMA_ERR)) {
		/* error when transfering data to/from memory */
		ata_ehi_clear_desc(ehi);
		ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
		ehi->err_mask |= AC_ERR_HOST_BUS;
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		ehi->action |= ATA_EH_RESET;
2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154
		return -EINVAL;
	}

	ap->ops->irq_clear(ap);
	__ata_bmdma_stop(ap);

	sactive = readl(pp->sactive_block);
	done_mask = pp->qc_active ^ sactive;

	if (unlikely(done_mask & sactive)) {
		ata_ehi_clear_desc(ehi);
		ata_ehi_push_desc(ehi, "illegal SWNCQ:qc_active transition"
				  "(%08x->%08x)", pp->qc_active, sactive);
		ehi->err_mask |= AC_ERR_HSM;
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		ehi->action |= ATA_EH_RESET;
2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290
		return -EINVAL;
	}
	for (i = 0; i < ATA_MAX_QUEUE; i++) {
		if (!(done_mask & (1 << i)))
			continue;

		qc = ata_qc_from_tag(ap, i);
		if (qc) {
			ata_qc_complete(qc);
			pp->qc_active &= ~(1 << i);
			pp->dhfis_bits &= ~(1 << i);
			pp->dmafis_bits &= ~(1 << i);
			pp->sdbfis_bits |= (1 << i);
			nr_done++;
		}
	}

	if (!ap->qc_active) {
		DPRINTK("over\n");
		nv_swncq_pp_reinit(ap);
		return nr_done;
	}

	if (pp->qc_active & pp->dhfis_bits)
		return nr_done;

	if ((pp->ncq_flags & ncq_saw_backout) ||
	    (pp->qc_active ^ pp->dhfis_bits))
		/* if the controller cann't get a device to host register FIS,
		 * The driver needs to reissue the new command.
		 */
		lack_dhfis = 1;

	DPRINTK("id 0x%x QC: qc_active 0x%x,"
		"SWNCQ:qc_active 0x%X defer_bits %X "
		"dhfis 0x%X dmafis 0x%X last_issue_tag %x\n",
		ap->print_id, ap->qc_active, pp->qc_active,
		pp->defer_queue.defer_bits, pp->dhfis_bits,
		pp->dmafis_bits, pp->last_issue_tag);

	nv_swncq_fis_reinit(ap);

	if (lack_dhfis) {
		qc = ata_qc_from_tag(ap, pp->last_issue_tag);
		nv_swncq_issue_atacmd(ap, qc);
		return nr_done;
	}

	if (pp->defer_queue.defer_bits) {
		/* send deferral queue command */
		qc = nv_swncq_qc_from_dq(ap);
		WARN_ON(qc == NULL);
		nv_swncq_issue_atacmd(ap, qc);
	}

	return nr_done;
}

static inline u32 nv_swncq_tag(struct ata_port *ap)
{
	struct nv_swncq_port_priv *pp = ap->private_data;
	u32 tag;

	tag = readb(pp->tag_block) >> 2;
	return (tag & 0x1f);
}

static int nv_swncq_dmafis(struct ata_port *ap)
{
	struct ata_queued_cmd *qc;
	unsigned int rw;
	u8 dmactl;
	u32 tag;
	struct nv_swncq_port_priv *pp = ap->private_data;

	__ata_bmdma_stop(ap);
	tag = nv_swncq_tag(ap);

	DPRINTK("dma setup tag 0x%x\n", tag);
	qc = ata_qc_from_tag(ap, tag);

	if (unlikely(!qc))
		return 0;

	rw = qc->tf.flags & ATA_TFLAG_WRITE;

	/* load PRD table addr. */
	iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag,
		  ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
	dmactl &= ~ATA_DMA_WR;
	if (!rw)
		dmactl |= ATA_DMA_WR;

	iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);

	return 1;
}

static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
{
	struct nv_swncq_port_priv *pp = ap->private_data;
	struct ata_queued_cmd *qc;
	struct ata_eh_info *ehi = &ap->link.eh_info;
	u32 serror;
	u8 ata_stat;
	int rc = 0;

	ata_stat = ap->ops->check_status(ap);
	nv_swncq_irq_clear(ap, fis);
	if (!fis)
		return;

	if (ap->pflags & ATA_PFLAG_FROZEN)
		return;

	if (fis & NV_SWNCQ_IRQ_HOTPLUG) {
		nv_swncq_hotplug(ap, fis);
		return;
	}

	if (!pp->qc_active)
		return;

	if (ap->ops->scr_read(ap, SCR_ERROR, &serror))
		return;
	ap->ops->scr_write(ap, SCR_ERROR, serror);

	if (ata_stat & ATA_ERR) {
		ata_ehi_clear_desc(ehi);
		ata_ehi_push_desc(ehi, "Ata error. fis:0x%X", fis);
		ehi->err_mask |= AC_ERR_DEV;
		ehi->serror |= serror;
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		ehi->action |= ATA_EH_RESET;
2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322
		ata_port_freeze(ap);
		return;
	}

	if (fis & NV_SWNCQ_IRQ_BACKOUT) {
		/* If the IRQ is backout, driver must issue
		 * the new command again some time later.
		 */
		pp->ncq_flags |= ncq_saw_backout;
	}

	if (fis & NV_SWNCQ_IRQ_SDBFIS) {
		pp->ncq_flags |= ncq_saw_sdb;
		DPRINTK("id 0x%x SWNCQ: qc_active 0x%X "
			"dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
			ap->print_id, pp->qc_active, pp->dhfis_bits,
			pp->dmafis_bits, readl(pp->sactive_block));
		rc = nv_swncq_sdbfis(ap);
		if (rc < 0)
			goto irq_error;
	}

	if (fis & NV_SWNCQ_IRQ_DHREGFIS) {
		/* The interrupt indicates the new command
		 * was transmitted correctly to the drive.
		 */
		pp->dhfis_bits |= (0x1 << pp->last_issue_tag);
		pp->ncq_flags |= ncq_saw_d2h;
		if (pp->ncq_flags & (ncq_saw_sdb | ncq_saw_backout)) {
			ata_ehi_push_desc(ehi, "illegal fis transaction");
			ehi->err_mask |= AC_ERR_HSM;
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			ehi->action |= ATA_EH_RESET;
2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391
			goto irq_error;
		}

		if (!(fis & NV_SWNCQ_IRQ_DMASETUP) &&
		    !(pp->ncq_flags & ncq_saw_dmas)) {
			ata_stat = ap->ops->check_status(ap);
			if (ata_stat & ATA_BUSY)
				goto irq_exit;

			if (pp->defer_queue.defer_bits) {
				DPRINTK("send next command\n");
				qc = nv_swncq_qc_from_dq(ap);
				nv_swncq_issue_atacmd(ap, qc);
			}
		}
	}

	if (fis & NV_SWNCQ_IRQ_DMASETUP) {
		/* program the dma controller with appropriate PRD buffers
		 * and start the DMA transfer for requested command.
		 */
		pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
		pp->ncq_flags |= ncq_saw_dmas;
		rc = nv_swncq_dmafis(ap);
	}

irq_exit:
	return;
irq_error:
	ata_ehi_push_desc(ehi, "fis:0x%x", fis);
	ata_port_freeze(ap);
	return;
}

static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	unsigned long flags;
	u32 irq_stat;

	spin_lock_irqsave(&host->lock, flags);

	irq_stat = readl(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_MCP55);

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];

		if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
			if (ap->link.sactive) {
				nv_swncq_host_interrupt(ap, (u16)irq_stat);
				handled = 1;
			} else {
				if (irq_stat)	/* reserve Hotplug */
					nv_swncq_irq_clear(ap, 0xfff0);

				handled += nv_host_intr(ap, (u8)irq_stat);
			}
		}
		irq_stat >>= NV_INT_PORT_SHIFT_MCP55;
	}

	spin_unlock_irqrestore(&host->lock, flags);

	return IRQ_RETVAL(handled);
}

2392
static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
L
Linus Torvalds 已提交
2393
{
2394
	static int printed_version;
T
Tejun Heo 已提交
2395
	const struct ata_port_info *ppi[] = { NULL, NULL };
2396
	struct ata_host *host;
2397
	struct nv_host_priv *hpriv;
L
Linus Torvalds 已提交
2398 2399
	int rc;
	u32 bar;
T
Tejun Heo 已提交
2400
	void __iomem *base;
2401
	unsigned long type = ent->driver_data;
L
Linus Torvalds 已提交
2402 2403 2404 2405

        // Make sure this is a SATA controller by counting the number of bars
        // (NVIDIA SATA controllers will always have six bars).  Otherwise,
        // it's an IDE controller and we ignore it.
2406
	for (bar = 0; bar < 6; bar++)
L
Linus Torvalds 已提交
2407 2408 2409
		if (pci_resource_start(pdev, bar) == 0)
			return -ENODEV;

2410
	if (!printed_version++)
2411
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
L
Linus Torvalds 已提交
2412

2413
	rc = pcim_enable_device(pdev);
L
Linus Torvalds 已提交
2414
	if (rc)
2415
		return rc;
L
Linus Torvalds 已提交
2416

2417
	/* determine type and allocate host */
2418
	if (type == CK804 && adma_enabled) {
2419 2420 2421 2422
		dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
		type = ADMA;
	}

J
Jeff Garzik 已提交
2423 2424 2425 2426 2427 2428 2429 2430
	if (type == SWNCQ) {
		if (swncq_enabled)
			dev_printk(KERN_NOTICE, &pdev->dev,
				   "Using SWNCQ mode\n");
		else
			type = GENERIC;
	}

T
Tejun Heo 已提交
2431
	ppi[0] = &nv_port_info[type];
2432
	rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
2433 2434
	if (rc)
		return rc;
L
Linus Torvalds 已提交
2435

2436
	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2437
	if (!hpriv)
2438
		return -ENOMEM;
2439 2440
	hpriv->type = type;
	host->private_data = hpriv;
2441

2442 2443 2444 2445
	/* request and iomap NV_MMIO_BAR */
	rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
	if (rc)
		return rc;
L
Linus Torvalds 已提交
2446

2447 2448 2449 2450
	/* configure SCR access */
	base = host->iomap[NV_MMIO_BAR];
	host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
	host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
L
Linus Torvalds 已提交
2451

T
Tejun Heo 已提交
2452
	/* enable SATA space for CK804 */
2453
	if (type >= CK804) {
T
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2454 2455 2456 2457 2458 2459 2460
		u8 regval;

		pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
		regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
		pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
	}

2461
	/* init ADMA */
2462
	if (type == ADMA) {
2463
		rc = nv_adma_host_init(host);
2464
		if (rc)
2465
			return rc;
J
Jeff Garzik 已提交
2466
	} else if (type == SWNCQ)
2467
		nv_swncq_host_init(host);
2468

2469 2470 2471
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler,
				 IRQF_SHARED, ppi[0]->sht);
L
Linus Torvalds 已提交
2472 2473
}

2474
#ifdef CONFIG_PM
2475 2476 2477 2478
static int nv_pci_device_resume(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct nv_host_priv *hpriv = host->private_data;
2479
	int rc;
2480

2481
	rc = ata_pci_device_do_resume(pdev);
2482
	if (rc)
2483
		return rc;
2484 2485

	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2486
		if (hpriv->type >= CK804) {
2487 2488 2489 2490 2491 2492
			u8 regval;

			pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
			regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
			pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
		}
2493
		if (hpriv->type == ADMA) {
2494 2495 2496 2497 2498 2499
			u32 tmp32;
			struct nv_adma_port_priv *pp;
			/* enable/disable ADMA on the ports appropriately */
			pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);

			pp = host->ports[0]->private_data;
2500
			if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
2501
				tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
2502
					   NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
2503 2504
			else
				tmp32 |=  (NV_MCP_SATA_CFG_20_PORT0_EN |
2505
					   NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
2506
			pp = host->ports[1]->private_data;
2507
			if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
2508
				tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
2509
					   NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
2510 2511
			else
				tmp32 |=  (NV_MCP_SATA_CFG_20_PORT1_EN |
2512
					   NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
2513 2514 2515 2516 2517 2518 2519 2520 2521

			pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
		}
	}

	ata_host_resume(host);

	return 0;
}
2522
#endif
2523

J
Jeff Garzik 已提交
2524
static void nv_ck804_host_stop(struct ata_host *host)
T
Tejun Heo 已提交
2525
{
J
Jeff Garzik 已提交
2526
	struct pci_dev *pdev = to_pci_dev(host->dev);
T
Tejun Heo 已提交
2527 2528 2529 2530 2531 2532 2533 2534
	u8 regval;

	/* disable SATA space for CK804 */
	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
}

2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551
static void nv_adma_host_stop(struct ata_host *host)
{
	struct pci_dev *pdev = to_pci_dev(host->dev);
	u32 tmp32;

	/* disable ADMA on the ports */
	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
	tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
		   NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
		   NV_MCP_SATA_CFG_20_PORT1_EN |
		   NV_MCP_SATA_CFG_20_PORT1_PWB_EN);

	pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);

	nv_ck804_host_stop(host);
}

L
Linus Torvalds 已提交
2552 2553
static int __init nv_init(void)
{
2554
	return pci_register_driver(&nv_pci_driver);
L
Linus Torvalds 已提交
2555 2556 2557 2558 2559 2560 2561 2562 2563
}

static void __exit nv_exit(void)
{
	pci_unregister_driver(&nv_pci_driver);
}

module_init(nv_init);
module_exit(nv_exit);
2564 2565
module_param_named(adma, adma_enabled, bool, 0444);
MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");
2566 2567 2568
module_param_named(swncq, swncq_enabled, bool, 0444);
MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: false)");