sata_nv.c 47.8 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3 4 5 6
/*
 *  sata_nv.c - NVIDIA nForce SATA
 *
 *  Copyright 2004 NVIDIA Corp.  All rights reserved.
 *  Copyright 2004 Andrew Chew
 *
7 8 9 10 11 12 13 14 15 16 17 18 19 20
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
L
Linus Torvalds 已提交
21
 *
22 23 24 25 26 27 28 29 30 31
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  No hardware documentation available outside of NVIDIA.
 *  This driver programs the NVIDIA SATA controller in a similar
 *  fashion as with other PCI IDE BMDMA controllers, with a few
 *  NV-specific details such as register offsets, SATA phy location,
 *  hotplug info, etc.
 *
32 33 34 35 36
 *  CK804/MCP04 controllers support an alternate programming interface
 *  similar to the ADMA specification (with some modifications).
 *  This allows the use of NCQ. Non-DMA-mapped ATA commands are still
 *  sent through the legacy interface.
 *
L
Linus Torvalds 已提交
37 38 39 40 41 42 43 44 45
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
46
#include <linux/device.h>
L
Linus Torvalds 已提交
47
#include <scsi/scsi_host.h>
48
#include <scsi/scsi_device.h>
L
Linus Torvalds 已提交
49 50 51
#include <linux/libata.h>

#define DRV_NAME			"sata_nv"
J
Jeff Garzik 已提交
52
#define DRV_VERSION			"3.5"
53 54

#define NV_ADMA_DMA_BOUNDARY		0xffffffffUL
L
Linus Torvalds 已提交
55

56
enum {
T
Tejun Heo 已提交
57 58
	NV_MMIO_BAR			= 5,

59 60 61 62 63 64
	NV_PORTS			= 2,
	NV_PIO_MASK			= 0x1f,
	NV_MWDMA_MASK			= 0x07,
	NV_UDMA_MASK			= 0x7f,
	NV_PORT0_SCR_REG_OFFSET		= 0x00,
	NV_PORT1_SCR_REG_OFFSET		= 0x40,
L
Linus Torvalds 已提交
65

T
Tejun Heo 已提交
66
	/* INT_STATUS/ENABLE */
67 68
	NV_INT_STATUS			= 0x10,
	NV_INT_ENABLE			= 0x11,
T
Tejun Heo 已提交
69
	NV_INT_STATUS_CK804		= 0x440,
70
	NV_INT_ENABLE_CK804		= 0x441,
L
Linus Torvalds 已提交
71

T
Tejun Heo 已提交
72 73 74 75 76 77 78 79
	/* INT_STATUS/ENABLE bits */
	NV_INT_DEV			= 0x01,
	NV_INT_PM			= 0x02,
	NV_INT_ADDED			= 0x04,
	NV_INT_REMOVED			= 0x08,

	NV_INT_PORT_SHIFT		= 4,	/* each port occupies 4 bits */

T
Tejun Heo 已提交
80
	NV_INT_ALL			= 0x0f,
T
Tejun Heo 已提交
81 82
	NV_INT_MASK			= NV_INT_DEV |
					  NV_INT_ADDED | NV_INT_REMOVED,
T
Tejun Heo 已提交
83

T
Tejun Heo 已提交
84
	/* INT_CONFIG */
85 86
	NV_INT_CONFIG			= 0x12,
	NV_INT_CONFIG_METHD		= 0x01, // 0 = INT, 1 = SMI
L
Linus Torvalds 已提交
87

88 89 90
	// For PCI config register 20
	NV_MCP_SATA_CFG_20		= 0x50,
	NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169
	NV_MCP_SATA_CFG_20_PORT0_EN	= (1 << 17),
	NV_MCP_SATA_CFG_20_PORT1_EN	= (1 << 16),
	NV_MCP_SATA_CFG_20_PORT0_PWB_EN	= (1 << 14),
	NV_MCP_SATA_CFG_20_PORT1_PWB_EN	= (1 << 12),

	NV_ADMA_MAX_CPBS		= 32,
	NV_ADMA_CPB_SZ			= 128,
	NV_ADMA_APRD_SZ			= 16,
	NV_ADMA_SGTBL_LEN		= (1024 - NV_ADMA_CPB_SZ) /
					   NV_ADMA_APRD_SZ,
	NV_ADMA_SGTBL_TOTAL_LEN		= NV_ADMA_SGTBL_LEN + 5,
	NV_ADMA_SGTBL_SZ                = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
	NV_ADMA_PORT_PRIV_DMA_SZ        = NV_ADMA_MAX_CPBS *
					   (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),

	/* BAR5 offset to ADMA general registers */
	NV_ADMA_GEN			= 0x400,
	NV_ADMA_GEN_CTL			= 0x00,
	NV_ADMA_NOTIFIER_CLEAR		= 0x30,

	/* BAR5 offset to ADMA ports */
	NV_ADMA_PORT			= 0x480,

	/* size of ADMA port register space  */
	NV_ADMA_PORT_SIZE		= 0x100,

	/* ADMA port registers */
	NV_ADMA_CTL			= 0x40,
	NV_ADMA_CPB_COUNT		= 0x42,
	NV_ADMA_NEXT_CPB_IDX		= 0x43,
	NV_ADMA_STAT			= 0x44,
	NV_ADMA_CPB_BASE_LOW		= 0x48,
	NV_ADMA_CPB_BASE_HIGH		= 0x4C,
	NV_ADMA_APPEND			= 0x50,
	NV_ADMA_NOTIFIER		= 0x68,
	NV_ADMA_NOTIFIER_ERROR		= 0x6C,

	/* NV_ADMA_CTL register bits */
	NV_ADMA_CTL_HOTPLUG_IEN		= (1 << 0),
	NV_ADMA_CTL_CHANNEL_RESET	= (1 << 5),
	NV_ADMA_CTL_GO			= (1 << 7),
	NV_ADMA_CTL_AIEN		= (1 << 8),
	NV_ADMA_CTL_READ_NON_COHERENT	= (1 << 11),
	NV_ADMA_CTL_WRITE_NON_COHERENT	= (1 << 12),

	/* CPB response flag bits */
	NV_CPB_RESP_DONE		= (1 << 0),
	NV_CPB_RESP_ATA_ERR		= (1 << 3),
	NV_CPB_RESP_CMD_ERR		= (1 << 4),
	NV_CPB_RESP_CPB_ERR		= (1 << 7),

	/* CPB control flag bits */
	NV_CPB_CTL_CPB_VALID		= (1 << 0),
	NV_CPB_CTL_QUEUE		= (1 << 1),
	NV_CPB_CTL_APRD_VALID		= (1 << 2),
	NV_CPB_CTL_IEN			= (1 << 3),
	NV_CPB_CTL_FPDMA		= (1 << 4),

	/* APRD flags */
	NV_APRD_WRITE			= (1 << 1),
	NV_APRD_END			= (1 << 2),
	NV_APRD_CONT			= (1 << 3),

	/* NV_ADMA_STAT flags */
	NV_ADMA_STAT_TIMEOUT		= (1 << 0),
	NV_ADMA_STAT_HOTUNPLUG		= (1 << 1),
	NV_ADMA_STAT_HOTPLUG		= (1 << 2),
	NV_ADMA_STAT_CPBERR		= (1 << 4),
	NV_ADMA_STAT_SERROR		= (1 << 5),
	NV_ADMA_STAT_CMD_COMPLETE	= (1 << 6),
	NV_ADMA_STAT_IDLE		= (1 << 8),
	NV_ADMA_STAT_LEGACY		= (1 << 9),
	NV_ADMA_STAT_STOPPED		= (1 << 10),
	NV_ADMA_STAT_DONE		= (1 << 12),
	NV_ADMA_STAT_ERR		= NV_ADMA_STAT_CPBERR |
	 				  NV_ADMA_STAT_TIMEOUT,

	/* port flags */
	NV_ADMA_PORT_REGISTER_MODE	= (1 << 0),
170
	NV_ADMA_ATAPI_SETUP_COMPLETE	= (1 << 1),
171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209

};

/* ADMA Physical Region Descriptor - one SG segment */
struct nv_adma_prd {
	__le64			addr;
	__le32			len;
	u8			flags;
	u8			packet_len;
	__le16			reserved;
};

enum nv_adma_regbits {
	CMDEND	= (1 << 15),		/* end of command list */
	WNB	= (1 << 14),		/* wait-not-BSY */
	IGN	= (1 << 13),		/* ignore this entry */
	CS1n	= (1 << (4 + 8)),	/* std. PATA signals follow... */
	DA2	= (1 << (2 + 8)),
	DA1	= (1 << (1 + 8)),
	DA0	= (1 << (0 + 8)),
};

/* ADMA Command Parameter Block
   The first 5 SG segments are stored inside the Command Parameter Block itself.
   If there are more than 5 segments the remainder are stored in a separate
   memory area indicated by next_aprd. */
struct nv_adma_cpb {
	u8			resp_flags;    /* 0 */
	u8			reserved1;     /* 1 */
	u8			ctl_flags;     /* 2 */
	/* len is length of taskfile in 64 bit words */
 	u8			len;           /* 3  */
	u8			tag;           /* 4 */
	u8			next_cpb_idx;  /* 5 */
	__le16			reserved2;     /* 6-7 */
	__le16			tf[12];        /* 8-31 */
	struct nv_adma_prd	aprd[5];       /* 32-111 */
	__le64			next_aprd;     /* 112-119 */
	__le64			reserved3;     /* 120-127 */
210
};
L
Linus Torvalds 已提交
211

212 213 214 215 216 217

struct nv_adma_port_priv {
	struct nv_adma_cpb	*cpb;
	dma_addr_t		cpb_dma;
	struct nv_adma_prd	*aprd;
	dma_addr_t		aprd_dma;
218 219 220
	void __iomem *		ctl_block;
	void __iomem *		gen_block;
	void __iomem *		notifier_clear_block;
221
	u8			flags;
222
	int			last_issue_ncq;
223 224
};

225 226 227 228
struct nv_host_priv {
	unsigned long		type;
};

229 230
#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))

L
Linus Torvalds 已提交
231
static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
232
#ifdef CONFIG_PM
233
static int nv_pci_device_resume(struct pci_dev *pdev);
234
#endif
J
Jeff Garzik 已提交
235
static void nv_ck804_host_stop(struct ata_host *host);
236 237 238
static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
239 240
static int nv_scr_read (struct ata_port *ap, unsigned int sc_reg, u32 *val);
static int nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
L
Linus Torvalds 已提交
241

T
Tejun Heo 已提交
242 243 244 245 246
static void nv_nf2_freeze(struct ata_port *ap);
static void nv_nf2_thaw(struct ata_port *ap);
static void nv_ck804_freeze(struct ata_port *ap);
static void nv_ck804_thaw(struct ata_port *ap);
static void nv_error_handler(struct ata_port *ap);
247
static int nv_adma_slave_config(struct scsi_device *sdev);
248
static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
249 250 251 252 253 254
static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
static void nv_adma_irq_clear(struct ata_port *ap);
static int nv_adma_port_start(struct ata_port *ap);
static void nv_adma_port_stop(struct ata_port *ap);
255
#ifdef CONFIG_PM
256 257
static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int nv_adma_port_resume(struct ata_port *ap);
258
#endif
259 260
static void nv_adma_freeze(struct ata_port *ap);
static void nv_adma_thaw(struct ata_port *ap);
261 262
static void nv_adma_error_handler(struct ata_port *ap);
static void nv_adma_host_stop(struct ata_host *host);
263
static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
264
static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
T
Tejun Heo 已提交
265

L
Linus Torvalds 已提交
266 267 268 269
enum nv_host_type
{
	GENERIC,
	NFORCE2,
T
Tejun Heo 已提交
270
	NFORCE3 = NFORCE2,	/* NF2 == NF3 as far as sata_nv is concerned */
271 272
	CK804,
	ADMA
L
Linus Torvalds 已提交
273 274
};

275
static const struct pci_device_id nv_pci_tbl[] = {
276 277 278 279 280 281 282 283 284 285 286 287 288 289
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
	{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
290 291

	{ } /* terminate list */
L
Linus Torvalds 已提交
292 293 294 295 296 297
};

static struct pci_driver nv_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= nv_pci_tbl,
	.probe			= nv_init_one,
298
#ifdef CONFIG_PM
299 300
	.suspend		= ata_pci_device_suspend,
	.resume			= nv_pci_device_resume,
301
#endif
302
	.remove			= ata_pci_remove_one,
L
Linus Torvalds 已提交
303 304
};

305
static struct scsi_host_template nv_sht = {
L
Linus Torvalds 已提交
306 307 308 309 310 311 312 313 314 315 316 317 318
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
T
Tejun Heo 已提交
319
	.slave_destroy		= ata_scsi_slave_destroy,
L
Linus Torvalds 已提交
320 321 322
	.bios_param		= ata_std_bios_param,
};

323 324 325 326 327
static struct scsi_host_template nv_adma_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
328
	.change_queue_depth	= ata_scsi_change_queue_depth,
329 330 331 332 333 334 335 336 337 338 339 340 341
	.can_queue		= NV_ADMA_MAX_CPBS,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= NV_ADMA_SGTBL_TOTAL_LEN,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= NV_ADMA_DMA_BOUNDARY,
	.slave_configure	= nv_adma_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

T
Tejun Heo 已提交
342
static const struct ata_port_operations nv_generic_ops = {
L
Linus Torvalds 已提交
343 344 345 346 347 348 349 350 351 352 353 354
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
T
Tejun Heo 已提交
355 356 357 358
	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
T
Tejun Heo 已提交
359
	.data_xfer		= ata_data_xfer,
L
Linus Torvalds 已提交
360
	.irq_clear		= ata_bmdma_irq_clear,
361 362
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
L
Linus Torvalds 已提交
363 364 365 366 367
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= ata_port_start,
};

T
Tejun Heo 已提交
368 369 370 371 372 373 374 375 376 377 378 379 380
static const struct ata_port_operations nv_nf2_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
T
Tejun Heo 已提交
381 382 383 384
	.freeze			= nv_nf2_freeze,
	.thaw			= nv_nf2_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
T
Tejun Heo 已提交
385
	.data_xfer		= ata_data_xfer,
T
Tejun Heo 已提交
386
	.irq_clear		= ata_bmdma_irq_clear,
387 388
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
T
Tejun Heo 已提交
389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= ata_port_start,
};

static const struct ata_port_operations nv_ck804_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
T
Tejun Heo 已提交
407 408 409 410
	.freeze			= nv_ck804_freeze,
	.thaw			= nv_ck804_thaw,
	.error_handler		= nv_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
T
Tejun Heo 已提交
411
	.data_xfer		= ata_data_xfer,
T
Tejun Heo 已提交
412
	.irq_clear		= ata_bmdma_irq_clear,
413 414
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
T
Tejun Heo 已提交
415 416 417 418 419 420
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= ata_port_start,
	.host_stop		= nv_ck804_host_stop,
};

421 422 423
static const struct ata_port_operations nv_adma_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
424
	.tf_read		= nv_adma_tf_read,
425
	.check_atapi_dma	= nv_adma_check_atapi_dma,
426 427 428
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,
429 430 431 432
	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
433 434
	.qc_prep		= nv_adma_qc_prep,
	.qc_issue		= nv_adma_qc_issue,
435 436
	.freeze			= nv_adma_freeze,
	.thaw			= nv_adma_thaw,
437
	.error_handler		= nv_adma_error_handler,
438
	.post_internal_cmd	= nv_adma_post_internal_cmd,
T
Tejun Heo 已提交
439
	.data_xfer		= ata_data_xfer,
440
	.irq_clear		= nv_adma_irq_clear,
441 442
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
443 444 445 446
	.scr_read		= nv_scr_read,
	.scr_write		= nv_scr_write,
	.port_start		= nv_adma_port_start,
	.port_stop		= nv_adma_port_stop,
447
#ifdef CONFIG_PM
448 449
	.port_suspend		= nv_adma_port_suspend,
	.port_resume		= nv_adma_port_resume,
450
#endif
451 452 453
	.host_stop		= nv_adma_host_stop,
};

T
Tejun Heo 已提交
454
static const struct ata_port_info nv_port_info[] = {
T
Tejun Heo 已提交
455 456 457
	/* generic */
	{
		.sht		= &nv_sht,
458 459
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_HRST_TO_RESUME,
T
Tejun Heo 已提交
460 461 462 463
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_generic_ops,
464
		.irq_handler	= nv_generic_interrupt,
T
Tejun Heo 已提交
465 466 467 468
	},
	/* nforce2/3 */
	{
		.sht		= &nv_sht,
469 470
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_HRST_TO_RESUME,
T
Tejun Heo 已提交
471 472 473 474
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_nf2_ops,
475
		.irq_handler	= nv_nf2_interrupt,
T
Tejun Heo 已提交
476 477 478 479
	},
	/* ck804 */
	{
		.sht		= &nv_sht,
480 481
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_HRST_TO_RESUME,
T
Tejun Heo 已提交
482 483 484 485
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_ck804_ops,
486
		.irq_handler	= nv_ck804_interrupt,
T
Tejun Heo 已提交
487
	},
488 489 490 491
	/* ADMA */
	{
		.sht		= &nv_adma_sht,
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
492
				  ATA_FLAG_HRST_TO_RESUME |
493 494 495 496 497
				  ATA_FLAG_MMIO | ATA_FLAG_NCQ,
		.pio_mask	= NV_PIO_MASK,
		.mwdma_mask	= NV_MWDMA_MASK,
		.udma_mask	= NV_UDMA_MASK,
		.port_ops	= &nv_adma_ops,
498
		.irq_handler	= nv_adma_interrupt,
499
	},
L
Linus Torvalds 已提交
500 501 502 503 504 505 506 507
};

MODULE_AUTHOR("NVIDIA");
MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
MODULE_VERSION(DRV_VERSION);

508 509
static int adma_enabled = 1;

510 511 512
static void nv_adma_register_mode(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
513
	void __iomem *mmio = pp->ctl_block;
514 515
	u16 tmp, status;
	int count = 0;
516 517 518 519

	if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
		return;

520 521 522 523 524 525 526 527 528 529 530
	status = readw(mmio + NV_ADMA_STAT);
	while(!(status & NV_ADMA_STAT_IDLE) && count < 20) {
		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
	if(count == 20)
		ata_port_printk(ap, KERN_WARNING,
			"timeout waiting for ADMA IDLE, stat=0x%hx\n",
			status);

531 532 533
	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);

534 535 536 537 538 539 540 541 542 543 544 545
	count = 0;
	status = readw(mmio + NV_ADMA_STAT);
	while(!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
	if(count == 20)
		ata_port_printk(ap, KERN_WARNING,
			 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
			 status);

546 547 548 549 550 551
	pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
}

static void nv_adma_mode(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
552
	void __iomem *mmio = pp->ctl_block;
553 554
	u16 tmp, status;
	int count = 0;
555 556 557

	if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
		return;
J
Jeff Garzik 已提交
558

559 560 561 562 563
	WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);

	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);

564 565 566 567 568 569 570 571 572 573 574 575
	status = readw(mmio + NV_ADMA_STAT);
	while(((status & NV_ADMA_STAT_LEGACY) ||
	      !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
		ndelay(50);
		status = readw(mmio + NV_ADMA_STAT);
		count++;
	}
	if(count == 20)
		ata_port_printk(ap, KERN_WARNING,
			"timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
			status);

576 577 578
	pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
}

579 580 581
static int nv_adma_slave_config(struct scsi_device *sdev)
{
	struct ata_port *ap = ata_shost_to_port(sdev->host);
582 583
	struct nv_adma_port_priv *pp = ap->private_data;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
584 585 586 587
	u64 bounce_limit;
	unsigned long segment_boundary;
	unsigned short sg_tablesize;
	int rc;
588 589
	int adma_enable;
	u32 current_reg, new_reg, config_mask;
590 591 592 593 594 595 596

	rc = ata_scsi_slave_config(sdev);

	if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
		/* Not a proper libata device, ignore */
		return rc;

T
Tejun Heo 已提交
597
	if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) {
598 599 600 601 602 603 604 605 606 607 608 609
		/*
		 * NVIDIA reports that ADMA mode does not support ATAPI commands.
		 * Therefore ATAPI commands are sent through the legacy interface.
		 * However, the legacy interface only supports 32-bit DMA.
		 * Restrict DMA parameters as required by the legacy interface
		 * when an ATAPI device is connected.
		 */
		bounce_limit = ATA_DMA_MASK;
		segment_boundary = ATA_DMA_BOUNDARY;
		/* Subtract 1 since an extra entry may be needed for padding, see
		   libata-scsi.c */
		sg_tablesize = LIBATA_MAX_PRD - 1;
J
Jeff Garzik 已提交
610

611 612 613 614
		/* Since the legacy DMA engine is in use, we need to disable ADMA
		   on the port. */
		adma_enable = 0;
		nv_adma_register_mode(ap);
615 616 617 618 619
	}
	else {
		bounce_limit = *ap->dev->dma_mask;
		segment_boundary = NV_ADMA_DMA_BOUNDARY;
		sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
620
		adma_enable = 1;
621
	}
J
Jeff Garzik 已提交
622

623 624 625 626 627 628 629 630
	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);

	if(ap->port_no == 1)
		config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
			      NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
	else
		config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
			      NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
J
Jeff Garzik 已提交
631

632 633 634 635 636 637 638 639
	if(adma_enable) {
		new_reg = current_reg | config_mask;
		pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
	}
	else {
		new_reg = current_reg & ~config_mask;
		pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
	}
J
Jeff Garzik 已提交
640

641 642
	if(current_reg != new_reg)
		pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
J
Jeff Garzik 已提交
643

644 645 646 647 648 649 650 651 652
	blk_queue_bounce_limit(sdev->request_queue, bounce_limit);
	blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
	blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize);
	ata_port_printk(ap, KERN_INFO,
		"bounce limit 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
		(unsigned long long)bounce_limit, segment_boundary, sg_tablesize);
	return rc;
}

653 654 655 656 657 658
static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
}

659 660 661 662 663 664 665 666 667 668 669 670
static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	/* Since commands where a result TF is requested are not
	   executed in ADMA mode, the only time this function will be called
	   in ADMA mode will be if a command fails. In this case we
	   don't care about going into register mode with ADMA commands
	   pending, as the commands will all shortly be aborted anyway. */
	nv_adma_register_mode(ap);

	ata_tf_read(ap, tf);
}

671
static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
672 673 674
{
	unsigned int idx = 0;

R
Robert Hancock 已提交
675 676 677 678 679 680 681 682 683 684
	if(tf->flags & ATA_TFLAG_ISADDR) {
		if (tf->flags & ATA_TFLAG_LBA48) {
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR   << 8) | tf->hob_feature | WNB);
			cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAL  << 8) | tf->hob_lbal);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAM  << 8) | tf->hob_lbam);
			cpb[idx++] = cpu_to_le16((ATA_REG_LBAH  << 8) | tf->hob_lbah);
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR    << 8) | tf->feature);
		} else
			cpb[idx++] = cpu_to_le16((ATA_REG_ERR    << 8) | tf->feature | WNB);
J
Jeff Garzik 已提交
685

R
Robert Hancock 已提交
686 687 688 689
		cpb[idx++] = cpu_to_le16((ATA_REG_NSECT  << 8) | tf->nsect);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAL   << 8) | tf->lbal);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAM   << 8) | tf->lbam);
		cpb[idx++] = cpu_to_le16((ATA_REG_LBAH   << 8) | tf->lbah);
690
	}
J
Jeff Garzik 已提交
691

R
Robert Hancock 已提交
692 693
	if(tf->flags & ATA_TFLAG_DEVICE)
		cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
694 695

	cpb[idx++] = cpu_to_le16((ATA_REG_CMD    << 8) | tf->command | CMDEND);
J
Jeff Garzik 已提交
696

R
Robert Hancock 已提交
697 698
	while(idx < 12)
		cpb[idx++] = cpu_to_le16(IGN);
699 700 701 702

	return idx;
}

703
static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
704 705
{
	struct nv_adma_port_priv *pp = ap->private_data;
706
	u8 flags = pp->cpb[cpb_num].resp_flags;
707 708 709

	VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);

710 711 712 713
	if (unlikely((force_err ||
		     flags & (NV_CPB_RESP_ATA_ERR |
			      NV_CPB_RESP_CMD_ERR |
			      NV_CPB_RESP_CPB_ERR)))) {
T
Tejun Heo 已提交
714
		struct ata_eh_info *ehi = &ap->link.eh_info;
715 716 717
		int freeze = 0;

		ata_ehi_clear_desc(ehi);
T
Tejun Heo 已提交
718
		__ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags );
719
		if (flags & NV_CPB_RESP_ATA_ERR) {
T
Tejun Heo 已提交
720
			ata_ehi_push_desc(ehi, "ATA error");
721 722
			ehi->err_mask |= AC_ERR_DEV;
		} else if (flags & NV_CPB_RESP_CMD_ERR) {
T
Tejun Heo 已提交
723
			ata_ehi_push_desc(ehi, "CMD error");
724 725
			ehi->err_mask |= AC_ERR_DEV;
		} else if (flags & NV_CPB_RESP_CPB_ERR) {
T
Tejun Heo 已提交
726
			ata_ehi_push_desc(ehi, "CPB error");
727 728 729 730
			ehi->err_mask |= AC_ERR_SYSTEM;
			freeze = 1;
		} else {
			/* notifier error, but no error in CPB flags? */
T
Tejun Heo 已提交
731
			ata_ehi_push_desc(ehi, "unknown");
732 733 734 735 736 737 738 739 740
			ehi->err_mask |= AC_ERR_OTHER;
			freeze = 1;
		}
		/* Kill all commands. EH will determine what actually failed. */
		if (freeze)
			ata_port_freeze(ap);
		else
			ata_port_abort(ap);
		return 1;
741
	}
742

743
	if (likely(flags & NV_CPB_RESP_DONE)) {
744
		struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
745 746
		VPRINTK("CPB flags done, flags=0x%x\n", flags);
		if (likely(qc)) {
747
			DPRINTK("Completing qc from tag %d\n",cpb_num);
748
			ata_qc_complete(qc);
749
		} else {
T
Tejun Heo 已提交
750
			struct ata_eh_info *ehi = &ap->link.eh_info;
751 752 753 754 755 756 757 758 759
			/* Notifier bits set without a command may indicate the drive
			   is misbehaving. Raise host state machine violation on this
			   condition. */
			ata_port_printk(ap, KERN_ERR, "notifier for tag %d with no command?\n",
				cpb_num);
			ehi->err_mask |= AC_ERR_HSM;
			ehi->action |= ATA_EH_SOFTRESET;
			ata_port_freeze(ap);
			return 1;
760 761
		}
	}
762
	return 0;
763 764
}

765 766
static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
{
T
Tejun Heo 已提交
767
	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785

	/* freeze if hotplugged */
	if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
		ata_port_freeze(ap);
		return 1;
	}

	/* bail out if not our interrupt */
	if (!(irq_stat & NV_INT_DEV))
		return 0;

	/* DEV interrupt w/ no active qc? */
	if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
		ata_check_status(ap);
		return 1;
	}

	/* handle interrupt */
786
	return ata_host_intr(ap, qc);
787 788
}

789 790 791 792
static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	int i, handled = 0;
793
	u32 notifier_clears[2];
794 795 796 797 798

	spin_lock(&host->lock);

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
799
		notifier_clears[i] = 0;
800 801 802

		if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
			struct nv_adma_port_priv *pp = ap->private_data;
803
			void __iomem *mmio = pp->ctl_block;
804 805 806
			u16 status;
			u32 gen_ctl;
			u32 notifier, notifier_error;
J
Jeff Garzik 已提交
807

808 809 810 811 812 813 814
			/* if ADMA is disabled, use standard ata interrupt handler */
			if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
				u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
					>> (NV_INT_PORT_SHIFT * i);
				handled += nv_host_intr(ap, irq_stat);
				continue;
			}
815

816
			/* if in ATA register mode, check for standard interrupts */
817
			if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
T
Tejun Heo 已提交
818
				u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
819
					>> (NV_INT_PORT_SHIFT * i);
T
Tejun Heo 已提交
820
				if(ata_tag_valid(ap->link.active_tag))
821 822 823 824
					/** NV_INT_DEV indication seems unreliable at times
					    at least in ADMA mode. Force it on always when a
					    command is active, to prevent losing interrupts. */
					irq_stat |= NV_INT_DEV;
825
				handled += nv_host_intr(ap, irq_stat);
826 827 828 829
			}

			notifier = readl(mmio + NV_ADMA_NOTIFIER);
			notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
830
			notifier_clears[i] = notifier | notifier_error;
831

832
			gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
833 834 835 836 837 838 839 840 841 842 843 844 845 846 847

			if( !NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
			    !notifier_error)
				/* Nothing to do */
				continue;

			status = readw(mmio + NV_ADMA_STAT);

			/* Clear status. Ensure the controller sees the clearing before we start
			   looking at any of the CPB statuses, so that any CPB completions after
			   this point in the handler will raise another interrupt. */
			writew(status, mmio + NV_ADMA_STAT);
			readw(mmio + NV_ADMA_STAT); /* flush posted write */
			rmb();

848 849 850 851 852
			handled++; /* irq handled if we got here */

			/* freeze if hotplugged or controller error */
			if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
					       NV_ADMA_STAT_HOTUNPLUG |
853 854
					       NV_ADMA_STAT_TIMEOUT |
					       NV_ADMA_STAT_SERROR))) {
T
Tejun Heo 已提交
855
				struct ata_eh_info *ehi = &ap->link.eh_info;
856 857

				ata_ehi_clear_desc(ehi);
T
Tejun Heo 已提交
858
				__ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status );
859 860
				if (status & NV_ADMA_STAT_TIMEOUT) {
					ehi->err_mask |= AC_ERR_SYSTEM;
T
Tejun Heo 已提交
861
					ata_ehi_push_desc(ehi, "timeout");
862 863
				} else if (status & NV_ADMA_STAT_HOTPLUG) {
					ata_ehi_hotplugged(ehi);
T
Tejun Heo 已提交
864
					ata_ehi_push_desc(ehi, "hotplug");
865 866
				} else if (status & NV_ADMA_STAT_HOTUNPLUG) {
					ata_ehi_hotplugged(ehi);
T
Tejun Heo 已提交
867
					ata_ehi_push_desc(ehi, "hot unplug");
868 869
				} else if (status & NV_ADMA_STAT_SERROR) {
					/* let libata analyze SError and figure out the cause */
T
Tejun Heo 已提交
870 871 872
					ata_ehi_push_desc(ehi, "SError");
				} else
					ata_ehi_push_desc(ehi, "unknown");
873 874 875 876
				ata_port_freeze(ap);
				continue;
			}

877 878
			if (status & (NV_ADMA_STAT_DONE |
				      NV_ADMA_STAT_CPBERR)) {
879
				u32 check_commands;
880
				int pos, error = 0;
881

T
Tejun Heo 已提交
882 883
				if(ata_tag_valid(ap->link.active_tag))
					check_commands = 1 << ap->link.active_tag;
884
				else
T
Tejun Heo 已提交
885
					check_commands = ap->link.sactive;
886

887
				/** Check CPBs for completed commands */
888 889 890 891 892
				while ((pos = ffs(check_commands)) && !error) {
					pos--;
					error = nv_adma_check_cpb(ap, pos,
						notifier_error & (1 << pos) );
					check_commands &= ~(1 << pos );
893 894 895 896
				}
			}
		}
	}
J
Jeff Garzik 已提交
897

898 899 900
	if(notifier_clears[0] || notifier_clears[1]) {
		/* Note: Both notifier clear registers must be written
		   if either is set, even if one is zero, according to NVIDIA. */
901 902 903 904
		struct nv_adma_port_priv *pp = host->ports[0]->private_data;
		writel(notifier_clears[0], pp->notifier_clear_block);
		pp = host->ports[1]->private_data;
		writel(notifier_clears[1], pp->notifier_clear_block);
905
	}
906 907 908 909 910 911

	spin_unlock(&host->lock);

	return IRQ_RETVAL(handled);
}

912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951
static void nv_adma_freeze(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	nv_ck804_freeze(ap);

	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
		return;

	/* clear any outstanding CK804 notifications */
	writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
		ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);

	/* Disable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
	writew( tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
		mmio + NV_ADMA_CTL);
	readw( mmio + NV_ADMA_CTL );	/* flush posted write */
}

static void nv_adma_thaw(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	nv_ck804_thaw(ap);

	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
		return;

	/* Enable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
	writew( tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
		mmio + NV_ADMA_CTL);
	readw( mmio + NV_ADMA_CTL );	/* flush posted write */
}

952 953
static void nv_adma_irq_clear(struct ata_port *ap)
{
954 955
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
956
	u32 notifier_clears[2];
957

958 959 960 961 962 963 964 965
	if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
		ata_bmdma_irq_clear(ap);
		return;
	}

	/* clear any outstanding CK804 notifications */
	writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
		ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
966

967 968
	/* clear ADMA status */
	writew(0xffff, mmio + NV_ADMA_STAT);
J
Jeff Garzik 已提交
969

970 971 972 973 974 975 976 977 978 979 980 981 982
	/* clear notifiers - note both ports need to be written with
	   something even though we are only clearing on one */
	if (ap->port_no == 0) {
		notifier_clears[0] = 0xFFFFFFFF;
		notifier_clears[1] = 0;
	} else {
		notifier_clears[0] = 0;
		notifier_clears[1] = 0xFFFFFFFF;
	}
	pp = ap->host->ports[0]->private_data;
	writel(notifier_clears[0], pp->notifier_clear_block);
	pp = ap->host->ports[1]->private_data;
	writel(notifier_clears[1], pp->notifier_clear_block);
983 984
}

985
static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
986
{
987
	struct nv_adma_port_priv *pp = qc->ap->private_data;
988

989 990
	if(pp->flags & NV_ADMA_PORT_REGISTER_MODE)
		ata_bmdma_post_internal_cmd(qc);
991 992 993 994 995 996 997 998 999
}

static int nv_adma_port_start(struct ata_port *ap)
{
	struct device *dev = ap->host->dev;
	struct nv_adma_port_priv *pp;
	int rc;
	void *mem;
	dma_addr_t mem_dma;
1000
	void __iomem *mmio;
1001 1002 1003 1004 1005 1006 1007 1008
	u16 tmp;

	VPRINTK("ENTER\n");

	rc = ata_port_start(ap);
	if (rc)
		return rc;

1009 1010 1011
	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
	if (!pp)
		return -ENOMEM;
1012

T
Tejun Heo 已提交
1013
	mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
1014 1015
	       ap->port_no * NV_ADMA_PORT_SIZE;
	pp->ctl_block = mmio;
T
Tejun Heo 已提交
1016
	pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
1017 1018 1019
	pp->notifier_clear_block = pp->gen_block +
	       NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);

1020 1021 1022 1023
	mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
				  &mem_dma, GFP_KERNEL);
	if (!mem)
		return -ENOMEM;
1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056
	memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);

	/*
	 * First item in chunk of DMA memory:
	 * 128-byte command parameter block (CPB)
	 * one for each command tag
	 */
	pp->cpb     = mem;
	pp->cpb_dma = mem_dma;

	writel(mem_dma & 0xFFFFFFFF, 	mmio + NV_ADMA_CPB_BASE_LOW);
	writel((mem_dma >> 16 ) >> 16,	mmio + NV_ADMA_CPB_BASE_HIGH);

	mem     += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
	mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;

	/*
	 * Second item: block of ADMA_SGTBL_LEN s/g entries
	 */
	pp->aprd = mem;
	pp->aprd_dma = mem_dma;

	ap->private_data = pp;

	/* clear any outstanding interrupt conditions */
	writew(0xffff, mmio + NV_ADMA_STAT);

	/* initialize port variables */
	pp->flags = NV_ADMA_PORT_REGISTER_MODE;

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

1057
	/* clear GO for register mode, enable interrupt */
1058
	tmp = readw(mmio + NV_ADMA_CTL);
1059 1060
	writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
		 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
1061 1062 1063

	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1064
	readw( mmio + NV_ADMA_CTL );	/* flush posted write */
1065 1066
	udelay(1);
	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1067
	readw( mmio + NV_ADMA_CTL );	/* flush posted write */
1068 1069 1070 1071 1072 1073 1074

	return 0;
}

static void nv_adma_port_stop(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
1075
	void __iomem *mmio = pp->ctl_block;
1076 1077 1078 1079 1080

	VPRINTK("ENTER\n");
	writew(0, mmio + NV_ADMA_CTL);
}

1081
#ifdef CONFIG_PM
1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;

	/* Go to register mode - clears GO */
	nv_adma_register_mode(ap);

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

	/* disable interrupt, shut down port */
	writew(0, mmio + NV_ADMA_CTL);

	return 0;
}

static int nv_adma_port_resume(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	void __iomem *mmio = pp->ctl_block;
	u16 tmp;

	/* set CPB block location */
	writel(pp->cpb_dma & 0xFFFFFFFF, 	mmio + NV_ADMA_CPB_BASE_LOW);
	writel((pp->cpb_dma >> 16 ) >> 16,	mmio + NV_ADMA_CPB_BASE_HIGH);

	/* clear any outstanding interrupt conditions */
	writew(0xffff, mmio + NV_ADMA_STAT);

	/* initialize port variables */
	pp->flags |= NV_ADMA_PORT_REGISTER_MODE;

	/* clear CPB fetch count */
	writew(0, mmio + NV_ADMA_CPB_COUNT);

	/* clear GO for register mode, enable interrupt */
	tmp = readw(mmio + NV_ADMA_CTL);
1120 1121
	writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
		 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
1122 1123 1124

	tmp = readw(mmio + NV_ADMA_CTL);
	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1125
	readw( mmio + NV_ADMA_CTL );	/* flush posted write */
1126 1127
	udelay(1);
	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1128
	readw( mmio + NV_ADMA_CTL );	/* flush posted write */
1129 1130 1131

	return 0;
}
1132
#endif
1133

1134
static void nv_adma_setup_port(struct ata_port *ap)
1135
{
1136 1137
	void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
	struct ata_ioports *ioport = &ap->ioaddr;
1138 1139 1140

	VPRINTK("ENTER\n");

1141
	mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
1142

T
Tejun Heo 已提交
1143 1144
	ioport->cmd_addr	= mmio;
	ioport->data_addr	= mmio + (ATA_REG_DATA * 4);
1145
	ioport->error_addr	=
T
Tejun Heo 已提交
1146 1147 1148 1149 1150 1151
	ioport->feature_addr	= mmio + (ATA_REG_ERR * 4);
	ioport->nsect_addr	= mmio + (ATA_REG_NSECT * 4);
	ioport->lbal_addr	= mmio + (ATA_REG_LBAL * 4);
	ioport->lbam_addr	= mmio + (ATA_REG_LBAM * 4);
	ioport->lbah_addr	= mmio + (ATA_REG_LBAH * 4);
	ioport->device_addr	= mmio + (ATA_REG_DEVICE * 4);
1152
	ioport->status_addr	=
T
Tejun Heo 已提交
1153
	ioport->command_addr	= mmio + (ATA_REG_STATUS * 4);
1154
	ioport->altstatus_addr	=
T
Tejun Heo 已提交
1155
	ioport->ctl_addr	= mmio + 0x20;
1156 1157
}

1158
static int nv_adma_host_init(struct ata_host *host)
1159
{
1160
	struct pci_dev *pdev = to_pci_dev(host->dev);
1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174
	unsigned int i;
	u32 tmp32;

	VPRINTK("ENTER\n");

	/* enable ADMA on the ports */
	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
	tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
		 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
		 NV_MCP_SATA_CFG_20_PORT1_EN |
		 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;

	pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);

1175 1176
	for (i = 0; i < host->n_ports; i++)
		nv_adma_setup_port(host->ports[i]);
1177 1178 1179 1180 1181 1182 1183 1184 1185

	return 0;
}

static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
			      struct scatterlist *sg,
			      int idx,
			      struct nv_adma_prd *aprd)
{
1186
	u8 flags = 0;
1187 1188 1189 1190 1191 1192 1193 1194 1195
	if (qc->tf.flags & ATA_TFLAG_WRITE)
		flags |= NV_APRD_WRITE;
	if (idx == qc->n_elem - 1)
		flags |= NV_APRD_END;
	else if (idx != 4)
		flags |= NV_APRD_CONT;

	aprd->addr  = cpu_to_le64(((u64)sg_dma_address(sg)));
	aprd->len   = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
1196
	aprd->flags = flags;
1197
	aprd->packet_len = 0;
1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217
}

static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	unsigned int idx;
	struct nv_adma_prd *aprd;
	struct scatterlist *sg;

	VPRINTK("ENTER\n");

	idx = 0;

	ata_for_each_sg(sg, qc) {
		aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
		nv_adma_fill_aprd(qc, sg, idx, aprd);
		idx++;
	}
	if (idx > 5)
		cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
1218 1219
	else
		cpb->next_aprd = cpu_to_le64(0);
1220 1221
}

1222 1223 1224 1225 1226
static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;

	/* ADMA engine can only be used for non-ATAPI DMA commands,
1227 1228
	   or interrupt-driven no-data commands, where a result taskfile
	   is not required. */
1229
	if((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
1230 1231
	   (qc->tf.flags & ATA_TFLAG_POLLING) ||
	   (qc->flags & ATA_QCFLAG_RESULT_TF))
1232 1233 1234 1235 1236 1237 1238 1239 1240
		return 1;

	if((qc->flags & ATA_QCFLAG_DMAMAP) ||
	   (qc->tf.protocol == ATA_PROT_NODATA))
		return 0;

	return 1;
}

1241 1242 1243 1244 1245 1246 1247
static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
{
	struct nv_adma_port_priv *pp = qc->ap->private_data;
	struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
	u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
		       NV_CPB_CTL_IEN;

1248
	if (nv_adma_use_reg_mode(qc)) {
1249
		nv_adma_register_mode(qc->ap);
1250 1251 1252 1253
		ata_qc_prep(qc);
		return;
	}

1254 1255 1256 1257
	cpb->resp_flags = NV_CPB_RESP_DONE;
	wmb();
	cpb->ctl_flags = 0;
	wmb();
1258 1259 1260 1261 1262 1263 1264 1265 1266

	cpb->len		= 3;
	cpb->tag		= qc->tag;
	cpb->next_cpb_idx	= 0;

	/* turn on NCQ flags for NCQ commands */
	if (qc->tf.protocol == ATA_PROT_NCQ)
		ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;

1267 1268
	VPRINTK("qc->flags = 0x%lx\n", qc->flags);

1269 1270
	nv_adma_tf_to_cpb(&qc->tf, cpb->tf);

1271 1272 1273 1274 1275
	if(qc->flags & ATA_QCFLAG_DMAMAP) {
		nv_adma_fill_sg(qc, cpb);
		ctl_flags |= NV_CPB_CTL_APRD_VALID;
	} else
		memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
1276 1277 1278 1279 1280

	/* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are
	   finished filling in all of the contents */
	wmb();
	cpb->ctl_flags = ctl_flags;
1281 1282
	wmb();
	cpb->resp_flags = 0;
1283 1284 1285 1286
}

static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
{
1287
	struct nv_adma_port_priv *pp = qc->ap->private_data;
1288
	void __iomem *mmio = pp->ctl_block;
1289
	int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
1290 1291 1292

	VPRINTK("ENTER\n");

1293
	if (nv_adma_use_reg_mode(qc)) {
1294
		/* use ATA register mode */
1295
		VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
1296 1297 1298 1299 1300 1301 1302 1303
		nv_adma_register_mode(qc->ap);
		return ata_qc_issue_prot(qc);
	} else
		nv_adma_mode(qc->ap);

	/* write append register, command tag in lower 8 bits
	   and (number of cpbs to append -1) in top 8 bits */
	wmb();
1304 1305 1306 1307 1308 1309 1310 1311

	if(curr_ncq != pp->last_issue_ncq) {
	   	/* Seems to need some delay before switching between NCQ and non-NCQ
		   commands, else we get command timeouts and such. */
		udelay(20);
		pp->last_issue_ncq = curr_ncq;
	}

1312 1313 1314 1315 1316 1317 1318
	writew(qc->tag, mmio + NV_ADMA_APPEND);

	DPRINTK("Issued tag %u\n",qc->tag);

	return 0;
}

1319
static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
L
Linus Torvalds 已提交
1320
{
J
Jeff Garzik 已提交
1321
	struct ata_host *host = dev_instance;
L
Linus Torvalds 已提交
1322 1323 1324 1325
	unsigned int i;
	unsigned int handled = 0;
	unsigned long flags;

J
Jeff Garzik 已提交
1326
	spin_lock_irqsave(&host->lock, flags);
L
Linus Torvalds 已提交
1327

J
Jeff Garzik 已提交
1328
	for (i = 0; i < host->n_ports; i++) {
L
Linus Torvalds 已提交
1329 1330
		struct ata_port *ap;

J
Jeff Garzik 已提交
1331
		ap = host->ports[i];
1332
		if (ap &&
J
Jeff Garzik 已提交
1333
		    !(ap->flags & ATA_FLAG_DISABLED)) {
L
Linus Torvalds 已提交
1334 1335
			struct ata_queued_cmd *qc;

T
Tejun Heo 已提交
1336
			qc = ata_qc_from_tag(ap, ap->link.active_tag);
1337
			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
L
Linus Torvalds 已提交
1338
				handled += ata_host_intr(ap, qc);
1339 1340 1341 1342
			else
				// No request pending?  Clear interrupt status
				// anyway, in case there's one pending.
				ap->ops->check_status(ap);
L
Linus Torvalds 已提交
1343 1344 1345 1346
		}

	}

J
Jeff Garzik 已提交
1347
	spin_unlock_irqrestore(&host->lock, flags);
L
Linus Torvalds 已提交
1348 1349 1350 1351

	return IRQ_RETVAL(handled);
}

J
Jeff Garzik 已提交
1352
static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
T
Tejun Heo 已提交
1353 1354 1355
{
	int i, handled = 0;

J
Jeff Garzik 已提交
1356 1357
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
T
Tejun Heo 已提交
1358 1359 1360 1361 1362 1363 1364 1365 1366 1367

		if (ap && !(ap->flags & ATA_FLAG_DISABLED))
			handled += nv_host_intr(ap, irq_stat);

		irq_stat >>= NV_INT_PORT_SHIFT;
	}

	return IRQ_RETVAL(handled);
}

1368
static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
T
Tejun Heo 已提交
1369
{
J
Jeff Garzik 已提交
1370
	struct ata_host *host = dev_instance;
T
Tejun Heo 已提交
1371 1372 1373
	u8 irq_stat;
	irqreturn_t ret;

J
Jeff Garzik 已提交
1374
	spin_lock(&host->lock);
T
Tejun Heo 已提交
1375
	irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
J
Jeff Garzik 已提交
1376 1377
	ret = nv_do_interrupt(host, irq_stat);
	spin_unlock(&host->lock);
T
Tejun Heo 已提交
1378 1379 1380 1381

	return ret;
}

1382
static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
T
Tejun Heo 已提交
1383
{
J
Jeff Garzik 已提交
1384
	struct ata_host *host = dev_instance;
T
Tejun Heo 已提交
1385 1386 1387
	u8 irq_stat;
	irqreturn_t ret;

J
Jeff Garzik 已提交
1388
	spin_lock(&host->lock);
T
Tejun Heo 已提交
1389
	irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
J
Jeff Garzik 已提交
1390 1391
	ret = nv_do_interrupt(host, irq_stat);
	spin_unlock(&host->lock);
T
Tejun Heo 已提交
1392 1393 1394 1395

	return ret;
}

1396
static int nv_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
L
Linus Torvalds 已提交
1397 1398
{
	if (sc_reg > SCR_CONTROL)
1399
		return -EINVAL;
L
Linus Torvalds 已提交
1400

1401 1402
	*val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
L
Linus Torvalds 已提交
1403 1404
}

1405
static int nv_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
L
Linus Torvalds 已提交
1406 1407
{
	if (sc_reg > SCR_CONTROL)
1408
		return -EINVAL;
L
Linus Torvalds 已提交
1409

T
Tejun Heo 已提交
1410
	iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
1411
	return 0;
L
Linus Torvalds 已提交
1412 1413
}

T
Tejun Heo 已提交
1414 1415
static void nv_nf2_freeze(struct ata_port *ap)
{
T
Tejun Heo 已提交
1416
	void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
T
Tejun Heo 已提交
1417 1418 1419
	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

T
Tejun Heo 已提交
1420
	mask = ioread8(scr_addr + NV_INT_ENABLE);
T
Tejun Heo 已提交
1421
	mask &= ~(NV_INT_ALL << shift);
T
Tejun Heo 已提交
1422
	iowrite8(mask, scr_addr + NV_INT_ENABLE);
T
Tejun Heo 已提交
1423 1424 1425 1426
}

static void nv_nf2_thaw(struct ata_port *ap)
{
T
Tejun Heo 已提交
1427
	void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
T
Tejun Heo 已提交
1428 1429 1430
	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

T
Tejun Heo 已提交
1431
	iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
T
Tejun Heo 已提交
1432

T
Tejun Heo 已提交
1433
	mask = ioread8(scr_addr + NV_INT_ENABLE);
T
Tejun Heo 已提交
1434
	mask |= (NV_INT_MASK << shift);
T
Tejun Heo 已提交
1435
	iowrite8(mask, scr_addr + NV_INT_ENABLE);
T
Tejun Heo 已提交
1436 1437 1438 1439
}

static void nv_ck804_freeze(struct ata_port *ap)
{
T
Tejun Heo 已提交
1440
	void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
T
Tejun Heo 已提交
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450
	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

	mask = readb(mmio_base + NV_INT_ENABLE_CK804);
	mask &= ~(NV_INT_ALL << shift);
	writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
}

static void nv_ck804_thaw(struct ata_port *ap)
{
T
Tejun Heo 已提交
1451
	void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
T
Tejun Heo 已提交
1452 1453 1454 1455 1456 1457 1458 1459 1460 1461
	int shift = ap->port_no * NV_INT_PORT_SHIFT;
	u8 mask;

	writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);

	mask = readb(mmio_base + NV_INT_ENABLE_CK804);
	mask |= (NV_INT_MASK << shift);
	writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
}

T
Tejun Heo 已提交
1462
static int nv_hardreset(struct ata_link *link, unsigned int *class,
1463
			unsigned long deadline)
T
Tejun Heo 已提交
1464 1465 1466 1467 1468 1469 1470
{
	unsigned int dummy;

	/* SATA hardreset fails to retrieve proper device signature on
	 * some controllers.  Don't classify on hardreset.  For more
	 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
	 */
T
Tejun Heo 已提交
1471
	return sata_std_hardreset(link, &dummy, deadline);
T
Tejun Heo 已提交
1472 1473 1474 1475 1476 1477 1478 1479
}

static void nv_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
			   nv_hardreset, ata_std_postreset);
}

1480 1481 1482 1483
static void nv_adma_error_handler(struct ata_port *ap)
{
	struct nv_adma_port_priv *pp = ap->private_data;
	if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
1484
		void __iomem *mmio = pp->ctl_block;
1485 1486
		int i;
		u16 tmp;
J
Jeff Garzik 已提交
1487

T
Tejun Heo 已提交
1488
		if(ata_tag_valid(ap->link.active_tag) || ap->link.sactive) {
1489 1490 1491 1492
			u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
			u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
			u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
			u32 status = readw(mmio + NV_ADMA_STAT);
1493 1494
			u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
			u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
1495 1496

			ata_port_printk(ap, KERN_ERR, "EH in ADMA mode, notifier 0x%X "
1497 1498 1499 1500
				"notifier_error 0x%X gen_ctl 0x%X status 0x%X "
				"next cpb count 0x%X next cpb idx 0x%x\n",
				notifier, notifier_error, gen_ctl, status,
				cpb_count, next_cpb_idx);
1501 1502 1503

			for( i=0;i<NV_ADMA_MAX_CPBS;i++) {
				struct nv_adma_cpb *cpb = &pp->cpb[i];
T
Tejun Heo 已提交
1504 1505
				if( (ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) ||
				    ap->link.sactive & (1 << i) )
1506 1507 1508 1509 1510
					ata_port_printk(ap, KERN_ERR,
						"CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
						i, cpb->ctl_flags, cpb->resp_flags);
			}
		}
1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524

		/* Push us back into port register mode for error handling. */
		nv_adma_register_mode(ap);

		/* Mark all of the CPBs as invalid to prevent them from being executed */
		for( i=0;i<NV_ADMA_MAX_CPBS;i++)
			pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;

		/* clear CPB fetch count */
		writew(0, mmio + NV_ADMA_CPB_COUNT);

		/* Reset channel */
		tmp = readw(mmio + NV_ADMA_CTL);
		writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1525
		readw( mmio + NV_ADMA_CTL );	/* flush posted write */
1526 1527
		udelay(1);
		writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1528
		readw( mmio + NV_ADMA_CTL );	/* flush posted write */
1529 1530 1531 1532 1533 1534
	}

	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
			   nv_hardreset, ata_std_postreset);
}

L
Linus Torvalds 已提交
1535 1536 1537
static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version = 0;
T
Tejun Heo 已提交
1538
	const struct ata_port_info *ppi[] = { NULL, NULL };
1539
	struct ata_host *host;
1540
	struct nv_host_priv *hpriv;
L
Linus Torvalds 已提交
1541 1542
	int rc;
	u32 bar;
T
Tejun Heo 已提交
1543
	void __iomem *base;
1544
	unsigned long type = ent->driver_data;
L
Linus Torvalds 已提交
1545 1546 1547 1548 1549 1550 1551 1552

        // Make sure this is a SATA controller by counting the number of bars
        // (NVIDIA SATA controllers will always have six bars).  Otherwise,
        // it's an IDE controller and we ignore it.
	for (bar=0; bar<6; bar++)
		if (pci_resource_start(pdev, bar) == 0)
			return -ENODEV;

1553
	if (!printed_version++)
1554
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
L
Linus Torvalds 已提交
1555

1556
	rc = pcim_enable_device(pdev);
L
Linus Torvalds 已提交
1557
	if (rc)
1558
		return rc;
L
Linus Torvalds 已提交
1559

1560 1561
	/* determine type and allocate host */
	if (type >= CK804 && adma_enabled) {
1562 1563 1564 1565
		dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
		type = ADMA;
	}

T
Tejun Heo 已提交
1566
	ppi[0] = &nv_port_info[type];
1567
	rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
1568 1569
	if (rc)
		return rc;
L
Linus Torvalds 已提交
1570

1571
	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1572
	if (!hpriv)
1573
		return -ENOMEM;
1574 1575
	hpriv->type = type;
	host->private_data = hpriv;
1576

1577 1578 1579 1580 1581
	/* set 64bit dma masks, may fail */
	if (type == ADMA) {
		if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0)
			pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
	}
L
Linus Torvalds 已提交
1582

1583 1584 1585 1586
	/* request and iomap NV_MMIO_BAR */
	rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
	if (rc)
		return rc;
L
Linus Torvalds 已提交
1587

1588 1589 1590 1591
	/* configure SCR access */
	base = host->iomap[NV_MMIO_BAR];
	host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
	host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
L
Linus Torvalds 已提交
1592

T
Tejun Heo 已提交
1593
	/* enable SATA space for CK804 */
1594
	if (type >= CK804) {
T
Tejun Heo 已提交
1595 1596 1597 1598 1599 1600 1601
		u8 regval;

		pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
		regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
		pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
	}

1602
	/* init ADMA */
1603
	if (type == ADMA) {
1604
		rc = nv_adma_host_init(host);
1605
		if (rc)
1606
			return rc;
1607 1608
	}

1609 1610 1611
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler,
				 IRQF_SHARED, ppi[0]->sht);
L
Linus Torvalds 已提交
1612 1613
}

1614
#ifdef CONFIG_PM
1615 1616 1617 1618
static int nv_pci_device_resume(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct nv_host_priv *hpriv = host->private_data;
1619
	int rc;
1620

1621 1622 1623
	rc = ata_pci_device_do_resume(pdev);
	if(rc)
		return rc;
1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661

	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
		if(hpriv->type >= CK804) {
			u8 regval;

			pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
			regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
			pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
		}
		if(hpriv->type == ADMA) {
			u32 tmp32;
			struct nv_adma_port_priv *pp;
			/* enable/disable ADMA on the ports appropriately */
			pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);

			pp = host->ports[0]->private_data;
			if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
				tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
				 	   NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
			else
				tmp32 |=  (NV_MCP_SATA_CFG_20_PORT0_EN |
				 	   NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
			pp = host->ports[1]->private_data;
			if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
				tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
				 	   NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
			else
				tmp32 |=  (NV_MCP_SATA_CFG_20_PORT1_EN |
				 	   NV_MCP_SATA_CFG_20_PORT1_PWB_EN);

			pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
		}
	}

	ata_host_resume(host);

	return 0;
}
1662
#endif
1663

J
Jeff Garzik 已提交
1664
static void nv_ck804_host_stop(struct ata_host *host)
T
Tejun Heo 已提交
1665
{
J
Jeff Garzik 已提交
1666
	struct pci_dev *pdev = to_pci_dev(host->dev);
T
Tejun Heo 已提交
1667 1668 1669 1670 1671 1672 1673 1674
	u8 regval;

	/* disable SATA space for CK804 */
	pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
	regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
	pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
}

1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691
static void nv_adma_host_stop(struct ata_host *host)
{
	struct pci_dev *pdev = to_pci_dev(host->dev);
	u32 tmp32;

	/* disable ADMA on the ports */
	pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
	tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
		   NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
		   NV_MCP_SATA_CFG_20_PORT1_EN |
		   NV_MCP_SATA_CFG_20_PORT1_PWB_EN);

	pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);

	nv_ck804_host_stop(host);
}

L
Linus Torvalds 已提交
1692 1693
static int __init nv_init(void)
{
1694
	return pci_register_driver(&nv_pci_driver);
L
Linus Torvalds 已提交
1695 1696 1697 1698 1699 1700 1701 1702 1703
}

static void __exit nv_exit(void)
{
	pci_unregister_driver(&nv_pci_driver);
}

module_init(nv_init);
module_exit(nv_exit);
1704 1705
module_param_named(adma, adma_enabled, bool, 0444);
MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");